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1 /*
2 * QEMU model of the Xilinx Zynq Double Data Rate Controller
3 *
4 * Copyright (c) Beckhoff Automation GmbH. & Co. KG
5 *
6 * SPDX-License-Identifier: GPL-2.0-or-later
7 */
8
9 #ifndef XLNX_ZYNQ_DDRC_H
10 #define XLNX_ZYNQ_DDRC_H
11
12 #include "hw/core/sysbus.h"
13 #include "hw/core/register.h"
14
15 #define TYPE_DDRCTRL "zynq.ddr-ctlr"
16 OBJECT_DECLARE_SIMPLE_TYPE(DDRCTRLState, DDRCTRL)
17
18 REG32(DDRC_CTRL, 0x00)
19 REG32(TWO_RANK_CFG, 0x04)
20 REG32(HPR_REG, 0x08)
21 REG32(LPR_REG, 0x0C)
22 REG32(WR_REG, 0x10)
23 REG32(DRAM_PARAM_REG0, 0x14)
24 REG32(DRAM_PARAM_REG1, 0x18)
25 REG32(DRAM_PARAM_REG2, 0x1C)
26 REG32(DRAM_PARAM_REG3, 0x20)
27 REG32(DRAM_PARAM_REG4, 0x24)
28 REG32(DRAM_INIT_PARAM, 0x28)
29 REG32(DRAM_EMR_REG, 0x2C)
30 REG32(DRAM_EMR_MR_REG, 0x30)
31 REG32(DRAM_BURST8_RDWR, 0x34)
32 REG32(DRAM_DISABLE_DQ, 0x38)
33 REG32(DRAM_ADDR_MAP_BANK, 0x3C)
34 REG32(DRAM_ADDR_MAP_COL, 0x40)
35 REG32(DRAM_ADDR_MAP_ROW, 0x44)
36 REG32(DRAM_ODT_REG, 0x48)
37 REG32(PHY_DBG_REG, 0x4C)
38 REG32(PHY_CMD_TIMEOUT_RDDATA_CPT, 0x50)
39 REG32(MODE_STS_REG, 0x54)
40 FIELD(MODE_STS_REG, DDR_REG_DBG_STALL, 3, 3)
41 FIELD(MODE_STS_REG, DDR_REG_OPERATING_MODE, 0, 2)
42 REG32(DLL_CALIB, 0x58)
43 REG32(ODT_DELAY_HOLD, 0x5C)
44 REG32(CTRL_REG1, 0x60)
45 REG32(CTRL_REG2, 0x64)
46 REG32(CTRL_REG3, 0x68)
47 REG32(CTRL_REG4, 0x6C)
48 REG32(CTRL_REG5, 0x78)
49 REG32(CTRL_REG6, 0x7C)
50 REG32(CHE_REFRESH_TIMER0, 0xA0)
51 REG32(CHE_T_ZQ, 0xA4)
52 REG32(CHE_T_ZQ_SHORT_INTERVAL_REG, 0xA8)
53 REG32(DEEP_PWRDWN_REG, 0xAC)
54 REG32(REG_2C, 0xB0)
55 REG32(REG_2D, 0xB4)
56 REG32(DFI_TIMING, 0xB8)
57 REG32(CHE_ECC_CONTROL_REG_OFFSET, 0xC4)
58 REG32(CHE_CORR_ECC_LOG_REG_OFFSET, 0xC8)
59 REG32(CHE_CORR_ECC_ADDR_REG_OFFSET, 0xCC)
60 REG32(CHE_CORR_ECC_DATA_31_0_REG_OFFSET, 0xD0)
61 REG32(CHE_CORR_ECC_DATA_63_32_REG_OFFSET, 0xD4)
62 REG32(CHE_CORR_ECC_DATA_71_64_REG_OFFSET, 0xD8)
63 REG32(CHE_UNCORR_ECC_LOG_REG_OFFSET, 0xDC)
64 REG32(CHE_UNCORR_ECC_ADDR_REG_OFFSET, 0xE0)
65 REG32(CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET, 0xE4)
66 REG32(CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET, 0xE8)
67 REG32(CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET, 0xEC)
68 REG32(CHE_ECC_STATS_REG_OFFSET, 0xF0)
69 REG32(ECC_SCRUB, 0xF4)
70 REG32(CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET, 0xF8)
71 REG32(CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET, 0xFC)
72 REG32(PHY_RCVER_ENABLE, 0x114)
73 REG32(PHY_CONFIG0, 0x118)
74 REG32(PHY_CONFIG1, 0x11C)
75 REG32(PHY_CONFIG2, 0x120)
76 REG32(PHY_CONFIG3, 0x124)
77 REG32(PHY_INIT_RATIO0, 0x12C)
78 REG32(PHY_INIT_RATIO1, 0x130)
79 REG32(PHY_INIT_RATIO2, 0x134)
80 REG32(PHY_INIT_RATIO3, 0x138)
81 REG32(PHY_RD_DQS_CFG0, 0x140)
82 REG32(PHY_RD_DQS_CFG1, 0x144)
83 REG32(PHY_RD_DQS_CFG2, 0x148)
84 REG32(PHY_RD_DQS_CFG3, 0x14C)
85 REG32(PHY_WR_DQS_CFG0, 0x154)
86 REG32(PHY_WR_DQS_CFG1, 0x158)
87 REG32(PHY_WR_DQS_CFG2, 0x15C)
88 REG32(PHY_WR_DQS_CFG3, 0x160)
89 REG32(PHY_WE_CFG0, 0x168)
90 REG32(PHY_WE_CFG1, 0x16C)
91 REG32(PHY_WE_CFG2, 0x170)
92 REG32(PHY_WE_CFG3, 0x174)
93 REG32(WR_DATA_SLV0, 0x17C)
94 REG32(WR_DATA_SLV1, 0x180)
95 REG32(WR_DATA_SLV2, 0x184)
96 REG32(WR_DATA_SLV3, 0x188)
97 REG32(REG_64, 0x190)
98 REG32(REG_65, 0x194)
99 REG32(REG69_6A0, 0x1A4)
100 REG32(REG69_6A1, 0x1A8)
101 REG32(REG6C_6D2, 0x1B0)
102 REG32(REG6C_6D3, 0x1B4)
103 REG32(REG6E_710, 0x1B8)
104 REG32(REG6E_711, 0x1BC)
105 REG32(REG6E_712, 0x1C0)
106 REG32(REG6E_713, 0x1C4)
107 REG32(PHY_DLL_STS0, 0x1CC)
108 REG32(PHY_DLL_STS1, 0x1D0)
109 REG32(PHY_DLL_STS2, 0x1D4)
110 REG32(PHY_DLL_STS3, 0x1D8)
111 REG32(DLL_LOCK_STS, 0x1E0)
112 REG32(PHY_CTRL_STS, 0x1E4)
113 REG32(PHY_CTRL_STS_REG2, 0x1E8)
114 REG32(AXI_ID, 0x200)
115 REG32(PAGE_MASK, 0x204)
116 REG32(AXI_PRIORITY_WR_PORT0, 0x208)
117 REG32(AXI_PRIORITY_WR_PORT1, 0x20C)
118 REG32(AXI_PRIORITY_WR_PORT2, 0x210)
119 REG32(AXI_PRIORITY_WR_PORT3, 0x214)
120 REG32(AXI_PRIORITY_RD_PORT0, 0x218)
121 REG32(AXI_PRIORITY_RD_PORT1, 0x21C)
122 REG32(AXI_PRIORITY_RD_PORT2, 0x220)
123 REG32(AXI_PRIORITY_RD_PORT3, 0x224)
124 REG32(EXCL_ACCESS_CFG0, 0x294)
125 REG32(EXCL_ACCESS_CFG1, 0x298)
126 REG32(EXCL_ACCESS_CFG2, 0x29C)
127 REG32(EXCL_ACCESS_CFG3, 0x2A0)
128 REG32(MODE_REG_READ, 0x2A4)
129 REG32(LPDDR_CTRL0, 0x2A8)
130 REG32(LPDDR_CTRL1, 0x2AC)
131 REG32(LPDDR_CTRL2, 0x2B0)
132 REG32(LPDDR_CTRL3, 0x2B4)
133
134
135 #define ZYNQ_DDRCTRL_MMIO_SIZE 0x400
136 #define ZYNQ_DDRCTRL_NUM_REG (ZYNQ_DDRCTRL_MMIO_SIZE / 4)
137
138 typedef struct DDRCTRLState {
139 SysBusDevice parent_obj;
140
141 MemoryRegion iomem;
142
143 RegisterInfoArray *reg_array;
144 uint32_t reg[ZYNQ_DDRCTRL_NUM_REG];
145 RegisterInfo regs_info[ZYNQ_DDRCTRL_NUM_REG];
146 } DDRCTRLState;
147 #endif