| 1 | /* |
| 2 | * QEMU Cadence GEM emulation |
| 3 | * |
| 4 | * Copyright (c) 2011 Xilinx, Inc. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to deal |
| 8 | * in the Software without restriction, including without limitation the rights |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 10 | * copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. |
| 23 | */ |
| 24 | |
| 25 | #ifndef CADENCE_GEM_H |
| 26 | #define CADENCE_GEM_H |
| 27 | #include "qom/object.h" |
| 28 | |
| 29 | #define TYPE_CADENCE_GEM "cadence_gem" |
| 30 | OBJECT_DECLARE_SIMPLE_TYPE(CadenceGEMState, CADENCE_GEM) |
| 31 | |
| 32 | #include "net/net.h" |
| 33 | #include "hw/core/sysbus.h" |
| 34 | |
| 35 | #define CADENCE_GEM_MAXREG (0x00000800 / 4) /* Last valid GEM address */ |
| 36 | |
| 37 | /* Max number of words in a DMA descriptor. */ |
| 38 | #define DESC_MAX_NUM_WORDS 6 |
| 39 | |
| 40 | #define MAX_PRIORITY_QUEUES 8 |
| 41 | #define MAX_TYPE1_SCREENERS 16 |
| 42 | #define MAX_TYPE2_SCREENERS 16 |
| 43 | |
| 44 | #define MAX_JUMBO_FRAME_SIZE_MASK 0x3FFF |
| 45 | #define MAX_FRAME_SIZE MAX_JUMBO_FRAME_SIZE_MASK |
| 46 | |
| 47 | struct CadenceGEMState { |
| 48 | /*< private >*/ |
| 49 | SysBusDevice parent_obj; |
| 50 | |
| 51 | /*< public >*/ |
| 52 | MemoryRegion iomem; |
| 53 | MemoryRegion *dma_mr; |
| 54 | AddressSpace dma_as; |
| 55 | NICState *nic; |
| 56 | NICConf conf; |
| 57 | qemu_irq irq[MAX_PRIORITY_QUEUES]; |
| 58 | |
| 59 | /* Static properties */ |
| 60 | uint8_t num_priority_queues; |
| 61 | uint8_t num_type1_screeners; |
| 62 | uint8_t num_type2_screeners; |
| 63 | uint32_t revision; |
| 64 | uint16_t jumbo_max_len; |
| 65 | bool pcs_enabled; |
| 66 | |
| 67 | /* GEM registers backing store */ |
| 68 | uint32_t regs[CADENCE_GEM_MAXREG]; |
| 69 | /* Mask of register bits which are write only */ |
| 70 | uint32_t regs_wo[CADENCE_GEM_MAXREG]; |
| 71 | /* Mask of register bits which are read only */ |
| 72 | uint32_t regs_ro[CADENCE_GEM_MAXREG]; |
| 73 | /* Mask of register bits which are clear on read */ |
| 74 | uint32_t regs_rtc[CADENCE_GEM_MAXREG]; |
| 75 | /* Mask of register bits which are write 1 to clear */ |
| 76 | uint32_t regs_w1c[CADENCE_GEM_MAXREG]; |
| 77 | |
| 78 | /* PHY address */ |
| 79 | uint8_t phy_addr; |
| 80 | /* PHY registers backing store */ |
| 81 | uint16_t phy_regs[32]; |
| 82 | |
| 83 | uint8_t phy_loop; /* Are we in phy loopback? */ |
| 84 | |
| 85 | bool phy_connected; /* true if connected */ |
| 86 | struct CadenceGEMState *phy_consumer; |
| 87 | |
| 88 | /* The current DMA descriptor pointers */ |
| 89 | uint32_t rx_desc_addr[MAX_PRIORITY_QUEUES]; |
| 90 | uint32_t tx_desc_addr[MAX_PRIORITY_QUEUES]; |
| 91 | |
| 92 | uint8_t can_rx_state; /* Debug only */ |
| 93 | |
| 94 | uint8_t tx_packet[MAX_FRAME_SIZE]; |
| 95 | uint8_t rx_packet[MAX_FRAME_SIZE]; |
| 96 | uint32_t rx_desc[MAX_PRIORITY_QUEUES][DESC_MAX_NUM_WORDS]; |
| 97 | |
| 98 | bool sar_active[4]; |
| 99 | }; |
| 100 | |
| 101 | #endif |