| 1 | /* |
| 2 | * Nuvoton NPCM7xx/8xx GMAC Module |
| 3 | * |
| 4 | * Copyright 2024 Google LLC |
| 5 | * Authors: |
| 6 | * Hao Wu <wuhaotsh@google.com> |
| 7 | * Nabih Estefan <nabihestefan@google.com> |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify it |
| 10 | * under the terms of the GNU General Public License as published by the |
| 11 | * Free Software Foundation; either version 2 of the License, or |
| 12 | * (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 17 | * for more details. |
| 18 | */ |
| 19 | |
| 20 | #ifndef NPCM_GMAC_H |
| 21 | #define NPCM_GMAC_H |
| 22 | |
| 23 | #include "hw/core/irq.h" |
| 24 | #include "hw/core/sysbus.h" |
| 25 | #include "net/net.h" |
| 26 | |
| 27 | #define NPCM_GMAC_REG_SIZE 0x1060 |
| 28 | #define NPCM_GMAC_NR_REGS (NPCM_GMAC_REG_SIZE / sizeof(uint32_t)) |
| 29 | |
| 30 | #define NPCM_GMAC_MAX_PHYS 32 |
| 31 | #define NPCM_GMAC_MAX_PHY_REGS 32 |
| 32 | |
| 33 | struct NPCMGMACRxDesc { |
| 34 | uint32_t rdes0; |
| 35 | uint32_t rdes1; |
| 36 | uint32_t rdes2; |
| 37 | uint32_t rdes3; |
| 38 | }; |
| 39 | |
| 40 | /* NPCMGMACRxDesc.flags values */ |
| 41 | /* RDES2 and RDES3 are buffer addresses */ |
| 42 | /* Owner: 0 = software, 1 = dma */ |
| 43 | #define RX_DESC_RDES0_OWN BIT(31) |
| 44 | /* Destination Address Filter Fail */ |
| 45 | #define RX_DESC_RDES0_DEST_ADDR_FILT_FAIL BIT(30) |
| 46 | /* Frame length */ |
| 47 | #define RX_DESC_RDES0_FRAME_LEN_MASK(word) extract32(word, 16, 14) |
| 48 | /* Frame length Shift*/ |
| 49 | #define RX_DESC_RDES0_FRAME_LEN_SHIFT 16 |
| 50 | /* Error Summary */ |
| 51 | #define RX_DESC_RDES0_ERR_SUMM_MASK BIT(15) |
| 52 | /* Descriptor Error */ |
| 53 | #define RX_DESC_RDES0_DESC_ERR_MASK BIT(14) |
| 54 | /* Source Address Filter Fail */ |
| 55 | #define RX_DESC_RDES0_SRC_ADDR_FILT_FAIL_MASK BIT(13) |
| 56 | /* Length Error */ |
| 57 | #define RX_DESC_RDES0_LEN_ERR_MASK BIT(12) |
| 58 | /* Overflow Error */ |
| 59 | #define RX_DESC_RDES0_OVRFLW_ERR_MASK BIT(11) |
| 60 | /* VLAN Tag */ |
| 61 | #define RX_DESC_RDES0_VLAN_TAG_MASK BIT(10) |
| 62 | /* First Descriptor */ |
| 63 | #define RX_DESC_RDES0_FIRST_DESC_MASK BIT(9) |
| 64 | /* Last Descriptor */ |
| 65 | #define RX_DESC_RDES0_LAST_DESC_MASK BIT(8) |
| 66 | /* IPC Checksum Error/Giant Frame */ |
| 67 | #define RX_DESC_RDES0_IPC_CHKSM_ERR_GNT_FRM_MASK BIT(7) |
| 68 | /* Late Collision */ |
| 69 | #define RX_DESC_RDES0_LT_COLL_MASK BIT(6) |
| 70 | /* Frame Type */ |
| 71 | #define RX_DESC_RDES0_FRM_TYPE_MASK BIT(5) |
| 72 | /* Receive Watchdog Timeout */ |
| 73 | #define RX_DESC_RDES0_REC_WTCHDG_TMT_MASK BIT(4) |
| 74 | /* Receive Error */ |
| 75 | #define RX_DESC_RDES0_RCV_ERR_MASK BIT(3) |
| 76 | /* Dribble Bit Error */ |
| 77 | #define RX_DESC_RDES0_DRBL_BIT_ERR_MASK BIT(2) |
| 78 | /* Cyclcic Redundancy Check Error */ |
| 79 | #define RX_DESC_RDES0_CRC_ERR_MASK BIT(1) |
| 80 | /* Rx MAC Address/Payload Checksum Error */ |
| 81 | #define RC_DESC_RDES0_RCE_MASK BIT(0) |
| 82 | |
| 83 | /* Disable Interrupt on Completion */ |
| 84 | #define RX_DESC_RDES1_DIS_INTR_COMP_MASK BIT(31) |
| 85 | /* Receive end of ring */ |
| 86 | #define RX_DESC_RDES1_RC_END_RING_MASK BIT(25) |
| 87 | /* Second Address Chained */ |
| 88 | #define RX_DESC_RDES1_SEC_ADDR_CHND_MASK BIT(24) |
| 89 | /* Receive Buffer 2 Size */ |
| 90 | #define RX_DESC_RDES1_BFFR2_SZ_SHIFT 11 |
| 91 | #define RX_DESC_RDES1_BFFR2_SZ_MASK(word) extract32(word, \ |
| 92 | RX_DESC_RDES1_BFFR2_SZ_SHIFT, 11) |
| 93 | /* Receive Buffer 1 Size */ |
| 94 | #define RX_DESC_RDES1_BFFR1_SZ_MASK(word) extract32(word, 0, 11) |
| 95 | |
| 96 | |
| 97 | struct NPCMGMACTxDesc { |
| 98 | uint32_t tdes0; |
| 99 | uint32_t tdes1; |
| 100 | uint32_t tdes2; |
| 101 | uint32_t tdes3; |
| 102 | }; |
| 103 | |
| 104 | /* NPCMGMACTxDesc.flags values */ |
| 105 | /* TDES2 and TDES3 are buffer addresses */ |
| 106 | /* Owner: 0 = software, 1 = gmac */ |
| 107 | #define TX_DESC_TDES0_OWN BIT(31) |
| 108 | /* Tx Time Stamp Status */ |
| 109 | #define TX_DESC_TDES0_TTSS_MASK BIT(17) |
| 110 | /* IP Header Error */ |
| 111 | #define TX_DESC_TDES0_IP_HEAD_ERR_MASK BIT(16) |
| 112 | /* Error Summary */ |
| 113 | #define TX_DESC_TDES0_ERR_SUMM_MASK BIT(15) |
| 114 | /* Jabber Timeout */ |
| 115 | #define TX_DESC_TDES0_JBBR_TMT_MASK BIT(14) |
| 116 | /* Frame Flushed */ |
| 117 | #define TX_DESC_TDES0_FRM_FLSHD_MASK BIT(13) |
| 118 | /* Payload Checksum Error */ |
| 119 | #define TX_DESC_TDES0_PYLD_CHKSM_ERR_MASK BIT(12) |
| 120 | /* Loss of Carrier */ |
| 121 | #define TX_DESC_TDES0_LSS_CARR_MASK BIT(11) |
| 122 | /* No Carrier */ |
| 123 | #define TX_DESC_TDES0_NO_CARR_MASK BIT(10) |
| 124 | /* Late Collision */ |
| 125 | #define TX_DESC_TDES0_LATE_COLL_MASK BIT(9) |
| 126 | /* Excessive Collision */ |
| 127 | #define TX_DESC_TDES0_EXCS_COLL_MASK BIT(8) |
| 128 | /* VLAN Frame */ |
| 129 | #define TX_DESC_TDES0_VLAN_FRM_MASK BIT(7) |
| 130 | /* Collision Count */ |
| 131 | #define TX_DESC_TDES0_COLL_CNT_MASK(word) extract32(word, 3, 4) |
| 132 | /* Excessive Deferral */ |
| 133 | #define TX_DESC_TDES0_EXCS_DEF_MASK BIT(2) |
| 134 | /* Underflow Error */ |
| 135 | #define TX_DESC_TDES0_UNDRFLW_ERR_MASK BIT(1) |
| 136 | /* Deferred Bit */ |
| 137 | #define TX_DESC_TDES0_DFRD_BIT_MASK BIT(0) |
| 138 | |
| 139 | /* Interrupt of Completion */ |
| 140 | #define TX_DESC_TDES1_INTERR_COMP_MASK BIT(31) |
| 141 | /* Last Segment */ |
| 142 | #define TX_DESC_TDES1_LAST_SEG_MASK BIT(30) |
| 143 | /* First Segment */ |
| 144 | #define TX_DESC_TDES1_FIRST_SEG_MASK BIT(29) |
| 145 | /* Checksum Insertion Control */ |
| 146 | #define TX_DESC_TDES1_CHKSM_INS_CTRL_MASK(word) extract32(word, 27, 2) |
| 147 | /* Disable Cyclic Redundancy Check */ |
| 148 | #define TX_DESC_TDES1_DIS_CDC_MASK BIT(26) |
| 149 | /* Transmit End of Ring */ |
| 150 | #define TX_DESC_TDES1_TX_END_RING_MASK BIT(25) |
| 151 | /* Secondary Address Chained */ |
| 152 | #define TX_DESC_TDES1_SEC_ADDR_CHND_MASK BIT(24) |
| 153 | /* Transmit Buffer 2 Size */ |
| 154 | #define TX_DESC_TDES1_BFFR2_SZ_MASK(word) extract32(word, 11, 11) |
| 155 | /* Transmit Buffer 1 Size */ |
| 156 | #define TX_DESC_TDES1_BFFR1_SZ_MASK(word) extract32(word, 0, 11) |
| 157 | |
| 158 | typedef struct NPCMGMACState { |
| 159 | SysBusDevice parent; |
| 160 | |
| 161 | MemoryRegion iomem; |
| 162 | qemu_irq irq; |
| 163 | |
| 164 | NICState *nic; |
| 165 | NICConf conf; |
| 166 | |
| 167 | uint32_t regs[NPCM_GMAC_NR_REGS]; |
| 168 | uint16_t phy_regs[NPCM_GMAC_MAX_PHYS][NPCM_GMAC_MAX_PHY_REGS]; |
| 169 | } NPCMGMACState; |
| 170 | |
| 171 | #define TYPE_NPCM_GMAC "npcm-gmac" |
| 172 | OBJECT_DECLARE_SIMPLE_TYPE(NPCMGMACState, NPCM_GMAC) |
| 173 | |
| 174 | /* Mask for RO bits in Status */ |
| 175 | #define NPCM_DMA_STATUS_RO_MASK(word) (word & 0xfffe0000) |
| 176 | /* Mask for RO bits in Status */ |
| 177 | #define NPCM_DMA_STATUS_W1C_MASK(word) (word & 0x1e7ff) |
| 178 | |
| 179 | /* Transmit Process State */ |
| 180 | #define NPCM_DMA_STATUS_TX_PROCESS_STATE_SHIFT 20 |
| 181 | /* Transmit States */ |
| 182 | #define NPCM_DMA_STATUS_TX_STOPPED_STATE \ |
| 183 | (0b000) |
| 184 | #define NPCM_DMA_STATUS_TX_RUNNING_FETCHING_STATE \ |
| 185 | (0b001) |
| 186 | #define NPCM_DMA_STATUS_TX_RUNNING_WAITING_STATE \ |
| 187 | (0b010) |
| 188 | #define NPCM_DMA_STATUS_TX_RUNNING_READ_STATE \ |
| 189 | (0b011) |
| 190 | #define NPCM_DMA_STATUS_TX_SUSPENDED_STATE \ |
| 191 | (0b110) |
| 192 | #define NPCM_DMA_STATUS_TX_RUNNING_CLOSING_STATE \ |
| 193 | (0b111) |
| 194 | /* Transmit Process State */ |
| 195 | #define NPCM_DMA_STATUS_RX_PROCESS_STATE_SHIFT 17 |
| 196 | /* Receive States */ |
| 197 | #define NPCM_DMA_STATUS_RX_STOPPED_STATE \ |
| 198 | (0b000) |
| 199 | #define NPCM_DMA_STATUS_RX_RUNNING_FETCHING_STATE \ |
| 200 | (0b001) |
| 201 | #define NPCM_DMA_STATUS_RX_RUNNING_WAITING_STATE \ |
| 202 | (0b011) |
| 203 | #define NPCM_DMA_STATUS_RX_SUSPENDED_STATE \ |
| 204 | (0b100) |
| 205 | #define NPCM_DMA_STATUS_RX_RUNNING_CLOSING_STATE \ |
| 206 | (0b101) |
| 207 | #define NPCM_DMA_STATUS_RX_RUNNING_TRANSFERRING_STATE \ |
| 208 | (0b111) |
| 209 | |
| 210 | |
| 211 | /* Early Receive Interrupt */ |
| 212 | #define NPCM_DMA_STATUS_ERI BIT(14) |
| 213 | /* Fatal Bus Error Interrupt */ |
| 214 | #define NPCM_DMA_STATUS_FBI BIT(13) |
| 215 | /* Early transmit Interrupt */ |
| 216 | #define NPCM_DMA_STATUS_ETI BIT(10) |
| 217 | /* Receive Watchdog Timeout */ |
| 218 | #define NPCM_DMA_STATUS_RWT BIT(9) |
| 219 | /* Receive Process Stopped */ |
| 220 | #define NPCM_DMA_STATUS_RPS BIT(8) |
| 221 | /* Receive Buffer Unavailable */ |
| 222 | #define NPCM_DMA_STATUS_RU BIT(7) |
| 223 | /* Receive Interrupt */ |
| 224 | #define NPCM_DMA_STATUS_RI BIT(6) |
| 225 | /* Transmit Underflow */ |
| 226 | #define NPCM_DMA_STATUS_UNF BIT(5) |
| 227 | /* Receive Overflow */ |
| 228 | #define NPCM_DMA_STATUS_OVF BIT(4) |
| 229 | /* Transmit Jabber Timeout */ |
| 230 | #define NPCM_DMA_STATUS_TJT BIT(3) |
| 231 | /* Transmit Buffer Unavailable */ |
| 232 | #define NPCM_DMA_STATUS_TU BIT(2) |
| 233 | /* Transmit Process Stopped */ |
| 234 | #define NPCM_DMA_STATUS_TPS BIT(1) |
| 235 | /* Transmit Interrupt */ |
| 236 | #define NPCM_DMA_STATUS_TI BIT(0) |
| 237 | |
| 238 | /* Normal Interrupt Summary */ |
| 239 | #define NPCM_DMA_STATUS_NIS BIT(16) |
| 240 | /* Interrupts enabled by NIE */ |
| 241 | #define NPCM_DMA_STATUS_NIS_BITS (NPCM_DMA_STATUS_TI | \ |
| 242 | NPCM_DMA_STATUS_TU | \ |
| 243 | NPCM_DMA_STATUS_RI | \ |
| 244 | NPCM_DMA_STATUS_ERI) |
| 245 | /* Abnormal Interrupt Summary */ |
| 246 | #define NPCM_DMA_STATUS_AIS BIT(15) |
| 247 | /* Interrupts enabled by AIE */ |
| 248 | #define NPCM_DMA_STATUS_AIS_BITS (NPCM_DMA_STATUS_TPS | \ |
| 249 | NPCM_DMA_STATUS_TJT | \ |
| 250 | NPCM_DMA_STATUS_OVF | \ |
| 251 | NPCM_DMA_STATUS_UNF | \ |
| 252 | NPCM_DMA_STATUS_RU | \ |
| 253 | NPCM_DMA_STATUS_RPS | \ |
| 254 | NPCM_DMA_STATUS_RWT | \ |
| 255 | NPCM_DMA_STATUS_ETI | \ |
| 256 | NPCM_DMA_STATUS_FBI) |
| 257 | |
| 258 | /* Early Receive Interrupt Enable */ |
| 259 | #define NPCM_DMA_INTR_ENAB_ERE BIT(14) |
| 260 | /* Fatal Bus Error Interrupt Enable */ |
| 261 | #define NPCM_DMA_INTR_ENAB_FBE BIT(13) |
| 262 | /* Early transmit Interrupt Enable */ |
| 263 | #define NPCM_DMA_INTR_ENAB_ETE BIT(10) |
| 264 | /* Receive Watchdog Timout Enable */ |
| 265 | #define NPCM_DMA_INTR_ENAB_RWE BIT(9) |
| 266 | /* Receive Process Stopped Enable */ |
| 267 | #define NPCM_DMA_INTR_ENAB_RSE BIT(8) |
| 268 | /* Receive Buffer Unavailable Enable */ |
| 269 | #define NPCM_DMA_INTR_ENAB_RUE BIT(7) |
| 270 | /* Receive Interrupt Enable */ |
| 271 | #define NPCM_DMA_INTR_ENAB_RIE BIT(6) |
| 272 | /* Transmit Underflow Enable */ |
| 273 | #define NPCM_DMA_INTR_ENAB_UNE BIT(5) |
| 274 | /* Receive Overflow Enable */ |
| 275 | #define NPCM_DMA_INTR_ENAB_OVE BIT(4) |
| 276 | /* Transmit Jabber Timeout Enable */ |
| 277 | #define NPCM_DMA_INTR_ENAB_TJE BIT(3) |
| 278 | /* Transmit Buffer Unavailable Enable */ |
| 279 | #define NPCM_DMA_INTR_ENAB_TUE BIT(2) |
| 280 | /* Transmit Process Stopped Enable */ |
| 281 | #define NPCM_DMA_INTR_ENAB_TSE BIT(1) |
| 282 | /* Transmit Interrupt Enable */ |
| 283 | #define NPCM_DMA_INTR_ENAB_TIE BIT(0) |
| 284 | |
| 285 | /* Normal Interrupt Summary Enable */ |
| 286 | #define NPCM_DMA_INTR_ENAB_NIE BIT(16) |
| 287 | /* Interrupts enabled by NIE Enable */ |
| 288 | #define NPCM_DMA_INTR_ENAB_NIE_BITS (NPCM_DMA_INTR_ENAB_TIE | \ |
| 289 | NPCM_DMA_INTR_ENAB_TUE | \ |
| 290 | NPCM_DMA_INTR_ENAB_RIE | \ |
| 291 | NPCM_DMA_INTR_ENAB_ERE) |
| 292 | /* Abnormal Interrupt Summary Enable */ |
| 293 | #define NPCM_DMA_INTR_ENAB_AIE BIT(15) |
| 294 | /* Interrupts enabled by AIE Enable */ |
| 295 | #define NPCM_DMA_INTR_ENAB_AIE_BITS (NPCM_DMA_INTR_ENAB_TSE | \ |
| 296 | NPCM_DMA_INTR_ENAB_TJE | \ |
| 297 | NPCM_DMA_INTR_ENAB_OVE | \ |
| 298 | NPCM_DMA_INTR_ENAB_UNE | \ |
| 299 | NPCM_DMA_INTR_ENAB_RUE | \ |
| 300 | NPCM_DMA_INTR_ENAB_RSE | \ |
| 301 | NPCM_DMA_INTR_ENAB_RWE | \ |
| 302 | NPCM_DMA_INTR_ENAB_ETE | \ |
| 303 | NPCM_DMA_INTR_ENAB_FBE) |
| 304 | |
| 305 | /* Flushing Disabled */ |
| 306 | #define NPCM_DMA_CONTROL_FLUSH_MASK BIT(24) |
| 307 | /* Start/stop Transmit */ |
| 308 | #define NPCM_DMA_CONTROL_START_STOP_TX BIT(13) |
| 309 | /* Start/stop Receive */ |
| 310 | #define NPCM_DMA_CONTROL_START_STOP_RX BIT(1) |
| 311 | /* Next receive descriptor start address */ |
| 312 | #define NPCM_DMA_HOST_RX_DESC_MASK(word) ((uint32_t) (word) & ~3u) |
| 313 | /* Next transmit descriptor start address */ |
| 314 | #define NPCM_DMA_HOST_TX_DESC_MASK(word) ((uint32_t) (word) & ~3u) |
| 315 | |
| 316 | /* Receive enable */ |
| 317 | #define NPCM_GMAC_MAC_CONFIG_RX_EN BIT(2) |
| 318 | /* Transmit enable */ |
| 319 | #define NPCM_GMAC_MAC_CONFIG_TX_EN BIT(3) |
| 320 | |
| 321 | /* Frame Receive All */ |
| 322 | #define NPCM_GMAC_FRAME_FILTER_REC_ALL_MASK BIT(31) |
| 323 | /* Frame HPF Filter*/ |
| 324 | #define NPCM_GMAC_FRAME_FILTER_HPF_MASK BIT(10) |
| 325 | /* Frame SAF Filter*/ |
| 326 | #define NPCM_GMAC_FRAME_FILTER_SAF_MASK BIT(9) |
| 327 | /* Frame SAIF Filter*/ |
| 328 | #define NPCM_GMAC_FRAME_FILTER_SAIF_MASK BIT(8) |
| 329 | /* Frame PCF Filter*/ |
| 330 | #define NPCM_GMAC_FRAME_FILTER_PCF_MASK BIT(word) extract32((word), 6, 2) |
| 331 | /* Frame DBF Filter*/ |
| 332 | #define NPCM_GMAC_FRAME_FILTER_DBF_MASK BIT(5) |
| 333 | /* Frame PM Filter*/ |
| 334 | #define NPCM_GMAC_FRAME_FILTER_PM_MASK BIT(4) |
| 335 | /* Frame DAIF Filter*/ |
| 336 | #define NPCM_GMAC_FRAME_FILTER_DAIF_MASK BIT(3) |
| 337 | /* Frame HMC Filter*/ |
| 338 | #define NPCM_GMAC_FRAME_FILTER_HMC_MASK BIT(2) |
| 339 | /* Frame HUC Filter*/ |
| 340 | #define NPCM_GMAC_FRAME_FILTER_HUC_MASK BIT(1) |
| 341 | /* Frame PR Filter*/ |
| 342 | #define NPCM_GMAC_FRAME_FILTER_PR_MASK BIT(0) |
| 343 | |
| 344 | #endif /* NPCM_GMAC_H */ |