| 1 | /* |
| 2 | * Copyright (c) 2020 Xilinx Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 5 | * of this software and associated documentation files (the "Software"), to deal |
| 6 | * in the Software without restriction, including without limitation the rights |
| 7 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 8 | * copies of the Software, and to permit persons to whom the Software is |
| 9 | * furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 19 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 20 | * THE SOFTWARE. |
| 21 | */ |
| 22 | #ifndef XLNX_VERSAL_EFUSE_H |
| 23 | #define XLNX_VERSAL_EFUSE_H |
| 24 | |
| 25 | #include "hw/core/irq.h" |
| 26 | #include "hw/core/sysbus.h" |
| 27 | #include "hw/core/register.h" |
| 28 | #include "hw/nvram/xlnx-efuse.h" |
| 29 | |
| 30 | #define XLNX_VERSAL_EFUSE_CTRL_R_MAX ((0x100 / 4) + 1) |
| 31 | |
| 32 | #define TYPE_XLNX_VERSAL_EFUSE_CTRL "xlnx-versal-efuse" |
| 33 | #define TYPE_XLNX_VERSAL_EFUSE_CACHE "xlnx-pmc-efuse-cache" |
| 34 | |
| 35 | OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalEFuseCtrl, XLNX_VERSAL_EFUSE_CTRL); |
| 36 | OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalEFuseCache, XLNX_VERSAL_EFUSE_CACHE); |
| 37 | |
| 38 | struct XlnxVersalEFuseCtrl { |
| 39 | SysBusDevice parent_obj; |
| 40 | qemu_irq irq_efuse_imr; |
| 41 | |
| 42 | XlnxEFuse *efuse; |
| 43 | |
| 44 | void *extra_pg0_lock_spec; /* Opaque property */ |
| 45 | uint32_t extra_pg0_lock_n16; |
| 46 | |
| 47 | RegisterInfoArray *reg_array; |
| 48 | uint32_t regs[XLNX_VERSAL_EFUSE_CTRL_R_MAX]; |
| 49 | RegisterInfo regs_info[XLNX_VERSAL_EFUSE_CTRL_R_MAX]; |
| 50 | }; |
| 51 | |
| 52 | struct XlnxVersalEFuseCache { |
| 53 | SysBusDevice parent_obj; |
| 54 | MemoryRegion iomem; |
| 55 | |
| 56 | XlnxEFuse *efuse; |
| 57 | }; |
| 58 | |
| 59 | /** |
| 60 | * xlnx_versal_efuse_read_row: |
| 61 | * @s: the efuse object |
| 62 | * @bit: the bit-address within the 32-bit row to be read |
| 63 | * @denied: if non-NULL, to receive true if the row is write-only |
| 64 | * |
| 65 | * Returns: the 32-bit word containing address @bit; 0 if @denies is true |
| 66 | */ |
| 67 | uint32_t xlnx_versal_efuse_read_row(XlnxEFuse *s, uint32_t bit, bool *denied); |
| 68 | |
| 69 | #endif |