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1 /*
2 * ASPEED PCIe Host Controller
3 *
4 * Copyright (C) 2025 ASPEED Technology Inc.
5 * Copyright (c) 2022 Cédric Le Goater <clg@kaod.org>
6 *
7 * Authors:
8 * Cédric Le Goater <clg@kaod.org>
9 * Jamin Lin <jamin_lin@aspeedtech.com>
10 *
11 * SPDX-License-Identifier: GPL-2.0-or-later
12 *
13 * Based on previous work from Cédric Le Goater.
14 * Modifications extend support for the ASPEED AST2600 and AST2700 platforms.
15 */
16
17 #ifndef ASPEED_PCIE_H
18 #define ASPEED_PCIE_H
19
20 #include "hw/core/sysbus.h"
21 #include "hw/pci/pci_bridge.h"
22 #include "hw/pci/pcie_host.h"
23 #include "hw/pci/pcie_port.h"
24 #include "qom/object.h"
25
26 typedef struct AspeedPCIECfgTxDesc {
27 uint32_t desc0;
28 uint32_t desc1;
29 uint32_t desc2;
30 uint32_t desc3;
31 uint32_t wdata;
32 uint32_t rdata_reg;
33 } AspeedPCIECfgTxDesc;
34
35 typedef struct AspeedPCIERcRegs {
36 uint32_t int_en_reg;
37 uint32_t int_sts_reg;
38 uint32_t msi_sts0_reg;
39 uint32_t msi_sts1_reg;
40 } AspeedPCIERcRegs;
41
42 typedef struct AspeedPCIERegMap {
43 AspeedPCIERcRegs rc;
44 } AspeedPCIERegMap;
45
46 #define TYPE_ASPEED_PCIE_ROOT_PORT "aspeed.pcie-root-port"
47 OBJECT_DECLARE_SIMPLE_TYPE(AspeedPCIERootPortState, ASPEED_PCIE_ROOT_PORT)
48
49 typedef struct AspeedPCIERootPortState {
50 PCIESlot parent_obj;
51 } AspeedPCIERootPortState;
52
53 #define TYPE_ASPEED_PCIE_RC "aspeed.pcie-rc"
54 OBJECT_DECLARE_SIMPLE_TYPE(AspeedPCIERcState, ASPEED_PCIE_RC);
55
56 struct AspeedPCIERcState {
57 PCIExpressHost parent_obj;
58
59 MemoryRegion iommu_root;
60 AddressSpace iommu_as;
61 MemoryRegion dram_alias;
62 MemoryRegion *dram_mr;
63 MemoryRegion mmio_window;
64 MemoryRegion msi_window;
65 MemoryRegion io_window;
66 MemoryRegion mmio;
67 MemoryRegion io;
68
69 uint64_t dram_base;
70 uint32_t msi_addr;
71 uint32_t rp_addr;
72 char name[16];
73 qemu_irq irq;
74
75 AspeedPCIERootPortState root_port;
76 };
77
78 /* Bridge between AHB bus and PCIe RC. */
79 #define TYPE_ASPEED_PCIE_CFG "aspeed.pcie-cfg"
80 #define TYPE_ASPEED_2700_PCIE_CFG TYPE_ASPEED_PCIE_CFG "-ast2700"
81 OBJECT_DECLARE_TYPE(AspeedPCIECfgState, AspeedPCIECfgClass, ASPEED_PCIE_CFG);
82
83 struct AspeedPCIECfgState {
84 SysBusDevice parent_obj;
85
86 MemoryRegion mmio;
87 uint32_t *regs;
88 uint32_t id;
89
90 const AspeedPCIERcRegs *rc_regs;
91 AspeedPCIERcState rc;
92 uint32_t tlpn_fifo[3];
93 uint32_t tlpn_idx;
94 };
95
96 struct AspeedPCIECfgClass {
97 SysBusDeviceClass parent_class;
98
99 const AspeedPCIERegMap *reg_map;
100 const MemoryRegionOps *reg_ops;
101
102 uint32_t rc_msi_addr;
103 uint32_t rc_rp_addr;
104 uint64_t nr_regs;
105 bool rc_has_rd;
106 };
107
108 #define TYPE_ASPEED_PCIE_PHY "aspeed.pcie-phy"
109 #define TYPE_ASPEED_2700_PCIE_PHY TYPE_ASPEED_PCIE_PHY "-ast2700"
110 OBJECT_DECLARE_TYPE(AspeedPCIEPhyState, AspeedPCIEPhyClass, ASPEED_PCIE_PHY);
111
112 struct AspeedPCIEPhyState {
113 SysBusDevice parent_obj;
114
115 MemoryRegion mmio;
116 uint32_t *regs;
117 uint32_t id;
118 };
119
120 struct AspeedPCIEPhyClass {
121 SysBusDeviceClass parent_class;
122
123 uint64_t nr_regs;
124 };
125
126 #endif /* ASPEED_PCIE_H */