| 1 | /* |
| 2 | * QEMU PowerPC PowerNV (POWER9) PHB4 model |
| 3 | * |
| 4 | * Copyright (c) 2018-2020, IBM Corporation. |
| 5 | * |
| 6 | * This code is licensed under the GPL version 2 or later. See the |
| 7 | * COPYING file in the top-level directory. |
| 8 | */ |
| 9 | |
| 10 | #ifndef PCI_HOST_PNV_PHB4_H |
| 11 | #define PCI_HOST_PNV_PHB4_H |
| 12 | |
| 13 | #include "hw/pci-host/pnv_phb.h" |
| 14 | #include "hw/pci/pci_bus.h" |
| 15 | #include "hw/ppc/pnv.h" |
| 16 | #include "hw/ppc/pnv_nest_pervasive.h" |
| 17 | #include "hw/ppc/xive.h" |
| 18 | #include "qom/object.h" |
| 19 | |
| 20 | |
| 21 | #define TYPE_PNV_PHB4 "pnv-phb4" |
| 22 | OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB4, PNV_PHB4) |
| 23 | |
| 24 | typedef struct PnvPhb4PecStack PnvPhb4PecStack; |
| 25 | |
| 26 | /* |
| 27 | * We have one such address space wrapper per possible device under |
| 28 | * the PHB since they need to be assigned statically at qemu device |
| 29 | * creation time. The relationship to a PE is done later |
| 30 | * dynamically. This means we can potentially create a lot of these |
| 31 | * guys. Q35 stores them as some kind of radix tree but we never |
| 32 | * really need to do fast lookups so instead we simply keep a QLIST of |
| 33 | * them for now, we can add the radix if needed later on. |
| 34 | * |
| 35 | * We do cache the PE number to speed things up a bit though. |
| 36 | */ |
| 37 | typedef struct PnvPhb4DMASpace { |
| 38 | PCIBus *bus; |
| 39 | uint8_t devfn; |
| 40 | int pe_num; /* Cached PE number */ |
| 41 | #define PHB_INVALID_PE (-1) |
| 42 | PnvPHB4 *phb; |
| 43 | AddressSpace dma_as; |
| 44 | IOMMUMemoryRegion dma_mr; |
| 45 | MemoryRegion msi32_mr; |
| 46 | MemoryRegion msi64_mr; |
| 47 | QLIST_ENTRY(PnvPhb4DMASpace) list; |
| 48 | } PnvPhb4DMASpace; |
| 49 | |
| 50 | /* |
| 51 | * PHB4 PCIe Root Bus |
| 52 | */ |
| 53 | #define TYPE_PNV_PHB4_ROOT_BUS "pnv-phb4-root" |
| 54 | struct PnvPHB4RootBus { |
| 55 | PCIBus parent; |
| 56 | |
| 57 | uint32_t chip_id; |
| 58 | uint32_t phb_id; |
| 59 | }; |
| 60 | OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB4RootBus, PNV_PHB4_ROOT_BUS) |
| 61 | |
| 62 | /* |
| 63 | * PHB4 PCIe Host Bridge for PowerNV machines (POWER9) |
| 64 | */ |
| 65 | #define PNV_PHB4_MAX_LSIs 8 |
| 66 | #define PNV_PHB4_MAX_INTs 4096 |
| 67 | #define PNV_PHB4_MAX_MIST (PNV_PHB4_MAX_INTs >> 2) |
| 68 | #define PNV_PHB4_MAX_MMIO_WINDOWS 32 |
| 69 | #define PNV_PHB4_MIN_MMIO_WINDOWS 16 |
| 70 | #define PNV_PHB4_NUM_REGS (0x3000 >> 3) |
| 71 | #define PNV_PHB4_MAX_PEs 512 |
| 72 | #define PNV_PHB4_MAX_TVEs (PNV_PHB4_MAX_PEs * 2) |
| 73 | #define PNV_PHB4_MAX_PEEVs (PNV_PHB4_MAX_PEs / 64) |
| 74 | #define PNV_PHB4_MAX_MBEs (PNV_PHB4_MAX_MMIO_WINDOWS * 2) |
| 75 | |
| 76 | #define PNV_PHB4_VERSION 0x000000a400000002ull |
| 77 | #define PNV_PHB4_DEVICE_ID 0x04c1 |
| 78 | |
| 79 | #define PCI_MMIO_TOTAL_SIZE (0x1ull << 60) |
| 80 | |
| 81 | struct PnvPHB4 { |
| 82 | DeviceState parent; |
| 83 | |
| 84 | PnvPHB *phb_base; |
| 85 | |
| 86 | uint32_t chip_id; |
| 87 | uint32_t phb_id; |
| 88 | |
| 89 | /* The owner PEC */ |
| 90 | PnvPhb4PecState *pec; |
| 91 | |
| 92 | char bus_path[8]; |
| 93 | |
| 94 | /* Main register images */ |
| 95 | uint64_t regs[PNV_PHB4_NUM_REGS]; |
| 96 | MemoryRegion mr_regs; |
| 97 | |
| 98 | /* Extra SCOM-only register */ |
| 99 | uint64_t scom_hv_ind_addr_reg; |
| 100 | |
| 101 | /* |
| 102 | * Geometry of the PHB. There are two types, small and big PHBs, a |
| 103 | * number of resources (number of PEs, windows etc...) are doubled |
| 104 | * for a big PHB |
| 105 | */ |
| 106 | bool big_phb; |
| 107 | |
| 108 | /* Memory regions for MMIO space */ |
| 109 | MemoryRegion mr_mmio[PNV_PHB4_MAX_MMIO_WINDOWS]; |
| 110 | |
| 111 | /* PCI side space */ |
| 112 | MemoryRegion pci_mmio; |
| 113 | MemoryRegion pci_io; |
| 114 | |
| 115 | /* PCI registers (excluding pass-through) */ |
| 116 | #define PHB4_PEC_PCI_STK_REGS_COUNT 0xf |
| 117 | uint64_t pci_regs[PHB4_PEC_PCI_STK_REGS_COUNT]; |
| 118 | MemoryRegion pci_regs_mr; |
| 119 | |
| 120 | /* Nest registers */ |
| 121 | #define PHB4_PEC_NEST_STK_REGS_COUNT 0x18 |
| 122 | uint64_t nest_regs[PHB4_PEC_NEST_STK_REGS_COUNT]; |
| 123 | MemoryRegion nest_regs_mr; |
| 124 | |
| 125 | /* PHB pass-through XSCOM */ |
| 126 | MemoryRegion phb_regs_mr; |
| 127 | |
| 128 | /* Memory windows from PowerBus to PHB */ |
| 129 | MemoryRegion phbbar; |
| 130 | MemoryRegion intbar; |
| 131 | MemoryRegion mmbar0; |
| 132 | MemoryRegion mmbar1; |
| 133 | uint64_t mmio0_base; |
| 134 | uint64_t mmio0_size; |
| 135 | uint64_t mmio1_base; |
| 136 | uint64_t mmio1_size; |
| 137 | |
| 138 | /* On-chip IODA tables */ |
| 139 | uint64_t ioda_LIST[PNV_PHB4_MAX_LSIs]; |
| 140 | uint64_t ioda_MIST[PNV_PHB4_MAX_MIST]; |
| 141 | uint64_t ioda_TVT[PNV_PHB4_MAX_TVEs]; |
| 142 | uint64_t ioda_MBT[PNV_PHB4_MAX_MBEs]; |
| 143 | uint64_t ioda_MDT[PNV_PHB4_MAX_PEs]; |
| 144 | uint64_t ioda_PEEV[PNV_PHB4_MAX_PEEVs]; |
| 145 | |
| 146 | /* |
| 147 | * The internal PESTA/B is 2 bits per PE split into two tables, we |
| 148 | * store them in a single array here to avoid wasting space. |
| 149 | */ |
| 150 | uint8_t ioda_PEST_AB[PNV_PHB4_MAX_PEs]; |
| 151 | |
| 152 | /* P9 Interrupt generation */ |
| 153 | XiveSource xsrc; |
| 154 | qemu_irq *qirqs; |
| 155 | |
| 156 | QLIST_HEAD(, PnvPhb4DMASpace) dma_spaces; |
| 157 | }; |
| 158 | |
| 159 | void pnv_phb4_pic_print_info(PnvPHB4 *phb, GString *buf); |
| 160 | int pnv_phb4_pec_get_phb_id(PnvPhb4PecState *pec, int stack_index); |
| 161 | PnvPhb4PecState *pnv_pec_add_phb(PnvChip *chip, PnvPHB *phb, Error **errp); |
| 162 | void pnv_phb4_bus_init(DeviceState *dev, PnvPHB4 *phb); |
| 163 | extern const MemoryRegionOps pnv_phb4_xscom_ops; |
| 164 | |
| 165 | /* |
| 166 | * PHB4 PEC (PCI Express Controller) |
| 167 | */ |
| 168 | #define TYPE_PNV_PHB4_PEC "pnv-phb4-pec" |
| 169 | OBJECT_DECLARE_TYPE(PnvPhb4PecState, PnvPhb4PecClass, PNV_PHB4_PEC) |
| 170 | |
| 171 | struct PnvPhb4PecState { |
| 172 | DeviceState parent; |
| 173 | |
| 174 | /* PEC number in chip */ |
| 175 | uint32_t index; |
| 176 | uint32_t chip_id; |
| 177 | |
| 178 | /* Pervasive chiplet control */ |
| 179 | PnvNestChipletPervasive nest_pervasive; |
| 180 | |
| 181 | /* Nest registers, excuding per-stack */ |
| 182 | #define PHB4_PEC_NEST_REGS_COUNT 0xf |
| 183 | uint64_t nest_regs[PHB4_PEC_NEST_REGS_COUNT]; |
| 184 | MemoryRegion nest_regs_mr; |
| 185 | |
| 186 | /* PCI registers, excluding per-stack */ |
| 187 | #define PHB4_PEC_PCI_REGS_COUNT 0x3 |
| 188 | uint64_t pci_regs[PHB4_PEC_PCI_REGS_COUNT]; |
| 189 | MemoryRegion pci_regs_mr; |
| 190 | |
| 191 | /* PHBs */ |
| 192 | uint32_t num_phbs; |
| 193 | #define MAX_PHBS_PER_PEC 3 |
| 194 | PnvPHB *phbs[MAX_PHBS_PER_PEC]; |
| 195 | |
| 196 | PnvChip *chip; |
| 197 | }; |
| 198 | |
| 199 | |
| 200 | struct PnvPhb4PecClass { |
| 201 | DeviceClass parent_class; |
| 202 | |
| 203 | uint32_t (*xscom_cplt_base)(PnvPhb4PecState *pec); |
| 204 | uint32_t (*xscom_nest_base)(PnvPhb4PecState *pec); |
| 205 | uint32_t xscom_nest_size; |
| 206 | uint32_t (*xscom_pci_base)(PnvPhb4PecState *pec); |
| 207 | uint32_t xscom_pci_size; |
| 208 | const char *compat; |
| 209 | int compat_size; |
| 210 | const char *stk_compat; |
| 211 | int stk_compat_size; |
| 212 | uint64_t version; |
| 213 | const char *phb_type; |
| 214 | const uint32_t *num_phbs; |
| 215 | }; |
| 216 | |
| 217 | /* |
| 218 | * POWER10 definitions |
| 219 | */ |
| 220 | |
| 221 | #define TYPE_PNV_PHB5 "pnv-phb5" |
| 222 | #define PNV_PHB5(obj) \ |
| 223 | OBJECT_CHECK(PnvPhb4, (obj), TYPE_PNV_PHB5) |
| 224 | |
| 225 | #define PNV_PHB5_VERSION 0x000000a500000002ull |
| 226 | |
| 227 | #define TYPE_PNV_PHB5_PEC "pnv-phb5-pec" |
| 228 | #define PNV_PHB5_PEC(obj) \ |
| 229 | OBJECT_CHECK(PnvPhb4PecState, (obj), TYPE_PNV_PHB5_PEC) |
| 230 | |
| 231 | #endif /* PCI_HOST_PNV_PHB4_H */ |