| 1 | /* |
| 2 | * QEMU PowerPC PowerNV (POWER9) PHB4 model |
| 3 | * |
| 4 | * Copyright (c) 2013-2020, IBM Corporation. |
| 5 | * |
| 6 | * This code is licensed under the GPL version 2 or later. See the |
| 7 | * COPYING file in the top-level directory. |
| 8 | */ |
| 9 | |
| 10 | #ifndef PCI_HOST_PNV_PHB4_REGS_H |
| 11 | #define PCI_HOST_PNV_PHB4_REGS_H |
| 12 | |
| 13 | /* |
| 14 | * PEC XSCOM registers |
| 15 | * |
| 16 | * There a 3 PECs in P9. Each PEC can have several PHBs. Each PEC has some |
| 17 | * "global" registers and some "per-stack" (per-PHB) registers. Those are |
| 18 | * organized in two XSCOM ranges, the "Nest" range and the "PCI" range, each |
| 19 | * range contains both some "PEC" registers and some "per-stack" registers. |
| 20 | * |
| 21 | * Finally the PCI range also contains an additional range per stack that |
| 22 | * passes through to some of the PHB own registers. |
| 23 | * |
| 24 | * PEC0 can contain 1 PHB (PHB0) |
| 25 | * PEC1 can contain 2 PHBs (PHB1 and PHB2) |
| 26 | * PEC2 can contain 3 PHBs (PHB3, PHB4 and PHB5) |
| 27 | */ |
| 28 | |
| 29 | /* |
| 30 | * This is the "stack" offset, it's the offset from a given range base |
| 31 | * to the first "per-stack" registers and also the stride between |
| 32 | * stacks, thus for PEC2, the global registers are at offset 0, the |
| 33 | * PHB3 registers at offset 0x40, the PHB4 at offset 0x80 etc.... |
| 34 | * |
| 35 | * It is *also* the offset to the pass-through SCOM region but in this case |
| 36 | * it is 0 based, ie PHB3 is at 0x100 PHB4 is a 0x140 etc.. |
| 37 | */ |
| 38 | #define PEC_STACK_OFFSET 0x40 |
| 39 | |
| 40 | /* XSCOM Nest global registers */ |
| 41 | #define PEC_NEST_PBCQ_HW_CONFIG 0x00 |
| 42 | #define PEC_NEST_DROP_PRIO_CTRL 0x01 |
| 43 | #define PEC_NEST_PBCQ_ERR_INJECT 0x02 |
| 44 | #define PEC_NEST_PCI_NEST_CLK_TRACE_CTL 0x03 |
| 45 | #define PEC_NEST_PBCQ_PMON_CTRL 0x04 |
| 46 | #define PEC_NEST_PBCQ_PBUS_ADDR_EXT 0x05 |
| 47 | #define PEC_NEST_PBCQ_PRED_VEC_TIMEOUT 0x06 |
| 48 | #define PEC_NEST_CAPP_CTRL 0x07 |
| 49 | #define PEC_NEST_PBCQ_READ_STK_OVR 0x08 |
| 50 | #define PEC_NEST_PBCQ_WRITE_STK_OVR 0x09 |
| 51 | #define PEC_NEST_PBCQ_STORE_STK_OVR 0x0a |
| 52 | #define PEC_NEST_PBCQ_RETRY_BKOFF_CTRL 0x0b |
| 53 | |
| 54 | /* XSCOM Nest per-stack registers */ |
| 55 | #define PEC_NEST_STK_PCI_NEST_FIR 0x00 |
| 56 | #define PEC_NEST_STK_PCI_NEST_FIR_CLR 0x01 |
| 57 | #define PEC_NEST_STK_PCI_NEST_FIR_SET 0x02 |
| 58 | #define PEC_NEST_STK_PCI_NEST_FIR_MSK 0x03 |
| 59 | #define PEC_NEST_STK_PCI_NEST_FIR_MSKC 0x04 |
| 60 | #define PEC_NEST_STK_PCI_NEST_FIR_MSKS 0x05 |
| 61 | #define PEC_NEST_STK_PCI_NEST_FIR_ACT0 0x06 |
| 62 | #define PEC_NEST_STK_PCI_NEST_FIR_ACT1 0x07 |
| 63 | #define PEC_NEST_STK_PCI_NEST_FIR_WOF 0x08 |
| 64 | #define PEC_NEST_STK_ERR_REPORT_0 0x0a |
| 65 | #define PEC_NEST_STK_ERR_REPORT_1 0x0b |
| 66 | #define PEC_NEST_STK_PBCQ_GNRL_STATUS 0x0c |
| 67 | #define PEC_NEST_STK_PBCQ_MODE 0x0d |
| 68 | #define PEC_NEST_STK_MMIO_BAR0 0x0e |
| 69 | #define PEC_NEST_STK_MMIO_BAR0_MASK 0x0f |
| 70 | #define PEC_NEST_STK_MMIO_BAR1 0x10 |
| 71 | #define PEC_NEST_STK_MMIO_BAR1_MASK 0x11 |
| 72 | #define PEC_NEST_STK_PHB_REGS_BAR 0x12 |
| 73 | #define PEC_NEST_STK_INT_BAR 0x13 |
| 74 | #define PEC_NEST_STK_BAR_EN 0x14 |
| 75 | #define PEC_NEST_STK_BAR_EN_MMIO0 PPC_BIT(0) |
| 76 | #define PEC_NEST_STK_BAR_EN_MMIO1 PPC_BIT(1) |
| 77 | #define PEC_NEST_STK_BAR_EN_PHB PPC_BIT(2) |
| 78 | #define PEC_NEST_STK_BAR_EN_INT PPC_BIT(3) |
| 79 | #define PEC_NEST_STK_DATA_FRZ_TYPE 0x15 |
| 80 | #define PEC_NEST_STK_PBCQ_SPARSE_PAGE 0x16 /* P10 */ |
| 81 | #define PEC_NEST_STK_PBCQ_CACHE_INJ 0x17 /* P10 */ |
| 82 | |
| 83 | /* XSCOM PCI global registers */ |
| 84 | #define PEC_PCI_PBAIB_HW_CONFIG 0x00 |
| 85 | #define PEC_PCI_PBAIB_HW_OVR 0x01 |
| 86 | #define PEC_PCI_PBAIB_READ_STK_OVR 0x02 |
| 87 | |
| 88 | /* XSCOM PCI per-stack registers */ |
| 89 | #define PEC_PCI_STK_PCI_FIR 0x00 |
| 90 | #define PEC_PCI_STK_PCI_FIR_CLR 0x01 |
| 91 | #define PEC_PCI_STK_PCI_FIR_SET 0x02 |
| 92 | #define PEC_PCI_STK_PCI_FIR_MSK 0x03 |
| 93 | #define PEC_PCI_STK_PCI_FIR_MSKC 0x04 |
| 94 | #define PEC_PCI_STK_PCI_FIR_MSKS 0x05 |
| 95 | #define PEC_PCI_STK_PCI_FIR_ACT0 0x06 |
| 96 | #define PEC_PCI_STK_PCI_FIR_ACT1 0x07 |
| 97 | #define PEC_PCI_STK_PCI_FIR_WOF 0x08 |
| 98 | #define PEC_PCI_STK_ETU_RESET 0x0a |
| 99 | #define PEC_PCI_STK_PBAIB_ERR_REPORT 0x0b |
| 100 | #define PEC_PCI_STK_PBAIB_TX_CMD_CRED 0x0d |
| 101 | #define PEC_PCI_STK_PBAIB_TX_DAT_CRED 0x0e |
| 102 | |
| 103 | /* |
| 104 | * PHB "SCOM" registers. This is accessed via the above window |
| 105 | * and provides a backdoor to the PHB when the AIB bus is not |
| 106 | * functional. Some of these directly map some of the PHB MMIO |
| 107 | * registers, some are specific and allow indirect access to a |
| 108 | * wider range of PHB registers |
| 109 | */ |
| 110 | #define PHB_SCOM_HV_IND_ADDR 0x00 |
| 111 | #define PHB_SCOM_HV_IND_ADDR_VALID PPC_BIT(0) |
| 112 | #define PHB_SCOM_HV_IND_ADDR_4B PPC_BIT(1) |
| 113 | #define PHB_SCOM_HV_IND_ADDR_AUTOINC PPC_BIT(2) |
| 114 | #define PHB_SCOM_HV_IND_ADDR_ADDR PPC_BITMASK(51, 63) |
| 115 | #define PHB_SCOM_HV_IND_DATA 0x01 |
| 116 | #define PHB_SCOM_ETU_LEM_FIR 0x08 |
| 117 | #define PHB_SCOM_ETU_LEM_FIR_AND 0x09 |
| 118 | #define PHB_SCOM_ETU_LEM_FIR_OR 0x0a |
| 119 | #define PHB_SCOM_ETU_LEM_FIR_MSK 0x0b |
| 120 | #define PHB_SCOM_ETU_LEM_ERR_MSK_AND 0x0c |
| 121 | #define PHB_SCOM_ETU_LEM_ERR_MSK_OR 0x0d |
| 122 | #define PHB_SCOM_ETU_LEM_ACT0 0x0e |
| 123 | #define PHB_SCOM_ETU_LEM_ACT1 0x0f |
| 124 | #define PHB_SCOM_ETU_LEM_WOF 0x10 |
| 125 | #define PHB_SCOM_ETU_PMON_CONFIG 0x17 |
| 126 | #define PHB_SCOM_ETU_PMON_CTR0 0x18 |
| 127 | #define PHB_SCOM_ETU_PMON_CTR1 0x19 |
| 128 | #define PHB_SCOM_ETU_PMON_CTR2 0x1a |
| 129 | #define PHB_SCOM_ETU_PMON_CTR3 0x1b |
| 130 | |
| 131 | |
| 132 | /* |
| 133 | * PHB MMIO registers |
| 134 | */ |
| 135 | |
| 136 | /* PHB Fundamental register set A */ |
| 137 | #define PHB_LSI_SOURCE_ID 0x100 |
| 138 | #define PHB_LSI_SRC_ID PPC_BITMASK(4, 12) |
| 139 | #define PHB_DMA_CHAN_STATUS 0x110 |
| 140 | #define PHB_DMA_CHAN_ANY_ERR PPC_BIT(27) |
| 141 | #define PHB_DMA_CHAN_ANY_ERR1 PPC_BIT(28) |
| 142 | #define PHB_DMA_CHAN_ANY_FREEZE PPC_BIT(29) |
| 143 | #define PHB_CPU_LOADSTORE_STATUS 0x120 |
| 144 | #define PHB_CPU_LS_ANY_ERR PPC_BIT(27) |
| 145 | #define PHB_CPU_LS_ANY_ERR1 PPC_BIT(28) |
| 146 | #define PHB_CPU_LS_ANY_FREEZE PPC_BIT(29) |
| 147 | #define PHB_CONFIG_DATA 0x130 |
| 148 | #define PHB_LOCK0 0x138 |
| 149 | #define PHB_CONFIG_ADDRESS 0x140 |
| 150 | #define PHB_CA_ENABLE PPC_BIT(0) |
| 151 | #define PHB_CA_STATUS PPC_BITMASK(1, 3) |
| 152 | #define PHB_CA_STATUS_GOOD 0 |
| 153 | #define PHB_CA_STATUS_UR 1 |
| 154 | #define PHB_CA_STATUS_CRS 2 |
| 155 | #define PHB_CA_STATUS_CA 4 |
| 156 | #define PHB_CA_BUS PPC_BITMASK(4, 11) |
| 157 | #define PHB_CA_DEV PPC_BITMASK(12, 16) |
| 158 | #define PHB_CA_FUNC PPC_BITMASK(17, 19) |
| 159 | #define PHB_CA_BDFN PPC_BITMASK(4, 19) /* bus,dev,func */ |
| 160 | #define PHB_CA_REG PPC_BITMASK(20, 31) |
| 161 | #define PHB_CA_PE PPC_BITMASK(39, 47) |
| 162 | #define PHB_LOCK1 0x148 |
| 163 | #define PHB_PHB4_CONFIG 0x160 |
| 164 | #define PHB_PHB4C_32BIT_MSI_EN PPC_BIT(8) |
| 165 | #define PHB_PHB4C_64BIT_MSI_EN PPC_BIT(14) |
| 166 | #define PHB_RTT_BAR 0x168 |
| 167 | #define PHB_RTT_BAR_ENABLE PPC_BIT(0) |
| 168 | #define PHB_RTT_BASE_ADDRESS_MASK PPC_BITMASK(8, 46) |
| 169 | #define PHB_PELTV_BAR 0x188 |
| 170 | #define PHB_PELTV_BAR_ENABLE PPC_BIT(0) |
| 171 | #define PHB_PELTV_BASE_ADDRESS PPC_BITMASK(8, 50) |
| 172 | #define PHB_M32_START_ADDR 0x1a0 |
| 173 | #define PHB_PEST_BAR 0x1a8 |
| 174 | #define PHB_PEST_BAR_ENABLE PPC_BIT(0) |
| 175 | #define PHB_PEST_BASE_ADDRESS PPC_BITMASK(8, 51) |
| 176 | #define PHB_ASN_CMPM 0x1C0 |
| 177 | #define PHB_ASN_CMPM_ENABLE PPC_BIT(63) |
| 178 | #define PHB_CAPI_CMPM 0x1C8 |
| 179 | #define PHB_CAPI_CMPM_ENABLE PPC_BIT(63) |
| 180 | #define PHB_M64_AOMASK 0x1d0 |
| 181 | #define PHB_M64_UPPER_BITS 0x1f0 |
| 182 | #define PHB_NXLATE_PREFIX 0x1f8 |
| 183 | #define PHB_DMARD_SYNC 0x200 |
| 184 | #define PHB_DMARD_SYNC_START PPC_BIT(0) |
| 185 | #define PHB_DMARD_SYNC_COMPLETE PPC_BIT(1) |
| 186 | #define PHB_RTC_INVALIDATE 0x208 |
| 187 | #define PHB_RTC_INVALIDATE_ALL PPC_BIT(0) |
| 188 | #define PHB_RTC_INVALIDATE_RID PPC_BITMASK(16, 31) |
| 189 | #define PHB_TCE_KILL 0x210 |
| 190 | #define PHB_TCE_KILL_ALL PPC_BIT(0) |
| 191 | #define PHB_TCE_KILL_PE PPC_BIT(1) |
| 192 | #define PHB_TCE_KILL_ONE PPC_BIT(2) |
| 193 | #define PHB_TCE_KILL_PSEL PPC_BIT(3) |
| 194 | #define PHB_TCE_KILL_64K 0x1000 /* Address override */ |
| 195 | #define PHB_TCE_KILL_2M 0x2000 /* Address override */ |
| 196 | #define PHB_TCE_KILL_1G 0x3000 /* Address override */ |
| 197 | #define PHB_TCE_KILL_PENUM PPC_BITMASK(55, 63) |
| 198 | #define PHB_TCE_SPEC_CTL 0x218 |
| 199 | #define PHB_IODA_ADDR 0x220 |
| 200 | #define PHB_IODA_AD_AUTOINC PPC_BIT(0) |
| 201 | #define PHB_IODA_AD_TSEL PPC_BITMASK(11, 15) |
| 202 | #define PHB_IODA_AD_MIST_PWV PPC_BITMASK(28, 31) |
| 203 | #define PHB_IODA_AD_TADR PPC_BITMASK(54, 63) |
| 204 | #define PHB_IODA_DATA0 0x228 |
| 205 | #define PHB_PHB4_GEN_CAP 0x250 |
| 206 | #define PHB_PHB4_TCE_CAP 0x258 |
| 207 | #define PHB_PHB4_IRQ_CAP 0x260 |
| 208 | #define PHB_PHB4_EEH_CAP 0x268 |
| 209 | #define PHB_PAPR_ERR_INJ_CTL 0x2b0 |
| 210 | #define PHB_PAPR_ERR_INJ_CTL_INB PPC_BIT(0) |
| 211 | #define PHB_PAPR_ERR_INJ_CTL_OUTB PPC_BIT(1) |
| 212 | #define PHB_PAPR_ERR_INJ_CTL_STICKY PPC_BIT(2) |
| 213 | #define PHB_PAPR_ERR_INJ_CTL_CFG PPC_BIT(3) |
| 214 | #define PHB_PAPR_ERR_INJ_CTL_RD PPC_BIT(4) |
| 215 | #define PHB_PAPR_ERR_INJ_CTL_WR PPC_BIT(5) |
| 216 | #define PHB_PAPR_ERR_INJ_CTL_FREEZE PPC_BIT(6) |
| 217 | #define PHB_PAPR_ERR_INJ_ADDR 0x2b8 |
| 218 | #define PHB_PAPR_ERR_INJ_ADDR_MMIO PPC_BITMASK(16, 63) |
| 219 | #define PHB_PAPR_ERR_INJ_MASK 0x2c0 |
| 220 | #define PHB_PAPR_ERR_INJ_MASK_CFG PPC_BITMASK(4, 11) |
| 221 | #define PHB_PAPR_ERR_INJ_MASK_CFG_ALL PPC_BITMASK(4, 19) |
| 222 | #define PHB_PAPR_ERR_INJ_MASK_MMIO PPC_BITMASK(16, 63) |
| 223 | #define PHB_ETU_ERR_SUMMARY 0x2c8 |
| 224 | #define PHB_INT_NOTIFY_ADDR 0x300 |
| 225 | #define PHB_INT_NOTIFY_ADDR_64K PPC_BIT(1) /* P10 */ |
| 226 | #define PHB_INT_NOTIFY_INDEX 0x308 |
| 227 | |
| 228 | /* Fundamental register set B */ |
| 229 | #define PHB_VERSION 0x800 |
| 230 | #define PHB_CTRLR 0x810 |
| 231 | #define PHB_CTRLR_IRQ_PQ_DISABLE PPC_BIT(9) /* P10 */ |
| 232 | #define PHB_CTRLR_IRQ_ABT_MODE PPC_BIT(10) /* P10 */ |
| 233 | #define PHB_CTRLR_IRQ_PGSZ_64K PPC_BIT(11) |
| 234 | #define PHB_CTRLR_IRQ_STORE_EOI PPC_BIT(12) |
| 235 | #define PHB_CTRLR_MMIO_RD_STRICT PPC_BIT(13) |
| 236 | #define PHB_CTRLR_MMIO_EEH_DISABLE PPC_BIT(14) |
| 237 | #define PHB_CTRLR_CFG_EEH_BLOCK PPC_BIT(15) |
| 238 | #define PHB_CTRLR_FENCE_LNKILL_DIS PPC_BIT(16) |
| 239 | #define PHB_CTRLR_TVT_ADDR_SEL PPC_BITMASK(17, 19) |
| 240 | #define TVT_DD1_1_PER_PE 0 |
| 241 | #define TVT_DD1_2_PER_PE 1 |
| 242 | #define TVT_DD1_4_PER_PE 2 |
| 243 | #define TVT_DD1_8_PER_PE 3 |
| 244 | #define TVT_DD1_16_PER_PE 4 |
| 245 | #define TVT_2_PER_PE 0 |
| 246 | #define TVT_4_PER_PE 1 |
| 247 | #define TVT_8_PER_PE 2 |
| 248 | #define TVT_16_PER_PE 3 |
| 249 | #define PHB_CTRLR_DMA_RD_SPACING PPC_BITMASK(28, 31) |
| 250 | #define PHB_AIB_FENCE_CTRL 0x860 |
| 251 | #define PHB_TCE_TAG_ENABLE 0x868 |
| 252 | #define PHB_TCE_WATERMARK 0x870 |
| 253 | #define PHB_TIMEOUT_CTRL1 0x878 |
| 254 | #define PHB_TIMEOUT_CTRL2 0x880 |
| 255 | #define PHB_Q_DMA_R 0x888 |
| 256 | #define PHB_Q_DMA_R_QUIESCE_DMA PPC_BIT(0) |
| 257 | #define PHB_Q_DMA_R_AUTORESET PPC_BIT(1) |
| 258 | #define PHB_Q_DMA_R_DMA_RESP_STATUS PPC_BIT(4) |
| 259 | #define PHB_Q_DMA_R_MMIO_RESP_STATUS PPC_BIT(5) |
| 260 | #define PHB_Q_DMA_R_TCE_RESP_STATUS PPC_BIT(6) |
| 261 | #define PHB_Q_DMA_R_TCE_KILL_STATUS PPC_BIT(7) |
| 262 | #define PHB_TCE_TAG_STATUS 0x908 |
| 263 | |
| 264 | /* FIR & Error registers */ |
| 265 | #define PHB_LEM_FIR_ACCUM 0xc00 |
| 266 | #define PHB_LEM_FIR_AND_MASK 0xc08 |
| 267 | #define PHB_LEM_FIR_OR_MASK 0xc10 |
| 268 | #define PHB_LEM_ERROR_MASK 0xc18 |
| 269 | #define PHB_LEM_ERROR_AND_MASK 0xc20 |
| 270 | #define PHB_LEM_ERROR_OR_MASK 0xc28 |
| 271 | #define PHB_LEM_ACTION0 0xc30 |
| 272 | #define PHB_LEM_ACTION1 0xc38 |
| 273 | #define PHB_LEM_WOF 0xc40 |
| 274 | #define PHB_ERR_STATUS 0xc80 |
| 275 | #define PHB_ERR1_STATUS 0xc88 |
| 276 | #define PHB_ERR_INJECT 0xc90 |
| 277 | #define PHB_ERR_LEM_ENABLE 0xc98 |
| 278 | #define PHB_ERR_IRQ_ENABLE 0xca0 |
| 279 | #define PHB_ERR_FREEZE_ENABLE 0xca8 |
| 280 | #define PHB_ERR_AIB_FENCE_ENABLE 0xcb0 |
| 281 | #define PHB_ERR_LOG_0 0xcc0 |
| 282 | #define PHB_ERR_LOG_1 0xcc8 |
| 283 | #define PHB_ERR_STATUS_MASK 0xcd0 |
| 284 | #define PHB_ERR1_STATUS_MASK 0xcd8 |
| 285 | |
| 286 | #define PHB_TXE_ERR_STATUS 0xd00 |
| 287 | #define PHB_TXE_ERR1_STATUS 0xd08 |
| 288 | #define PHB_TXE_ERR_INJECT 0xd10 |
| 289 | #define PHB_TXE_ERR_LEM_ENABLE 0xd18 |
| 290 | #define PHB_TXE_ERR_IRQ_ENABLE 0xd20 |
| 291 | #define PHB_TXE_ERR_FREEZE_ENABLE 0xd28 |
| 292 | #define PHB_TXE_ERR_AIB_FENCE_ENABLE 0xd30 |
| 293 | #define PHB_TXE_ERR_LOG_0 0xd40 |
| 294 | #define PHB_TXE_ERR_LOG_1 0xd48 |
| 295 | #define PHB_TXE_ERR_STATUS_MASK 0xd50 |
| 296 | #define PHB_TXE_ERR1_STATUS_MASK 0xd58 |
| 297 | |
| 298 | #define PHB_RXE_ARB_ERR_STATUS 0xd80 |
| 299 | #define PHB_RXE_ARB_ERR1_STATUS 0xd88 |
| 300 | #define PHB_RXE_ARB_ERR_INJECT 0xd90 |
| 301 | #define PHB_RXE_ARB_ERR_LEM_ENABLE 0xd98 |
| 302 | #define PHB_RXE_ARB_ERR_IRQ_ENABLE 0xda0 |
| 303 | #define PHB_RXE_ARB_ERR_FREEZE_ENABLE 0xda8 |
| 304 | #define PHB_RXE_ARB_ERR_AIB_FENCE_ENABLE 0xdb0 |
| 305 | #define PHB_RXE_ARB_ERR_LOG_0 0xdc0 |
| 306 | #define PHB_RXE_ARB_ERR_LOG_1 0xdc8 |
| 307 | #define PHB_RXE_ARB_ERR_STATUS_MASK 0xdd0 |
| 308 | #define PHB_RXE_ARB_ERR1_STATUS_MASK 0xdd8 |
| 309 | |
| 310 | #define PHB_RXE_MRG_ERR_STATUS 0xe00 |
| 311 | #define PHB_RXE_MRG_ERR1_STATUS 0xe08 |
| 312 | #define PHB_RXE_MRG_ERR_INJECT 0xe10 |
| 313 | #define PHB_RXE_MRG_ERR_LEM_ENABLE 0xe18 |
| 314 | #define PHB_RXE_MRG_ERR_IRQ_ENABLE 0xe20 |
| 315 | #define PHB_RXE_MRG_ERR_FREEZE_ENABLE 0xe28 |
| 316 | #define PHB_RXE_MRG_ERR_AIB_FENCE_ENABLE 0xe30 |
| 317 | #define PHB_RXE_MRG_ERR_LOG_0 0xe40 |
| 318 | #define PHB_RXE_MRG_ERR_LOG_1 0xe48 |
| 319 | #define PHB_RXE_MRG_ERR_STATUS_MASK 0xe50 |
| 320 | #define PHB_RXE_MRG_ERR1_STATUS_MASK 0xe58 |
| 321 | |
| 322 | #define PHB_RXE_TCE_ERR_STATUS 0xe80 |
| 323 | #define PHB_RXE_TCE_ERR1_STATUS 0xe88 |
| 324 | #define PHB_RXE_TCE_ERR_INJECT 0xe90 |
| 325 | #define PHB_RXE_TCE_ERR_LEM_ENABLE 0xe98 |
| 326 | #define PHB_RXE_TCE_ERR_IRQ_ENABLE 0xea0 |
| 327 | #define PHB_RXE_TCE_ERR_FREEZE_ENABLE 0xea8 |
| 328 | #define PHB_RXE_TCE_ERR_AIB_FENCE_ENABLE 0xeb0 |
| 329 | #define PHB_RXE_TCE_ERR_LOG_0 0xec0 |
| 330 | #define PHB_RXE_TCE_ERR_LOG_1 0xec8 |
| 331 | #define PHB_RXE_TCE_ERR_STATUS_MASK 0xed0 |
| 332 | #define PHB_RXE_TCE_ERR1_STATUS_MASK 0xed8 |
| 333 | |
| 334 | /* Performance monitor & Debug registers */ |
| 335 | #define PHB_TRACE_CONTROL 0xf80 |
| 336 | #define PHB_PERFMON_CONFIG 0xf88 |
| 337 | #define PHB_PERFMON_CTR0 0xf90 |
| 338 | #define PHB_PERFMON_CTR1 0xf98 |
| 339 | #define PHB_PERFMON_CTR2 0xfa0 |
| 340 | #define PHB_PERFMON_CTR3 0xfa8 |
| 341 | |
| 342 | /* Root complex config space memory mapped */ |
| 343 | #define PHB_RC_CONFIG_BASE 0x1000 |
| 344 | #define PHB_RC_CONFIG_SIZE 0x800 |
| 345 | |
| 346 | /* PHB4 REGB registers */ |
| 347 | |
| 348 | /* PBL core */ |
| 349 | #define PHB_PBL_CONTROL 0x1800 |
| 350 | #define PHB_PBL_TIMEOUT_CTRL 0x1810 |
| 351 | #define PHB_PBL_NPTAG_ENABLE 0x1820 |
| 352 | #define PHB_PBL_NBW_CMP_MASK 0x1830 |
| 353 | #define PHB_PBL_NBW_MASK_ENABLE PPC_BIT(63) |
| 354 | #define PHB_PBL_SYS_LINK_INIT 0x1838 |
| 355 | #define PHB_PBL_BUF_STATUS 0x1840 |
| 356 | #define PHB_PBL_ERR_STATUS 0x1900 |
| 357 | #define PHB_PBL_ERR1_STATUS 0x1908 |
| 358 | #define PHB_PBL_ERR_INJECT 0x1910 |
| 359 | #define PHB_PBL_ERR_INF_ENABLE 0x1920 |
| 360 | #define PHB_PBL_ERR_ERC_ENABLE 0x1928 |
| 361 | #define PHB_PBL_ERR_FAT_ENABLE 0x1930 |
| 362 | #define PHB_PBL_ERR_LOG_0 0x1940 |
| 363 | #define PHB_PBL_ERR_LOG_1 0x1948 |
| 364 | #define PHB_PBL_ERR_STATUS_MASK 0x1950 |
| 365 | #define PHB_PBL_ERR1_STATUS_MASK 0x1958 |
| 366 | |
| 367 | /* PCI-E stack */ |
| 368 | #define PHB_PCIE_SCR 0x1A00 |
| 369 | #define PHB_PCIE_SCR_SLOT_CAP PPC_BIT(15) |
| 370 | #define PHB_PCIE_SCR_MAXLINKSPEED PPC_BITMASK(32, 35) |
| 371 | |
| 372 | |
| 373 | #define PHB_PCIE_CRESET 0x1A10 |
| 374 | #define PHB_PCIE_CRESET_CFG_CORE PPC_BIT(0) |
| 375 | #define PHB_PCIE_CRESET_TLDLP PPC_BIT(1) |
| 376 | #define PHB_PCIE_CRESET_PBL PPC_BIT(2) |
| 377 | #define PHB_PCIE_CRESET_PERST_N PPC_BIT(3) |
| 378 | #define PHB_PCIE_CRESET_PIPE_N PPC_BIT(4) |
| 379 | |
| 380 | |
| 381 | #define PHB_PCIE_HOTPLUG_STATUS 0x1A20 |
| 382 | #define PHB_PCIE_HPSTAT_PRESENCE PPC_BIT(10) |
| 383 | |
| 384 | #define PHB_PCIE_DLP_TRAIN_CTL 0x1A40 |
| 385 | #define PHB_PCIE_DLP_LINK_WIDTH PPC_BITMASK(30, 35) |
| 386 | #define PHB_PCIE_DLP_LINK_SPEED PPC_BITMASK(36, 39) |
| 387 | #define PHB_PCIE_DLP_LTSSM_TRC PPC_BITMASK(24, 27) |
| 388 | #define PHB_PCIE_DLP_LTSSM_RESET 0 |
| 389 | #define PHB_PCIE_DLP_LTSSM_DETECT 1 |
| 390 | #define PHB_PCIE_DLP_LTSSM_POLLING 2 |
| 391 | #define PHB_PCIE_DLP_LTSSM_CONFIG 3 |
| 392 | #define PHB_PCIE_DLP_LTSSM_L0 4 |
| 393 | #define PHB_PCIE_DLP_LTSSM_REC 5 |
| 394 | #define PHB_PCIE_DLP_LTSSM_L1 6 |
| 395 | #define PHB_PCIE_DLP_LTSSM_L2 7 |
| 396 | #define PHB_PCIE_DLP_LTSSM_HOTRESET 8 |
| 397 | #define PHB_PCIE_DLP_LTSSM_DISABLED 9 |
| 398 | #define PHB_PCIE_DLP_LTSSM_LOOPBACK 10 |
| 399 | #define PHB_PCIE_DLP_TL_LINKACT PPC_BIT(23) |
| 400 | #define PHB_PCIE_DLP_DL_PGRESET PPC_BIT(22) |
| 401 | #define PHB_PCIE_DLP_TRAINING PPC_BIT(20) |
| 402 | #define PHB_PCIE_DLP_INBAND_PRESENCE PPC_BIT(19) |
| 403 | |
| 404 | #define PHB_PCIE_DLP_CTL 0x1A78 |
| 405 | #define PHB_PCIE_DLP_CTL_BYPASS_PH2 PPC_BIT(4) |
| 406 | #define PHB_PCIE_DLP_CTL_BYPASS_PH3 PPC_BIT(5) |
| 407 | |
| 408 | #define PHB_PCIE_DLP_TRWCTL 0x1A80 |
| 409 | #define PHB_PCIE_DLP_TRWCTL_EN PPC_BIT(0) |
| 410 | |
| 411 | #define PHB_PCIE_DLP_ERRLOG1 0x1AA0 |
| 412 | #define PHB_PCIE_DLP_ERRLOG2 0x1AA8 |
| 413 | #define PHB_PCIE_DLP_ERR_STATUS 0x1AB0 |
| 414 | #define PHB_PCIE_DLP_ERR_COUNTERS 0x1AB8 |
| 415 | |
| 416 | #define PHB_PCIE_LANE_EQ_CNTL0 0x1AD0 |
| 417 | #define PHB_PCIE_LANE_EQ_CNTL1 0x1AD8 |
| 418 | #define PHB_PCIE_LANE_EQ_CNTL2 0x1AE0 |
| 419 | #define PHB_PCIE_LANE_EQ_CNTL3 0x1AE8 |
| 420 | #define PHB_PCIE_LANE_EQ_CNTL20 0x1AF0 |
| 421 | #define PHB_PCIE_LANE_EQ_CNTL21 0x1AF8 |
| 422 | #define PHB_PCIE_LANE_EQ_CNTL22 0x1B00 /* DD1 only */ |
| 423 | #define PHB_PCIE_LANE_EQ_CNTL23 0x1B08 /* DD1 only */ |
| 424 | #define PHB_PCIE_TRACE_CTRL 0x1B20 |
| 425 | #define PHB_PCIE_MISC_STRAP 0x1B30 |
| 426 | |
| 427 | /* Error */ |
| 428 | #define PHB_REGB_ERR_STATUS 0x1C00 |
| 429 | #define PHB_REGB_ERR1_STATUS 0x1C08 |
| 430 | #define PHB_REGB_ERR_INJECT 0x1C10 |
| 431 | #define PHB_REGB_ERR_INF_ENABLE 0x1C20 |
| 432 | #define PHB_REGB_ERR_ERC_ENABLE 0x1C28 |
| 433 | #define PHB_REGB_ERR_FAT_ENABLE 0x1C30 |
| 434 | #define PHB_REGB_ERR_LOG_0 0x1C40 |
| 435 | #define PHB_REGB_ERR_LOG_1 0x1C48 |
| 436 | #define PHB_REGB_ERR_STATUS_MASK 0x1C50 |
| 437 | #define PHB_REGB_ERR1_STATUS_MASK 0x1C58 |
| 438 | |
| 439 | /* |
| 440 | * IODA3 on-chip tables |
| 441 | */ |
| 442 | |
| 443 | #define IODA3_TBL_LIST 1 |
| 444 | #define IODA3_TBL_MIST 2 |
| 445 | #define IODA3_TBL_RCAM 5 |
| 446 | #define IODA3_TBL_MRT 6 |
| 447 | #define IODA3_TBL_PESTA 7 |
| 448 | #define IODA3_TBL_PESTB 8 |
| 449 | #define IODA3_TBL_TVT 9 |
| 450 | #define IODA3_TBL_TCR 10 |
| 451 | #define IODA3_TBL_TDR 11 |
| 452 | #define IODA3_TBL_MBT 16 |
| 453 | #define IODA3_TBL_MDT 17 |
| 454 | #define IODA3_TBL_PEEV 20 |
| 455 | |
| 456 | /* LIST */ |
| 457 | #define IODA3_LIST_P PPC_BIT(6) |
| 458 | #define IODA3_LIST_Q PPC_BIT(7) |
| 459 | #define IODA3_LIST_STATE PPC_BIT(14) |
| 460 | |
| 461 | /* MIST */ |
| 462 | #define IODA3_MIST_P3 PPC_BIT(48 + 0) |
| 463 | #define IODA3_MIST_Q3 PPC_BIT(48 + 1) |
| 464 | #define IODA3_MIST_PE3 PPC_BITMASK(48 + 4, 48 + 15) |
| 465 | |
| 466 | /* TVT */ |
| 467 | #define IODA3_TVT_TABLE_ADDR PPC_BITMASK(0, 47) |
| 468 | #define IODA3_TVT_NUM_LEVELS PPC_BITMASK(48, 50) |
| 469 | #define IODA3_TVE_1_LEVEL 0 |
| 470 | #define IODA3_TVE_2_LEVELS 1 |
| 471 | #define IODA3_TVE_3_LEVELS 2 |
| 472 | #define IODA3_TVE_4_LEVELS 3 |
| 473 | #define IODA3_TVE_5_LEVELS 4 |
| 474 | #define IODA3_TVT_TCE_TABLE_SIZE PPC_BITMASK(51, 55) |
| 475 | #define IODA3_TVT_NON_TRANSLATE_50 PPC_BIT(56) |
| 476 | #define IODA3_TVT_IO_PSIZE PPC_BITMASK(59, 63) |
| 477 | |
| 478 | /* PESTA */ |
| 479 | #define IODA3_PESTA_MMIO_FROZEN PPC_BIT(0) |
| 480 | #define IODA3_PESTA_TRANS_TYPE PPC_BITMASK(5, 7) |
| 481 | #define IODA3_PESTA_TRANS_TYPE_MMIOLOAD 0x4 |
| 482 | #define IODA3_PESTA_CA_CMPLT_TMT PPC_BIT(8) |
| 483 | #define IODA3_PESTA_UR PPC_BIT(9) |
| 484 | |
| 485 | /* PESTB */ |
| 486 | #define IODA3_PESTB_DMA_STOPPED PPC_BIT(0) |
| 487 | |
| 488 | /* MDT */ |
| 489 | /* FIXME: check this field with Eric and add a B, C and D */ |
| 490 | #define IODA3_MDT_PE_A PPC_BITMASK(0, 15) |
| 491 | #define IODA3_MDT_PE_B PPC_BITMASK(16, 31) |
| 492 | #define IODA3_MDT_PE_C PPC_BITMASK(32, 47) |
| 493 | #define IODA3_MDT_PE_D PPC_BITMASK(48, 63) |
| 494 | |
| 495 | /* MBT */ |
| 496 | #define IODA3_MBT0_ENABLE PPC_BIT(0) |
| 497 | #define IODA3_MBT0_TYPE PPC_BIT(1) |
| 498 | #define IODA3_MBT0_TYPE_M32 IODA3_MBT0_TYPE |
| 499 | #define IODA3_MBT0_TYPE_M64 0 |
| 500 | #define IODA3_MBT0_MODE PPC_BITMASK(2, 3) |
| 501 | #define IODA3_MBT0_MODE_PE_SEG 0 |
| 502 | #define IODA3_MBT0_MODE_MDT 1 |
| 503 | #define IODA3_MBT0_MODE_SINGLE_PE 2 |
| 504 | #define IODA3_MBT0_SEG_DIV PPC_BITMASK(4, 5) |
| 505 | #define IODA3_MBT0_SEG_DIV_MAX 0 |
| 506 | #define IODA3_MBT0_SEG_DIV_128 1 |
| 507 | #define IODA3_MBT0_SEG_DIV_64 2 |
| 508 | #define IODA3_MBT0_SEG_DIV_8 3 |
| 509 | #define IODA3_MBT0_MDT_COLUMN PPC_BITMASK(4, 5) |
| 510 | #define IODA3_MBT0_BASE_ADDR PPC_BITMASK(8, 51) |
| 511 | |
| 512 | #define IODA3_MBT1_ENABLE PPC_BIT(0) |
| 513 | #define IODA3_MBT1_MASK PPC_BITMASK(8, 51) |
| 514 | #define IODA3_MBT1_SEG_BASE PPC_BITMASK(55, 63) |
| 515 | #define IODA3_MBT1_SINGLE_PE_NUM PPC_BITMASK(55, 63) |
| 516 | |
| 517 | /* |
| 518 | * IODA3 in-memory tables |
| 519 | */ |
| 520 | |
| 521 | /* |
| 522 | * PEST |
| 523 | * |
| 524 | * 2x8 bytes entries, PEST0 and PEST1 |
| 525 | */ |
| 526 | |
| 527 | #define IODA3_PEST0_MMIO_CAUSE PPC_BIT(2) |
| 528 | #define IODA3_PEST0_CFG_READ PPC_BIT(3) |
| 529 | #define IODA3_PEST0_CFG_WRITE PPC_BIT(4) |
| 530 | #define IODA3_PEST0_TTYPE PPC_BITMASK(5, 7) |
| 531 | #define PEST_TTYPE_DMA_WRITE 0 |
| 532 | #define PEST_TTYPE_MSI 1 |
| 533 | #define PEST_TTYPE_DMA_READ 2 |
| 534 | #define PEST_TTYPE_DMA_READ_RESP 3 |
| 535 | #define PEST_TTYPE_MMIO_LOAD 4 |
| 536 | #define PEST_TTYPE_MMIO_STORE 5 |
| 537 | #define PEST_TTYPE_OTHER 7 |
| 538 | #define IODA3_PEST0_CA_RETURN PPC_BIT(8) |
| 539 | #define IODA3_PEST0_UR_RETURN PPC_BIT(9) |
| 540 | #define IODA3_PEST0_PCIE_NONFATAL PPC_BIT(10) |
| 541 | #define IODA3_PEST0_PCIE_FATAL PPC_BIT(11) |
| 542 | #define IODA3_PEST0_PARITY_UE PPC_BIT(13) |
| 543 | #define IODA3_PEST0_PCIE_CORRECTABLE PPC_BIT(14) |
| 544 | #define IODA3_PEST0_PCIE_INTERRUPT PPC_BIT(15) |
| 545 | #define IODA3_PEST0_MMIO_XLATE PPC_BIT(16) |
| 546 | #define IODA3_PEST0_IODA3_ERROR PPC_BIT(16) /* Same bit as MMIO xlate */ |
| 547 | #define IODA3_PEST0_TCE_PAGE_FAULT PPC_BIT(18) |
| 548 | #define IODA3_PEST0_TCE_ACCESS_FAULT PPC_BIT(19) |
| 549 | #define IODA3_PEST0_DMA_RESP_TIMEOUT PPC_BIT(20) |
| 550 | #define IODA3_PEST0_AIB_SIZE_INVALID PPC_BIT(21) |
| 551 | #define IODA3_PEST0_LEM_BIT PPC_BITMASK(26, 31) |
| 552 | #define IODA3_PEST0_RID PPC_BITMASK(32, 47) |
| 553 | #define IODA3_PEST0_MSI_DATA PPC_BITMASK(48, 63) |
| 554 | |
| 555 | #define IODA3_PEST1_FAIL_ADDR PPC_BITMASK(3, 63) |
| 556 | |
| 557 | |
| 558 | #endif /* PCI_HOST_PNV_PHB4_REGS_H */ |