| 1 | /* |
| 2 | * QEMU SPAPR PCI BUS definitions |
| 3 | * |
| 4 | * Copyright (c) 2011 Alexey Kardashevskiy <aik@au1.ibm.com> |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2.1 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #ifndef PCI_HOST_SPAPR_H |
| 21 | #define PCI_HOST_SPAPR_H |
| 22 | |
| 23 | #include "hw/ppc/spapr.h" |
| 24 | #include "hw/pci/pci.h" |
| 25 | #include "hw/pci/pci_host.h" |
| 26 | #include "hw/ppc/xics.h" |
| 27 | #include "qom/object.h" |
| 28 | |
| 29 | #define TYPE_SPAPR_PCI_HOST_BRIDGE "spapr-pci-host-bridge" |
| 30 | |
| 31 | OBJECT_DECLARE_SIMPLE_TYPE(SpaprPhbState, SPAPR_PCI_HOST_BRIDGE) |
| 32 | |
| 33 | #define SPAPR_PCI_DMA_MAX_WINDOWS 2 |
| 34 | |
| 35 | |
| 36 | typedef struct SpaprPciMsi { |
| 37 | uint32_t first_irq; |
| 38 | uint32_t num; |
| 39 | } SpaprPciMsi; |
| 40 | |
| 41 | typedef struct SpaprPciMsiMig { |
| 42 | uint32_t key; |
| 43 | SpaprPciMsi value; |
| 44 | } SpaprPciMsiMig; |
| 45 | |
| 46 | typedef struct SpaprPciLsi { |
| 47 | uint32_t irq; |
| 48 | } SpaprPciLsi; |
| 49 | |
| 50 | struct SpaprPhbState { |
| 51 | PCIHostState parent_obj; |
| 52 | |
| 53 | uint32_t index; |
| 54 | uint64_t buid; |
| 55 | char *dtbusname; |
| 56 | |
| 57 | MemoryRegion memspace, iospace; |
| 58 | hwaddr mem_win_addr, mem_win_size, mem64_win_addr, mem64_win_size; |
| 59 | uint64_t mem64_win_pciaddr; |
| 60 | hwaddr io_win_addr, io_win_size; |
| 61 | MemoryRegion mem32window, mem64window, iowindow, msiwindow; |
| 62 | |
| 63 | uint32_t dma_liobn[SPAPR_PCI_DMA_MAX_WINDOWS]; |
| 64 | hwaddr dma_win_addr, dma_win_size; |
| 65 | AddressSpace iommu_as; |
| 66 | MemoryRegion iommu_root; |
| 67 | |
| 68 | SpaprPciLsi lsi_table[PCI_NUM_PINS]; |
| 69 | |
| 70 | GHashTable *msi; |
| 71 | /* Temporary cache for migration purposes */ |
| 72 | int32_t msi_devs_num; |
| 73 | SpaprPciMsiMig *msi_devs; |
| 74 | |
| 75 | QLIST_ENTRY(SpaprPhbState) list; |
| 76 | |
| 77 | bool ddw_enabled; |
| 78 | uint64_t page_size_mask; |
| 79 | uint64_t dma64_win_addr; |
| 80 | |
| 81 | uint32_t numa_node; |
| 82 | |
| 83 | bool pcie_ecs; /* Allow access to PCIe extended config space? */ |
| 84 | |
| 85 | /* Fields for migration compatibility hacks */ |
| 86 | bool pre_5_1_assoc; |
| 87 | }; |
| 88 | |
| 89 | #define SPAPR_PCI_MEM_WIN_BUS_OFFSET 0x80000000ULL |
| 90 | #define SPAPR_PCI_MEM32_WIN_SIZE \ |
| 91 | ((1ULL << 32) - SPAPR_PCI_MEM_WIN_BUS_OFFSET) |
| 92 | #define SPAPR_PCI_MEM64_WIN_SIZE 0x10000000000ULL /* 1 TiB */ |
| 93 | |
| 94 | /* All PCI outbound windows will be within this range */ |
| 95 | #define SPAPR_PCI_BASE (1ULL << 45) /* 32 TiB */ |
| 96 | #define SPAPR_PCI_LIMIT (1ULL << 46) /* 64 TiB */ |
| 97 | |
| 98 | #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \ |
| 99 | SPAPR_PCI_MEM64_WIN_SIZE - 1) |
| 100 | |
| 101 | #define SPAPR_PCI_IO_WIN_SIZE 0x10000 |
| 102 | |
| 103 | #define SPAPR_PCI_MSI_WINDOW 0x40000000000ULL |
| 104 | |
| 105 | int spapr_dt_phb(SpaprMachineState *spapr, SpaprPhbState *phb, |
| 106 | uint32_t intc_phandle, void *fdt, int *node_offset); |
| 107 | |
| 108 | void spapr_pci_rtas_init(void); |
| 109 | |
| 110 | SpaprPhbState *spapr_pci_find_phb(SpaprMachineState *spapr, uint64_t buid); |
| 111 | PCIDevice *spapr_pci_find_dev(SpaprMachineState *spapr, uint64_t buid, |
| 112 | uint32_t config_addr); |
| 113 | |
| 114 | /* DRC callbacks */ |
| 115 | void spapr_phb_remove_pci_device_cb(DeviceState *dev); |
| 116 | int spapr_pci_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, |
| 117 | void *fdt, int *fdt_start_offset, Error **errp); |
| 118 | |
| 119 | /* VFIO EEH hooks */ |
| 120 | #ifdef CONFIG_LINUX |
| 121 | bool spapr_phb_eeh_available(SpaprPhbState *sphb); |
| 122 | int spapr_phb_vfio_eeh_set_option(SpaprPhbState *sphb, |
| 123 | unsigned int addr, int option); |
| 124 | int spapr_phb_vfio_eeh_get_state(SpaprPhbState *sphb, int *state); |
| 125 | int spapr_phb_vfio_eeh_reset(SpaprPhbState *sphb, int option); |
| 126 | int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb); |
| 127 | void spapr_phb_vfio_reset(DeviceState *qdev); |
| 128 | #else |
| 129 | static inline bool spapr_phb_eeh_available(SpaprPhbState *sphb) |
| 130 | { |
| 131 | return false; |
| 132 | } |
| 133 | static inline int spapr_phb_vfio_eeh_set_option(SpaprPhbState *sphb, |
| 134 | unsigned int addr, int option) |
| 135 | { |
| 136 | return RTAS_OUT_HW_ERROR; |
| 137 | } |
| 138 | static inline int spapr_phb_vfio_eeh_get_state(SpaprPhbState *sphb, |
| 139 | int *state) |
| 140 | { |
| 141 | return RTAS_OUT_HW_ERROR; |
| 142 | } |
| 143 | static inline int spapr_phb_vfio_eeh_reset(SpaprPhbState *sphb, int option) |
| 144 | { |
| 145 | return RTAS_OUT_HW_ERROR; |
| 146 | } |
| 147 | static inline int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb) |
| 148 | { |
| 149 | return RTAS_OUT_HW_ERROR; |
| 150 | } |
| 151 | static inline void spapr_phb_vfio_reset(DeviceState *qdev) |
| 152 | { |
| 153 | } |
| 154 | #endif |
| 155 | |
| 156 | void spapr_phb_dma_reset(SpaprPhbState *sphb); |
| 157 | |
| 158 | static inline unsigned spapr_phb_windows_supported(SpaprPhbState *sphb) |
| 159 | { |
| 160 | return sphb->ddw_enabled ? SPAPR_PCI_DMA_MAX_WINDOWS : 1; |
| 161 | } |
| 162 | |
| 163 | char *spapr_pci_fw_dev_name(PCIDevice *dev); |
| 164 | |
| 165 | #endif /* PCI_HOST_SPAPR_H */ |