| 1 | #ifndef QEMU_PCI_H |
| 2 | #define QEMU_PCI_H |
| 3 | |
| 4 | #include "system/memory.h" |
| 5 | #include "system/dma.h" |
| 6 | #include "system/host_iommu_device.h" |
| 7 | |
| 8 | /* PCI includes legacy ISA access. */ |
| 9 | #include "hw/isa/isa.h" |
| 10 | |
| 11 | extern bool pci_available; |
| 12 | |
| 13 | /* PCI bus */ |
| 14 | |
| 15 | #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) |
| 16 | #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) |
| 17 | #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) |
| 18 | #define PCI_FUNC(devfn) ((devfn) & 0x07) |
| 19 | #define PCI_BUILD_BDF(bus, devfn) (((bus) << 8) | (devfn)) |
| 20 | #define PCI_BDF_TO_DEVFN(x) ((x) & 0xff) |
| 21 | #define PCI_BUS_MAX 256 |
| 22 | #define PCI_DEVFN_MAX 256 |
| 23 | #define PCI_SLOT_MAX 32 |
| 24 | #define PCI_FUNC_MAX 8 |
| 25 | |
| 26 | #define PCI_SBDF(seg, bus, dev, func) \ |
| 27 | ((((uint32_t)(seg)) << 16) | \ |
| 28 | (PCI_BUILD_BDF(bus, PCI_DEVFN(dev, func)))) |
| 29 | |
| 30 | /* Class, Vendor and Device IDs from Linux's pci_ids.h */ |
| 31 | #include "hw/pci/pci_ids.h" |
| 32 | |
| 33 | /* QEMU-specific Vendor and Device ID definitions */ |
| 34 | |
| 35 | /* IBM (0x1014) */ |
| 36 | #define PCI_DEVICE_ID_IBM_440GX 0x027f |
| 37 | #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff |
| 38 | |
| 39 | /* Hitachi (0x1054) */ |
| 40 | #define PCI_VENDOR_ID_HITACHI 0x1054 |
| 41 | #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e |
| 42 | |
| 43 | /* Apple (0x106b) */ |
| 44 | #define PCI_DEVICE_ID_APPLE_343S1201 0x0010 |
| 45 | #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e |
| 46 | #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f |
| 47 | #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022 |
| 48 | #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f |
| 49 | |
| 50 | /* Realtek (0x10ec) */ |
| 51 | #define PCI_DEVICE_ID_REALTEK_8029 0x8029 |
| 52 | |
| 53 | /* Xilinx (0x10ee) */ |
| 54 | #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300 |
| 55 | |
| 56 | /* Marvell (0x11ab) */ |
| 57 | #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620 |
| 58 | |
| 59 | /* QEMU/Bochs VGA (0x1234) */ |
| 60 | #define PCI_VENDOR_ID_QEMU 0x1234 |
| 61 | #define PCI_DEVICE_ID_QEMU_VGA 0x1111 |
| 62 | #define PCI_DEVICE_ID_QEMU_IPMI 0x1112 |
| 63 | |
| 64 | /* VMWare (0x15ad) */ |
| 65 | #define PCI_VENDOR_ID_VMWARE 0x15ad |
| 66 | #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 |
| 67 | #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 |
| 68 | #define PCI_DEVICE_ID_VMWARE_NET 0x0720 |
| 69 | #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 |
| 70 | #define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0 |
| 71 | #define PCI_DEVICE_ID_VMWARE_IDE 0x1729 |
| 72 | #define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0 |
| 73 | |
| 74 | /* Intel (0x8086) */ |
| 75 | #define PCI_DEVICE_ID_INTEL_82551IT 0x1209 |
| 76 | #define PCI_DEVICE_ID_INTEL_82557 0x1229 |
| 77 | #define PCI_DEVICE_ID_INTEL_82801IR 0x2922 |
| 78 | |
| 79 | /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */ |
| 80 | #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 |
| 81 | #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 |
| 82 | #define PCI_SUBDEVICE_ID_QEMU 0x1100 |
| 83 | |
| 84 | /* legacy virtio-pci devices */ |
| 85 | #define PCI_DEVICE_ID_VIRTIO_NET 0x1000 |
| 86 | #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 |
| 87 | #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 |
| 88 | #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 |
| 89 | #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004 |
| 90 | #define PCI_DEVICE_ID_VIRTIO_RNG 0x1005 |
| 91 | #define PCI_DEVICE_ID_VIRTIO_9P 0x1009 |
| 92 | #define PCI_DEVICE_ID_VIRTIO_VSOCK 0x1012 |
| 93 | |
| 94 | /* |
| 95 | * modern virtio-pci devices get their id assigned automatically, |
| 96 | * there is no need to add #defines here. It gets calculated as |
| 97 | * |
| 98 | * PCI_DEVICE_ID = PCI_DEVICE_ID_VIRTIO_10_BASE + |
| 99 | * virtio_bus_get_vdev_id(bus) |
| 100 | */ |
| 101 | #define PCI_DEVICE_ID_VIRTIO_10_BASE 0x1040 |
| 102 | |
| 103 | #define PCI_VENDOR_ID_REDHAT 0x1b36 |
| 104 | #define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001 |
| 105 | #define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002 |
| 106 | #define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003 |
| 107 | #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004 |
| 108 | #define PCI_DEVICE_ID_REDHAT_TEST 0x0005 |
| 109 | #define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006 |
| 110 | #define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007 |
| 111 | #define PCI_DEVICE_ID_REDHAT_PCIE_HOST 0x0008 |
| 112 | #define PCI_DEVICE_ID_REDHAT_PXB 0x0009 |
| 113 | #define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a |
| 114 | #define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b |
| 115 | #define PCI_DEVICE_ID_REDHAT_PCIE_RP 0x000c |
| 116 | #define PCI_DEVICE_ID_REDHAT_XHCI 0x000d |
| 117 | #define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e |
| 118 | #define PCI_DEVICE_ID_REDHAT_MDPY 0x000f |
| 119 | #define PCI_DEVICE_ID_REDHAT_NVME 0x0010 |
| 120 | #define PCI_DEVICE_ID_REDHAT_PVPANIC 0x0011 |
| 121 | #define PCI_DEVICE_ID_REDHAT_ACPI_ERST 0x0012 |
| 122 | #define PCI_DEVICE_ID_REDHAT_UFS 0x0013 |
| 123 | #define PCI_DEVICE_ID_REDHAT_RISCV_IOMMU 0x0014 |
| 124 | #define PCI_DEVICE_ID_REDHAT_QXL 0x0100 |
| 125 | |
| 126 | #define FMT_PCIBUS PRIx64 |
| 127 | |
| 128 | typedef uint64_t pcibus_t; |
| 129 | |
| 130 | struct PCIHostDeviceAddress { |
| 131 | unsigned int domain; |
| 132 | unsigned int bus; |
| 133 | unsigned int slot; |
| 134 | unsigned int function; |
| 135 | }; |
| 136 | |
| 137 | /* |
| 138 | * Represents the Address Type (AT) field in a PCI request, |
| 139 | * see MemTxAttrs.address_type |
| 140 | */ |
| 141 | typedef enum PCIAddressType { |
| 142 | PCI_AT_UNTRANSLATED = 0, /* Default when no attribute is set */ |
| 143 | PCI_AT_TRANSLATED = 1, |
| 144 | } PCIAddressType; |
| 145 | |
| 146 | typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, |
| 147 | uint32_t address, uint32_t data, int len); |
| 148 | typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev, |
| 149 | uint32_t address, int len); |
| 150 | typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, |
| 151 | pcibus_t addr, pcibus_t size, int type); |
| 152 | typedef void PCIUnregisterFunc(PCIDevice *pci_dev); |
| 153 | |
| 154 | typedef void MSITriggerFunc(PCIDevice *dev, MSIMessage msg); |
| 155 | typedef MSIMessage MSIPrepareMessageFunc(PCIDevice *dev, unsigned vector); |
| 156 | typedef MSIMessage MSIxPrepareMessageFunc(PCIDevice *dev, unsigned vector); |
| 157 | |
| 158 | typedef struct PCIIORegion { |
| 159 | pcibus_t addr; /* current PCI mapping address. -1 means not mapped */ |
| 160 | #define PCI_BAR_UNMAPPED (~(pcibus_t)0) |
| 161 | pcibus_t size; |
| 162 | uint8_t type; |
| 163 | MemoryRegion *memory; |
| 164 | MemoryRegion *address_space; |
| 165 | } PCIIORegion; |
| 166 | |
| 167 | #define PCI_ROM_SLOT 6 |
| 168 | #define PCI_NUM_REGIONS 7 |
| 169 | |
| 170 | enum { |
| 171 | QEMU_PCI_VGA_MEM, |
| 172 | QEMU_PCI_VGA_IO_LO, |
| 173 | QEMU_PCI_VGA_IO_HI, |
| 174 | QEMU_PCI_VGA_NUM_REGIONS, |
| 175 | }; |
| 176 | |
| 177 | #define QEMU_PCI_VGA_MEM_BASE 0xa0000 |
| 178 | #define QEMU_PCI_VGA_MEM_SIZE 0x20000 |
| 179 | #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0 |
| 180 | #define QEMU_PCI_VGA_IO_LO_SIZE 0xc |
| 181 | #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0 |
| 182 | #define QEMU_PCI_VGA_IO_HI_SIZE 0x20 |
| 183 | |
| 184 | #include "hw/pci/pci_regs.h" |
| 185 | |
| 186 | /* PCI HEADER_TYPE */ |
| 187 | #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 |
| 188 | |
| 189 | /* Size of the standard PCI config header */ |
| 190 | #define PCI_CONFIG_HEADER_SIZE 0x40 |
| 191 | /* Size of the standard PCI config space */ |
| 192 | #define PCI_CONFIG_SPACE_SIZE 0x100 |
| 193 | /* Size of the standard PCIe config space: 4KB */ |
| 194 | #define PCIE_CONFIG_SPACE_SIZE 0x1000 |
| 195 | |
| 196 | #define PCI_NUM_PINS 4 /* A-D */ |
| 197 | |
| 198 | /* Bits in cap_present field. */ |
| 199 | enum { |
| 200 | QEMU_PCI_CAP_MSI = 0x1, |
| 201 | QEMU_PCI_CAP_MSIX = 0x2, |
| 202 | QEMU_PCI_CAP_EXPRESS = 0x4, |
| 203 | |
| 204 | /* multifunction capable device */ |
| 205 | #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3 |
| 206 | QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR), |
| 207 | |
| 208 | /* command register SERR bit enabled - unused since QEMU v5.0 */ |
| 209 | #define QEMU_PCI_CAP_SERR_BITNR 4 |
| 210 | QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR), |
| 211 | /* Standard hot plug controller. */ |
| 212 | #define QEMU_PCI_SHPC_BITNR 5 |
| 213 | QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR), |
| 214 | #define QEMU_PCI_SLOTID_BITNR 6 |
| 215 | QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR), |
| 216 | /* PCI Express capability - Power Controller Present */ |
| 217 | #define QEMU_PCIE_SLTCAP_PCP_BITNR 7 |
| 218 | QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR), |
| 219 | /* Link active status in endpoint capability is always set */ |
| 220 | #define QEMU_PCIE_LNKSTA_DLLLA_BITNR 8 |
| 221 | QEMU_PCIE_LNKSTA_DLLLA = (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR), |
| 222 | #define QEMU_PCIE_CXL_BITNR 10 |
| 223 | QEMU_PCIE_CAP_CXL = (1 << QEMU_PCIE_CXL_BITNR), |
| 224 | #define QEMU_PCIE_ERR_UNC_MASK_BITNR 11 |
| 225 | QEMU_PCIE_ERR_UNC_MASK = (1 << QEMU_PCIE_ERR_UNC_MASK_BITNR), |
| 226 | #define QEMU_PCIE_ARI_NEXTFN_1_BITNR 12 |
| 227 | QEMU_PCIE_ARI_NEXTFN_1 = (1 << QEMU_PCIE_ARI_NEXTFN_1_BITNR), |
| 228 | #define QEMU_PCIE_EXT_TAG_BITNR 13 |
| 229 | QEMU_PCIE_EXT_TAG = (1 << QEMU_PCIE_EXT_TAG_BITNR), |
| 230 | #define QEMU_PCI_CAP_PM_BITNR 14 |
| 231 | QEMU_PCI_CAP_PM = (1 << QEMU_PCI_CAP_PM_BITNR), |
| 232 | #define QEMU_PCI_SKIP_RESET_ON_CPR_BITNR 15 |
| 233 | QEMU_PCI_SKIP_RESET_ON_CPR = (1 << QEMU_PCI_SKIP_RESET_ON_CPR_BITNR), |
| 234 | }; |
| 235 | |
| 236 | typedef struct PCIINTxRoute { |
| 237 | enum { |
| 238 | PCI_INTX_ENABLED, |
| 239 | PCI_INTX_INVERTED, |
| 240 | PCI_INTX_DISABLED, |
| 241 | } mode; |
| 242 | int irq; |
| 243 | } PCIINTxRoute; |
| 244 | |
| 245 | typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev); |
| 246 | typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector, |
| 247 | MSIMessage msg); |
| 248 | typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector); |
| 249 | typedef void (*MSIVectorPollNotifier)(PCIDevice *dev, |
| 250 | unsigned int vector_start, |
| 251 | unsigned int vector_end); |
| 252 | |
| 253 | void pci_register_bar(PCIDevice *pci_dev, int region_num, |
| 254 | uint8_t attr, MemoryRegion *memory); |
| 255 | void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, |
| 256 | MemoryRegion *io_lo, MemoryRegion *io_hi); |
| 257 | void pci_unregister_vga(PCIDevice *pci_dev); |
| 258 | pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num); |
| 259 | |
| 260 | int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, |
| 261 | uint8_t offset, uint8_t size, |
| 262 | Error **errp); |
| 263 | |
| 264 | void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size); |
| 265 | |
| 266 | uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id); |
| 267 | |
| 268 | |
| 269 | uint32_t pci_default_read_config(PCIDevice *d, |
| 270 | uint32_t address, int len); |
| 271 | void pci_default_write_config(PCIDevice *d, |
| 272 | uint32_t address, uint32_t val, int len); |
| 273 | void pci_device_save(PCIDevice *s, QEMUFile *f); |
| 274 | int pci_device_load(PCIDevice *s, QEMUFile *f); |
| 275 | MemoryRegion *pci_address_space(PCIDevice *dev); |
| 276 | MemoryRegion *pci_address_space_io(PCIDevice *dev); |
| 277 | |
| 278 | /* |
| 279 | * Should not normally be used by devices. For use by sPAPR target |
| 280 | * where QEMU emulates firmware. |
| 281 | */ |
| 282 | int pci_bar(PCIDevice *d, int reg); |
| 283 | |
| 284 | typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level); |
| 285 | typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); |
| 286 | typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin); |
| 287 | |
| 288 | #define TYPE_PCI_BUS "PCI" |
| 289 | OBJECT_DECLARE_TYPE(PCIBus, PCIBusClass, PCI_BUS) |
| 290 | #define TYPE_PCIE_BUS "PCIE" |
| 291 | #define TYPE_CXL_BUS "CXL" |
| 292 | |
| 293 | typedef void (*pci_bus_dev_fn)(PCIBus *b, PCIDevice *d, void *opaque); |
| 294 | typedef void (*pci_bus_fn)(PCIBus *b, void *opaque); |
| 295 | typedef void *(*pci_bus_ret_fn)(PCIBus *b, void *opaque); |
| 296 | |
| 297 | bool pci_bus_is_express(const PCIBus *bus); |
| 298 | |
| 299 | void pci_root_bus_init(PCIBus *bus, size_t bus_size, DeviceState *parent, |
| 300 | const char *name, |
| 301 | MemoryRegion *mem, MemoryRegion *io, |
| 302 | uint8_t devfn_min, const char *typename); |
| 303 | PCIBus *pci_root_bus_new(DeviceState *parent, const char *name, |
| 304 | MemoryRegion *mem, MemoryRegion *io, |
| 305 | uint8_t devfn_min, const char *typename); |
| 306 | void pci_root_bus_cleanup(PCIBus *bus); |
| 307 | void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, |
| 308 | void *irq_opaque, int nirq); |
| 309 | void pci_bus_map_irqs(PCIBus *bus, pci_map_irq_fn map_irq); |
| 310 | void pci_bus_irqs_cleanup(PCIBus *bus); |
| 311 | int pci_bus_get_irq_level(PCIBus *bus, int irq_num); |
| 312 | uint32_t pci_bus_get_slot_reserved_mask(PCIBus *bus); |
| 313 | void pci_bus_set_slot_reserved_mask(PCIBus *bus, uint32_t mask); |
| 314 | void pci_bus_clear_slot_reserved_mask(PCIBus *bus, uint32_t mask); |
| 315 | bool pci_bus_add_fw_cfg_extra_pci_roots(FWCfgState *fw_cfg, |
| 316 | PCIBus *bus, |
| 317 | Error **errp); |
| 318 | /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */ |
| 319 | static inline int pci_swizzle(int slot, int pin) |
| 320 | { |
| 321 | return (slot + pin) % PCI_NUM_PINS; |
| 322 | } |
| 323 | int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin); |
| 324 | PCIBus *pci_register_root_bus(DeviceState *parent, const char *name, |
| 325 | pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, |
| 326 | void *irq_opaque, |
| 327 | MemoryRegion *mem, MemoryRegion *io, |
| 328 | uint8_t devfn_min, int nirq, |
| 329 | const char *typename); |
| 330 | void pci_unregister_root_bus(PCIBus *bus); |
| 331 | void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn); |
| 332 | PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin); |
| 333 | bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new); |
| 334 | void pci_bus_fire_intx_routing_notifier(PCIBus *bus); |
| 335 | void pci_device_set_intx_routing_notifier(PCIDevice *dev, |
| 336 | PCIINTxRoutingNotifier notifier); |
| 337 | void pci_device_reset(PCIDevice *dev); |
| 338 | |
| 339 | void pci_init_nic_devices(PCIBus *bus, const char *default_model); |
| 340 | bool pci_init_nic_in_slot(PCIBus *rootbus, const char *default_model, |
| 341 | const char *alias, const char *devaddr); |
| 342 | PCIDevice *pci_vga_init(PCIBus *bus); |
| 343 | |
| 344 | static inline PCIBus *pci_get_bus(const PCIDevice *dev) |
| 345 | { |
| 346 | return PCI_BUS(qdev_get_parent_bus(DEVICE(dev))); |
| 347 | } |
| 348 | int pci_bus_num(PCIBus *s); |
| 349 | void pci_bus_range(PCIBus *bus, int *min_bus, int *max_bus); |
| 350 | static inline int pci_dev_bus_num(const PCIDevice *dev) |
| 351 | { |
| 352 | return pci_bus_num(pci_get_bus(dev)); |
| 353 | } |
| 354 | |
| 355 | int pci_bus_numa_node(PCIBus *bus); |
| 356 | void pci_for_each_device(PCIBus *bus, int bus_num, |
| 357 | pci_bus_dev_fn fn, |
| 358 | void *opaque); |
| 359 | void pci_for_each_device_reverse(PCIBus *bus, int bus_num, |
| 360 | pci_bus_dev_fn fn, |
| 361 | void *opaque); |
| 362 | void pci_for_each_device_under_bus(PCIBus *bus, |
| 363 | pci_bus_dev_fn fn, void *opaque); |
| 364 | void pci_for_each_device_under_bus_reverse(PCIBus *bus, |
| 365 | pci_bus_dev_fn fn, |
| 366 | void *opaque); |
| 367 | void pci_for_each_bus_depth_first(PCIBus *bus, pci_bus_ret_fn begin, |
| 368 | pci_bus_fn end, void *parent_state); |
| 369 | PCIDevice *pci_get_function_0(PCIDevice *pci_dev); |
| 370 | |
| 371 | /* Use this wrapper when specific scan order is not required. */ |
| 372 | static inline |
| 373 | void pci_for_each_bus(PCIBus *bus, pci_bus_fn fn, void *opaque) |
| 374 | { |
| 375 | pci_for_each_bus_depth_first(bus, NULL, fn, opaque); |
| 376 | } |
| 377 | |
| 378 | PCIBus *pci_device_root_bus(const PCIDevice *d); |
| 379 | const char *pci_root_bus_path(PCIDevice *dev); |
| 380 | bool pci_bus_bypass_iommu(PCIBus *bus); |
| 381 | PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn); |
| 382 | int pci_qdev_find_device(const char *id, PCIDevice **pdev); |
| 383 | void pci_qdev_property_add_specifics(DeviceClass *dc); |
| 384 | void pci_bus_get_w64_range(PCIBus *bus, Range *range); |
| 385 | |
| 386 | void pci_device_deassert_intx(PCIDevice *dev); |
| 387 | |
| 388 | /* Page Request Interface */ |
| 389 | typedef enum { |
| 390 | IOMMU_PRI_RESP_SUCCESS, |
| 391 | IOMMU_PRI_RESP_INVALID_REQUEST, |
| 392 | IOMMU_PRI_RESP_FAILURE, |
| 393 | } IOMMUPRIResponseCode; |
| 394 | |
| 395 | typedef struct IOMMUPRIResponse { |
| 396 | IOMMUPRIResponseCode response_code; |
| 397 | uint16_t prgi; |
| 398 | } IOMMUPRIResponse; |
| 399 | |
| 400 | struct IOMMUPRINotifier; |
| 401 | |
| 402 | typedef void (*IOMMUPRINotify)(struct IOMMUPRINotifier *notifier, |
| 403 | IOMMUPRIResponse *response); |
| 404 | |
| 405 | typedef struct IOMMUPRINotifier { |
| 406 | IOMMUPRINotify notify; |
| 407 | } IOMMUPRINotifier; |
| 408 | |
| 409 | #define PCI_PRI_PRGI_MASK 0x1ffU |
| 410 | |
| 411 | /** |
| 412 | * struct PCIIOMMUOps: callbacks structure for specific IOMMU handlers |
| 413 | * of a PCIBus |
| 414 | * |
| 415 | * Allows to modify the behavior of some IOMMU operations of the PCI |
| 416 | * framework for a set of devices on a PCI bus. |
| 417 | */ |
| 418 | typedef struct PCIIOMMUOps { |
| 419 | /** |
| 420 | * @supports_address_space: Optional pre-check to determine whether a PCI |
| 421 | * device can be associated with an IOMMU. If this callback returns true, |
| 422 | * the IOMMU accepts the device association and get_address_space() can be |
| 423 | * called to obtain the address_space to be used. |
| 424 | * |
| 425 | * @bus: the #PCIBus being accessed. |
| 426 | * |
| 427 | * @opaque: the data passed to pci_setup_iommu(). |
| 428 | * |
| 429 | * @devfn: device and function number. |
| 430 | * |
| 431 | * @errp: pass an Error out only when return false |
| 432 | * |
| 433 | * Returns: true if the device can be associated with an IOMMU, false |
| 434 | * otherwise with errp set. |
| 435 | */ |
| 436 | bool (*supports_address_space)(PCIBus *bus, void *opaque, int devfn, |
| 437 | Error **errp); |
| 438 | /** |
| 439 | * @get_address_space: get the address space for a set of devices |
| 440 | * on a PCI bus. |
| 441 | * |
| 442 | * Mandatory callback which returns a pointer to an #AddressSpace |
| 443 | * |
| 444 | * @bus: the #PCIBus being accessed. |
| 445 | * |
| 446 | * @opaque: the data passed to pci_setup_iommu(). |
| 447 | * |
| 448 | * @devfn: device and function number |
| 449 | */ |
| 450 | AddressSpace * (*get_address_space)(PCIBus *bus, void *opaque, int devfn); |
| 451 | /** |
| 452 | * @set_iommu_device: attach a HostIOMMUDevice to a vIOMMU |
| 453 | * |
| 454 | * Optional callback, if not implemented in vIOMMU, then vIOMMU can't |
| 455 | * retrieve host information from the associated HostIOMMUDevice. |
| 456 | * |
| 457 | * @bus: the #PCIBus of the PCI device. |
| 458 | * |
| 459 | * @opaque: the data passed to pci_setup_iommu(). |
| 460 | * |
| 461 | * @devfn: device and function number of the PCI device. |
| 462 | * |
| 463 | * @dev: the #HostIOMMUDevice to attach. |
| 464 | * |
| 465 | * @errp: pass an Error out only when return false |
| 466 | * |
| 467 | * Returns: true if HostIOMMUDevice is attached or else false with errp set. |
| 468 | */ |
| 469 | bool (*set_iommu_device)(PCIBus *bus, void *opaque, int devfn, |
| 470 | HostIOMMUDevice *dev, Error **errp); |
| 471 | /** |
| 472 | * @unset_iommu_device: detach a HostIOMMUDevice from a vIOMMU |
| 473 | * |
| 474 | * Optional callback. |
| 475 | * |
| 476 | * @bus: the #PCIBus of the PCI device. |
| 477 | * |
| 478 | * @opaque: the data passed to pci_setup_iommu(). |
| 479 | * |
| 480 | * @devfn: device and function number of the PCI device. |
| 481 | */ |
| 482 | void (*unset_iommu_device)(PCIBus *bus, void *opaque, int devfn); |
| 483 | /** |
| 484 | * @get_viommu_flags: get vIOMMU flags |
| 485 | * |
| 486 | * Optional callback, if not implemented, then vIOMMU doesn't support |
| 487 | * exposing flags to other sub-system, e.g., VFIO. |
| 488 | * |
| 489 | * @opaque: the data passed to pci_setup_iommu(). |
| 490 | * |
| 491 | * Returns: bitmap with each bit representing a vIOMMU flag defined in |
| 492 | * enum viommu_flags. |
| 493 | */ |
| 494 | uint64_t (*get_viommu_flags)(void *opaque); |
| 495 | /** |
| 496 | * @get_host_iommu_quirks: get host IOMMU quirks |
| 497 | * |
| 498 | * Optional callback, if not implemented, then vIOMMU doesn't support |
| 499 | * converting @type specific hardware information data into a standard |
| 500 | * bitmap format. |
| 501 | * |
| 502 | * @type: IOMMU hardware info type |
| 503 | * |
| 504 | * @caps: IOMMU @type specific hardware information data |
| 505 | * |
| 506 | * @size: size of @caps |
| 507 | * |
| 508 | * Returns: bitmap with each bit representing a host IOMMU quirk defined in |
| 509 | * enum host_iommu_quirks |
| 510 | */ |
| 511 | uint64_t (*get_host_iommu_quirks)(uint32_t type, void *caps, uint32_t size); |
| 512 | /** |
| 513 | * @get_iotlb_info: get properties required to initialize a device IOTLB. |
| 514 | * |
| 515 | * Callback required if devices are allowed to cache translations. |
| 516 | * |
| 517 | * @opaque: the data passed to pci_setup_iommu(). |
| 518 | * |
| 519 | * @addr_width: the address width of the IOMMU (output parameter). |
| 520 | * |
| 521 | * @min_page_size: the page size of the IOMMU (output parameter). |
| 522 | */ |
| 523 | void (*get_iotlb_info)(void *opaque, uint8_t *addr_width, |
| 524 | uint32_t *min_page_size); |
| 525 | /** |
| 526 | * @init_iotlb_notifier: initialize an IOMMU notifier. |
| 527 | * |
| 528 | * Optional callback. |
| 529 | * |
| 530 | * @bus: the #PCIBus of the PCI device. |
| 531 | * |
| 532 | * @opaque: the data passed to pci_setup_iommu(). |
| 533 | * |
| 534 | * @devfn: device and function number of the PCI device. |
| 535 | * |
| 536 | * @n: the notifier to be initialized. |
| 537 | * |
| 538 | * @fn: the callback to be installed. |
| 539 | * |
| 540 | * @user_opaque: a user pointer that can be used to track a state. |
| 541 | */ |
| 542 | void (*init_iotlb_notifier)(PCIBus *bus, void *opaque, int devfn, |
| 543 | IOMMUNotifier *n, IOMMUNotify fn, |
| 544 | void *user_opaque); |
| 545 | /** |
| 546 | * @register_iotlb_notifier: setup an IOTLB invalidation notifier. |
| 547 | * |
| 548 | * Callback required if devices are allowed to cache translations. |
| 549 | * |
| 550 | * @bus: the #PCIBus of the PCI device. |
| 551 | * |
| 552 | * @opaque: the data passed to pci_setup_iommu(). |
| 553 | * |
| 554 | * @devfn: device and function number of the PCI device. |
| 555 | * |
| 556 | * @pasid: the pasid of the address space to watch. |
| 557 | * |
| 558 | * @n: the notifier to register. |
| 559 | */ |
| 560 | void (*register_iotlb_notifier)(PCIBus *bus, void *opaque, int devfn, |
| 561 | uint32_t pasid, IOMMUNotifier *n); |
| 562 | /** |
| 563 | * @unregister_iotlb_notifier: remove an IOTLB invalidation notifier. |
| 564 | * |
| 565 | * Callback required if devices are allowed to cache translations. |
| 566 | * |
| 567 | * @bus: the #PCIBus of the PCI device. |
| 568 | * |
| 569 | * @opaque: the data passed to pci_setup_iommu(). |
| 570 | * |
| 571 | * @devfn: device and function number of the PCI device. |
| 572 | * |
| 573 | * @pasid: the pasid of the address space to stop watching. |
| 574 | * |
| 575 | * @n: the notifier to unregister. |
| 576 | */ |
| 577 | void (*unregister_iotlb_notifier)(PCIBus *bus, void *opaque, int devfn, |
| 578 | uint32_t pasid, IOMMUNotifier *n); |
| 579 | /** |
| 580 | * @ats_request_translation: issue an ATS request. |
| 581 | * |
| 582 | * Callback required if devices are allowed to use the address |
| 583 | * translation service. |
| 584 | * |
| 585 | * @bus: the #PCIBus of the PCI device. |
| 586 | * |
| 587 | * @opaque: the data passed to pci_setup_iommu(). |
| 588 | * |
| 589 | * @devfn: device and function number of the PCI device. |
| 590 | * |
| 591 | * @pasid: the pasid of the address space to use for the request. |
| 592 | * |
| 593 | * @priv_req: privileged mode bit (PASID TLP). |
| 594 | * |
| 595 | * @exec_req: execute request bit (PASID TLP). |
| 596 | * |
| 597 | * @addr: start address of the memory range to be translated. |
| 598 | * |
| 599 | * @length: length of the memory range in bytes. |
| 600 | * |
| 601 | * @no_write: request a read-only translation (if supported). |
| 602 | * |
| 603 | * @result: buffer in which the TLB entries will be stored. |
| 604 | * |
| 605 | * @result_length: result buffer length. |
| 606 | * |
| 607 | * @err_count: number of untranslated subregions. |
| 608 | * |
| 609 | * Returns: the number of translations stored in the result buffer, or |
| 610 | * -ENOMEM if the buffer is not large enough. |
| 611 | */ |
| 612 | ssize_t (*ats_request_translation)(PCIBus *bus, void *opaque, int devfn, |
| 613 | uint32_t pasid, bool priv_req, |
| 614 | bool exec_req, hwaddr addr, |
| 615 | size_t length, bool no_write, |
| 616 | IOMMUTLBEntry *result, |
| 617 | size_t result_length, |
| 618 | uint32_t *err_count); |
| 619 | /** |
| 620 | * @pri_register_notifier: setup the PRI completion callback. |
| 621 | * |
| 622 | * Callback required if devices are allowed to use the page request |
| 623 | * interface. |
| 624 | * |
| 625 | * @bus: the #PCIBus of the PCI device. |
| 626 | * |
| 627 | * @opaque: the data passed to pci_setup_iommu(). |
| 628 | * |
| 629 | * @devfn: device and function number of the PCI device. |
| 630 | * |
| 631 | * @pasid: the pasid of the address space to track. |
| 632 | * |
| 633 | * @notifier: the notifier to register. |
| 634 | */ |
| 635 | void (*pri_register_notifier)(PCIBus *bus, void *opaque, int devfn, |
| 636 | uint32_t pasid, IOMMUPRINotifier *notifier); |
| 637 | /** |
| 638 | * @pri_unregister_notifier: remove the PRI completion callback. |
| 639 | * |
| 640 | * Callback required if devices are allowed to use the page request |
| 641 | * interface. |
| 642 | * |
| 643 | * @bus: the #PCIBus of the PCI device. |
| 644 | * |
| 645 | * @opaque: the data passed to pci_setup_iommu(). |
| 646 | * |
| 647 | * @devfn: device and function number of the PCI device. |
| 648 | * |
| 649 | * @pasid: the pasid of the address space to stop tracking. |
| 650 | */ |
| 651 | void (*pri_unregister_notifier)(PCIBus *bus, void *opaque, int devfn, |
| 652 | uint32_t pasid); |
| 653 | /** |
| 654 | * @pri_request_page: issue a PRI request. |
| 655 | * |
| 656 | * Callback required if devices are allowed to use the page request |
| 657 | * interface. |
| 658 | * |
| 659 | * @bus: the #PCIBus of the PCI device. |
| 660 | * |
| 661 | * @opaque: the data passed to pci_setup_iommu(). |
| 662 | * |
| 663 | * @devfn: device and function number of the PCI device. |
| 664 | * |
| 665 | * @pasid: the pasid of the address space to use for the request. |
| 666 | * |
| 667 | * @priv_req: privileged mode bit (PASID TLP). |
| 668 | * |
| 669 | * @exec_req: execute request bit (PASID TLP). |
| 670 | * |
| 671 | * @addr: untranslated address of the requested page. |
| 672 | * |
| 673 | * @lpig: last page in group. |
| 674 | * |
| 675 | * @prgi: page request group index. |
| 676 | * |
| 677 | * @is_read: request read access. |
| 678 | * |
| 679 | * @is_write: request write access. |
| 680 | */ |
| 681 | int (*pri_request_page)(PCIBus *bus, void *opaque, int devfn, |
| 682 | uint32_t pasid, bool priv_req, bool exec_req, |
| 683 | hwaddr addr, bool lpig, uint16_t prgi, bool is_read, |
| 684 | bool is_write); |
| 685 | /** |
| 686 | * @get_msi_direct_gpa: get the guest physical address of MSI doorbell |
| 687 | * for the device on a PCI bus. |
| 688 | * |
| 689 | * Optional callback. If implemented, it must return a valid guest |
| 690 | * physical address for the MSI doorbell |
| 691 | * |
| 692 | * @bus: the #PCIBus being accessed. |
| 693 | * |
| 694 | * @opaque: the data passed to pci_setup_iommu(). |
| 695 | * |
| 696 | * @devfn: device and function number |
| 697 | * |
| 698 | * Returns: the guest physical address of the MSI doorbell. |
| 699 | */ |
| 700 | uint64_t (*get_msi_direct_gpa)(PCIBus *bus, void *opaque, int devfn); |
| 701 | } PCIIOMMUOps; |
| 702 | |
| 703 | bool pci_device_get_iommu_bus_devfn(PCIDevice *dev, PCIBus **piommu_bus, |
| 704 | PCIBus **aliased_bus, int *aliased_devfn); |
| 705 | AddressSpace *pci_device_iommu_address_space(PCIDevice *dev); |
| 706 | bool pci_device_set_iommu_device(PCIDevice *dev, HostIOMMUDevice *hiod, |
| 707 | Error **errp); |
| 708 | void pci_device_unset_iommu_device(PCIDevice *dev); |
| 709 | bool pci_device_iommu_msi_direct_gpa(PCIDevice *dev, hwaddr *out_doorbell); |
| 710 | |
| 711 | /** |
| 712 | * pci_device_get_viommu_flags: get vIOMMU flags. |
| 713 | * |
| 714 | * Returns: bitmap with each bit representing a vIOMMU flag defined in |
| 715 | * enum viommu_flags. Or 0 if vIOMMU doesn't report any. |
| 716 | * |
| 717 | * @dev: PCI device pointer. |
| 718 | */ |
| 719 | uint64_t pci_device_get_viommu_flags(PCIDevice *dev); |
| 720 | |
| 721 | /** |
| 722 | * pci_device_get_host_iommu_quirks: get host IOMMU quirks. |
| 723 | * |
| 724 | * Returns: bitmap with each bit representing a host IOMMU quirk defined in |
| 725 | * enum host_iommu_quirks. Or 0 if vIOMMU doesn't convert any. |
| 726 | * |
| 727 | * @dev: PCI device pointer. |
| 728 | * @type: IOMMU hardware info type |
| 729 | * @caps: IOMMU @type specific hardware information data |
| 730 | * @size: size of @caps |
| 731 | */ |
| 732 | uint64_t pci_device_get_host_iommu_quirks(PCIDevice *dev, uint32_t type, |
| 733 | void *caps, uint32_t size); |
| 734 | |
| 735 | /** |
| 736 | * pci_iommu_get_iotlb_info: get properties required to initialize a |
| 737 | * device IOTLB. |
| 738 | * |
| 739 | * Returns 0 on success, or a negative errno otherwise. |
| 740 | * |
| 741 | * @dev: the device that wants to get the information. |
| 742 | * @addr_width: the address width of the IOMMU (output parameter). |
| 743 | * @min_page_size: the page size of the IOMMU (output parameter). |
| 744 | */ |
| 745 | int pci_iommu_get_iotlb_info(PCIDevice *dev, uint8_t *addr_width, |
| 746 | uint32_t *min_page_size); |
| 747 | |
| 748 | /** |
| 749 | * pci_iommu_init_iotlb_notifier: initialize an IOMMU notifier. |
| 750 | * |
| 751 | * This function is used by devices before registering an IOTLB notifier. |
| 752 | * |
| 753 | * @dev: the device. |
| 754 | * @n: the notifier to be initialized. |
| 755 | * @fn: the callback to be installed. |
| 756 | * @opaque: a user pointer that can be used to track a state. |
| 757 | */ |
| 758 | int pci_iommu_init_iotlb_notifier(PCIDevice *dev, IOMMUNotifier *n, |
| 759 | IOMMUNotify fn, void *opaque); |
| 760 | |
| 761 | /** |
| 762 | * pci_ats_request_translation: perform an ATS request. |
| 763 | * |
| 764 | * Returns the number of translations stored in @result in case of success, |
| 765 | * a negative error code otherwise. |
| 766 | * -ENOMEM is returned when the result buffer is not large enough to store |
| 767 | * all the translations. |
| 768 | * |
| 769 | * @dev: the ATS-capable PCI device. |
| 770 | * @pasid: the pasid of the address space in which the translation will be done. |
| 771 | * @priv_req: privileged mode bit (PASID TLP). |
| 772 | * @exec_req: execute request bit (PASID TLP). |
| 773 | * @addr: start address of the memory range to be translated. |
| 774 | * @length: length of the memory range in bytes. |
| 775 | * @no_write: request a read-only translation (if supported). |
| 776 | * @result: buffer in which the TLB entries will be stored. |
| 777 | * @result_length: result buffer length. |
| 778 | * @err_count: number of untranslated subregions. |
| 779 | */ |
| 780 | ssize_t pci_ats_request_translation(PCIDevice *dev, uint32_t pasid, |
| 781 | bool priv_req, bool exec_req, |
| 782 | hwaddr addr, size_t length, |
| 783 | bool no_write, IOMMUTLBEntry *result, |
| 784 | size_t result_length, |
| 785 | uint32_t *err_count); |
| 786 | |
| 787 | /** |
| 788 | * pci_pri_request_page: perform a PRI request. |
| 789 | * |
| 790 | * Returns 0 if the PRI request has been sent to the guest OS, |
| 791 | * an error code otherwise. |
| 792 | * |
| 793 | * @dev: the PRI-capable PCI device. |
| 794 | * @pasid: the pasid of the address space in which the translation will be done. |
| 795 | * @priv_req: privileged mode bit (PASID TLP). |
| 796 | * @exec_req: execute request bit (PASID TLP). |
| 797 | * @addr: untranslated address of the requested page. |
| 798 | * @lpig: last page in group. |
| 799 | * @prgi: page request group index. |
| 800 | * @is_read: request read access. |
| 801 | * @is_write: request write access. |
| 802 | */ |
| 803 | int pci_pri_request_page(PCIDevice *dev, uint32_t pasid, bool priv_req, |
| 804 | bool exec_req, hwaddr addr, bool lpig, |
| 805 | uint16_t prgi, bool is_read, bool is_write); |
| 806 | |
| 807 | /** |
| 808 | * pci_pri_register_notifier: register the PRI callback for a given address |
| 809 | * space. |
| 810 | * |
| 811 | * Returns 0 on success, an error code otherwise. |
| 812 | * |
| 813 | * @dev: the PRI-capable PCI device. |
| 814 | * @pasid: the pasid of the address space to track. |
| 815 | * @notifier: the notifier to register. |
| 816 | */ |
| 817 | int pci_pri_register_notifier(PCIDevice *dev, uint32_t pasid, |
| 818 | IOMMUPRINotifier *notifier); |
| 819 | |
| 820 | /** |
| 821 | * pci_pri_unregister_notifier: remove the PRI callback from a given address |
| 822 | * space. |
| 823 | * |
| 824 | * @dev: the PRI-capable PCI device. |
| 825 | * @pasid: the pasid of the address space to stop tracking. |
| 826 | */ |
| 827 | void pci_pri_unregister_notifier(PCIDevice *dev, uint32_t pasid); |
| 828 | |
| 829 | /** |
| 830 | * pci_iommu_register_iotlb_notifier: register a notifier for changes to |
| 831 | * IOMMU translation entries in a specific address space. |
| 832 | * |
| 833 | * Returns 0 on success, or a negative errno otherwise. |
| 834 | * |
| 835 | * @dev: the device that wants to get notified. |
| 836 | * @pasid: the pasid of the address space to track. |
| 837 | * @n: the notifier to register. |
| 838 | */ |
| 839 | int pci_iommu_register_iotlb_notifier(PCIDevice *dev, uint32_t pasid, |
| 840 | IOMMUNotifier *n); |
| 841 | |
| 842 | /** |
| 843 | * pci_iommu_unregister_iotlb_notifier: unregister a notifier that has been |
| 844 | * registered with pci_iommu_register_iotlb_notifier. |
| 845 | * |
| 846 | * Returns 0 on success, or a negative errno otherwise. |
| 847 | * |
| 848 | * @dev: the device that wants to stop notifications. |
| 849 | * @pasid: the pasid of the address space to stop tracking. |
| 850 | * @n: the notifier to unregister. |
| 851 | */ |
| 852 | int pci_iommu_unregister_iotlb_notifier(PCIDevice *dev, uint32_t pasid, |
| 853 | IOMMUNotifier *n); |
| 854 | |
| 855 | /** |
| 856 | * pci_setup_iommu: Initialize specific IOMMU handlers for a PCIBus |
| 857 | * |
| 858 | * Let PCI host bridges define specific operations. |
| 859 | * |
| 860 | * @bus: the #PCIBus being updated. |
| 861 | * @ops: the #PCIIOMMUOps |
| 862 | * @opaque: passed to callbacks of the @ops structure. |
| 863 | */ |
| 864 | void pci_setup_iommu(PCIBus *bus, const PCIIOMMUOps *ops, void *opaque); |
| 865 | |
| 866 | /** |
| 867 | * pci_setup_iommu_per_bus: Initialize specific IOMMU handlers for a PCIBus |
| 868 | * |
| 869 | * Similar to pci_setup_iommu but enforces that the iommu only protects |
| 870 | * @bus downstream end points and no other bus hierarchy |
| 871 | * |
| 872 | * @bus: the #PCIBus being updated. |
| 873 | * @ops: the #PCIIOMMUOps |
| 874 | * @opaque: passed to callbacks of the @ops structure. |
| 875 | * @errp: error handle |
| 876 | * |
| 877 | * Returns false on failure with @errp set, true on success |
| 878 | */ |
| 879 | bool pci_setup_iommu_per_bus(PCIBus *bus, const PCIIOMMUOps *ops, |
| 880 | void *opaque, Error **errp); |
| 881 | |
| 882 | pcibus_t pci_bar_address(PCIDevice *d, |
| 883 | int reg, uint8_t type, pcibus_t size); |
| 884 | |
| 885 | static inline void |
| 886 | pci_set_byte(uint8_t *config, uint8_t val) |
| 887 | { |
| 888 | *config = val; |
| 889 | } |
| 890 | |
| 891 | static inline uint8_t |
| 892 | pci_get_byte(const uint8_t *config) |
| 893 | { |
| 894 | return *config; |
| 895 | } |
| 896 | |
| 897 | static inline void |
| 898 | pci_set_word(uint8_t *config, uint16_t val) |
| 899 | { |
| 900 | stw_le_p(config, val); |
| 901 | } |
| 902 | |
| 903 | static inline uint16_t |
| 904 | pci_get_word(const uint8_t *config) |
| 905 | { |
| 906 | return lduw_le_p(config); |
| 907 | } |
| 908 | |
| 909 | static inline void |
| 910 | pci_set_long(uint8_t *config, uint32_t val) |
| 911 | { |
| 912 | stl_le_p(config, val); |
| 913 | } |
| 914 | |
| 915 | static inline uint32_t |
| 916 | pci_get_long(const uint8_t *config) |
| 917 | { |
| 918 | return ldl_le_p(config); |
| 919 | } |
| 920 | |
| 921 | /* |
| 922 | * PCI capabilities and/or their fields |
| 923 | * are generally DWORD aligned only so |
| 924 | * mechanism used by pci_set/get_quad() |
| 925 | * must be tolerant to unaligned pointers |
| 926 | * |
| 927 | */ |
| 928 | static inline void |
| 929 | pci_set_quad(uint8_t *config, uint64_t val) |
| 930 | { |
| 931 | stq_le_p(config, val); |
| 932 | } |
| 933 | |
| 934 | static inline uint64_t |
| 935 | pci_get_quad(const uint8_t *config) |
| 936 | { |
| 937 | return ldq_le_p(config); |
| 938 | } |
| 939 | |
| 940 | static inline void |
| 941 | pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val) |
| 942 | { |
| 943 | pci_set_word(&pci_config[PCI_VENDOR_ID], val); |
| 944 | } |
| 945 | |
| 946 | static inline void |
| 947 | pci_config_set_device_id(uint8_t *pci_config, uint16_t val) |
| 948 | { |
| 949 | pci_set_word(&pci_config[PCI_DEVICE_ID], val); |
| 950 | } |
| 951 | |
| 952 | static inline void |
| 953 | pci_config_set_revision(uint8_t *pci_config, uint8_t val) |
| 954 | { |
| 955 | pci_set_byte(&pci_config[PCI_REVISION_ID], val); |
| 956 | } |
| 957 | |
| 958 | static inline void |
| 959 | pci_config_set_class(uint8_t *pci_config, uint16_t val) |
| 960 | { |
| 961 | pci_set_word(&pci_config[PCI_CLASS_DEVICE], val); |
| 962 | } |
| 963 | |
| 964 | static inline void |
| 965 | pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val) |
| 966 | { |
| 967 | pci_set_byte(&pci_config[PCI_CLASS_PROG], val); |
| 968 | } |
| 969 | |
| 970 | static inline void |
| 971 | pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val) |
| 972 | { |
| 973 | pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val); |
| 974 | } |
| 975 | |
| 976 | /* |
| 977 | * helper functions to do bit mask operation on configuration space. |
| 978 | * Just to set bit, use test-and-set and discard returned value. |
| 979 | * Just to clear bit, use test-and-clear and discard returned value. |
| 980 | * NOTE: They aren't atomic. |
| 981 | */ |
| 982 | static inline uint8_t |
| 983 | pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask) |
| 984 | { |
| 985 | uint8_t val = pci_get_byte(config); |
| 986 | pci_set_byte(config, val & ~mask); |
| 987 | return val & mask; |
| 988 | } |
| 989 | |
| 990 | static inline uint8_t |
| 991 | pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask) |
| 992 | { |
| 993 | uint8_t val = pci_get_byte(config); |
| 994 | pci_set_byte(config, val | mask); |
| 995 | return val & mask; |
| 996 | } |
| 997 | |
| 998 | static inline uint16_t |
| 999 | pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask) |
| 1000 | { |
| 1001 | uint16_t val = pci_get_word(config); |
| 1002 | pci_set_word(config, val & ~mask); |
| 1003 | return val & mask; |
| 1004 | } |
| 1005 | |
| 1006 | static inline uint16_t |
| 1007 | pci_word_test_and_set_mask(uint8_t *config, uint16_t mask) |
| 1008 | { |
| 1009 | uint16_t val = pci_get_word(config); |
| 1010 | pci_set_word(config, val | mask); |
| 1011 | return val & mask; |
| 1012 | } |
| 1013 | |
| 1014 | static inline uint32_t |
| 1015 | pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask) |
| 1016 | { |
| 1017 | uint32_t val = pci_get_long(config); |
| 1018 | pci_set_long(config, val & ~mask); |
| 1019 | return val & mask; |
| 1020 | } |
| 1021 | |
| 1022 | static inline uint32_t |
| 1023 | pci_long_test_and_set_mask(uint8_t *config, uint32_t mask) |
| 1024 | { |
| 1025 | uint32_t val = pci_get_long(config); |
| 1026 | pci_set_long(config, val | mask); |
| 1027 | return val & mask; |
| 1028 | } |
| 1029 | |
| 1030 | static inline uint64_t |
| 1031 | pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask) |
| 1032 | { |
| 1033 | uint64_t val = pci_get_quad(config); |
| 1034 | pci_set_quad(config, val & ~mask); |
| 1035 | return val & mask; |
| 1036 | } |
| 1037 | |
| 1038 | static inline uint64_t |
| 1039 | pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask) |
| 1040 | { |
| 1041 | uint64_t val = pci_get_quad(config); |
| 1042 | pci_set_quad(config, val | mask); |
| 1043 | return val & mask; |
| 1044 | } |
| 1045 | |
| 1046 | /* Access a register specified by a mask */ |
| 1047 | static inline void |
| 1048 | pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg) |
| 1049 | { |
| 1050 | uint8_t val = pci_get_byte(config); |
| 1051 | uint8_t rval; |
| 1052 | |
| 1053 | assert(mask); |
| 1054 | rval = reg << ctz32(mask); |
| 1055 | pci_set_byte(config, (~mask & val) | (mask & rval)); |
| 1056 | } |
| 1057 | |
| 1058 | static inline void |
| 1059 | pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg) |
| 1060 | { |
| 1061 | uint16_t val = pci_get_word(config); |
| 1062 | uint16_t rval; |
| 1063 | |
| 1064 | assert(mask); |
| 1065 | rval = reg << ctz32(mask); |
| 1066 | pci_set_word(config, (~mask & val) | (mask & rval)); |
| 1067 | } |
| 1068 | |
| 1069 | static inline void |
| 1070 | pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg) |
| 1071 | { |
| 1072 | uint32_t val = pci_get_long(config); |
| 1073 | uint32_t rval; |
| 1074 | |
| 1075 | assert(mask); |
| 1076 | rval = reg << ctz32(mask); |
| 1077 | pci_set_long(config, (~mask & val) | (mask & rval)); |
| 1078 | } |
| 1079 | |
| 1080 | static inline void |
| 1081 | pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg) |
| 1082 | { |
| 1083 | uint64_t val = pci_get_quad(config); |
| 1084 | uint64_t rval; |
| 1085 | |
| 1086 | assert(mask); |
| 1087 | rval = reg << ctz32(mask); |
| 1088 | pci_set_quad(config, (~mask & val) | (mask & rval)); |
| 1089 | } |
| 1090 | |
| 1091 | PCIDevice *pci_new_multifunction(int devfn, const char *name); |
| 1092 | PCIDevice *pci_new(int devfn, const char *name); |
| 1093 | bool pci_realize_and_unref(PCIDevice *dev, PCIBus *bus, Error **errp); |
| 1094 | |
| 1095 | PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, |
| 1096 | const char *name); |
| 1097 | PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name); |
| 1098 | |
| 1099 | void lsi53c8xx_handle_legacy_cmdline(DeviceState *lsi_dev); |
| 1100 | |
| 1101 | qemu_irq pci_allocate_irq(PCIDevice *pci_dev); |
| 1102 | void pci_set_irq(PCIDevice *pci_dev, int level); |
| 1103 | int pci_irq_disabled(PCIDevice *d); |
| 1104 | |
| 1105 | static inline void pci_irq_assert(PCIDevice *pci_dev) |
| 1106 | { |
| 1107 | pci_set_irq(pci_dev, 1); |
| 1108 | } |
| 1109 | |
| 1110 | static inline void pci_irq_deassert(PCIDevice *pci_dev) |
| 1111 | { |
| 1112 | pci_set_irq(pci_dev, 0); |
| 1113 | } |
| 1114 | |
| 1115 | MSIMessage pci_get_msi_message(PCIDevice *dev, int vector); |
| 1116 | void pci_set_enabled(PCIDevice *pci_dev, bool state); |
| 1117 | void pci_set_power(PCIDevice *pci_dev, bool state); |
| 1118 | int pci_pm_init(PCIDevice *pci_dev, uint8_t offset, Error **errp); |
| 1119 | |
| 1120 | #endif |