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1 #ifndef QEMU_PCI_BUS_H
2 #define QEMU_PCI_BUS_H
3
4 #include "hw/pci/pci.h"
5
6 /*
7 * PCI Bus datastructures.
8 *
9 * Do not access the following members directly;
10 * use accessor functions in pci.h
11 */
12
13 struct PCIBusClass {
14 /*< private >*/
15 BusClass parent_class;
16 /*< public >*/
17
18 int (*bus_num)(PCIBus *bus);
19 uint16_t (*numa_node)(PCIBus *bus);
20 };
21
22 enum PCIBusFlags {
23 /* This bus is the root of a PCI domain */
24 PCI_BUS_IS_ROOT = 0x0001,
25 /* PCIe extended configuration space is accessible on this bus */
26 PCI_BUS_EXTENDED_CONFIG_SPACE = 0x0002,
27 /* This is a CXL Type BUS */
28 PCI_BUS_CXL = 0x0004,
29 };
30
31 #define PCI_NO_PASID UINT32_MAX
32
33 struct PCIBus {
34 BusState qbus;
35 enum PCIBusFlags flags;
36 const PCIIOMMUOps *iommu_ops;
37 void *iommu_opaque;
38 bool iommu_per_bus;
39 uint8_t devfn_min;
40 uint32_t slot_reserved_mask;
41 pci_set_irq_fn set_irq;
42 pci_map_irq_fn map_irq;
43 pci_route_irq_fn route_intx_to_irq;
44 void *irq_opaque;
45 PCIDevice *devices[PCI_SLOT_MAX * PCI_FUNC_MAX];
46 PCIDevice *parent_dev;
47 MemoryRegion *address_space_mem;
48 MemoryRegion *address_space_io;
49
50 QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */
51 QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */
52
53 /* The bus IRQ state is the logical OR of the connected devices.
54 Keep a count of the number of devices with raised IRQs. */
55 int nirq;
56 int *irq_count;
57
58 Notifier machine_done;
59
60 uint32_t acpi_pcihp_bsel_val;
61 };
62
63 static inline bool pci_bus_is_cxl(PCIBus *bus)
64 {
65 return !!(bus->flags & PCI_BUS_CXL);
66 }
67
68 static inline bool pci_bus_is_root(PCIBus *bus)
69 {
70 return !!(bus->flags & PCI_BUS_IS_ROOT);
71 }
72
73 static inline bool pci_bus_allows_extended_config_space(PCIBus *bus)
74 {
75 return !!(bus->flags & PCI_BUS_EXTENDED_CONFIG_SPACE);
76 }
77
78 #endif /* QEMU_PCI_BUS_H */