| 1 | #ifndef QEMU_PCI_DEVICE_H |
| 2 | #define QEMU_PCI_DEVICE_H |
| 3 | |
| 4 | #include "hw/pci/pci.h" |
| 5 | #include "hw/pci/pcie.h" |
| 6 | #include "hw/pci/pcie_doe.h" |
| 7 | #include "system/spdm-socket.h" |
| 8 | |
| 9 | #define TYPE_PCI_DEVICE "pci-device" |
| 10 | typedef struct PCIDeviceClass PCIDeviceClass; |
| 11 | DECLARE_OBJ_CHECKERS(PCIDevice, PCIDeviceClass, |
| 12 | PCI_DEVICE, TYPE_PCI_DEVICE) |
| 13 | |
| 14 | /* |
| 15 | * Implemented by devices that can be plugged on CXL buses. In the spec, this is |
| 16 | * actually a "CXL Component, but we name it device to match the PCI naming. |
| 17 | */ |
| 18 | #define INTERFACE_CXL_DEVICE "cxl-device" |
| 19 | |
| 20 | /* Implemented by devices that can be plugged on PCI Express buses */ |
| 21 | #define INTERFACE_PCIE_DEVICE "pci-express-device" |
| 22 | |
| 23 | /* Implemented by devices that can be plugged on Conventional PCI buses */ |
| 24 | #define INTERFACE_CONVENTIONAL_PCI_DEVICE "conventional-pci-device" |
| 25 | |
| 26 | struct PCIDeviceClass { |
| 27 | DeviceClass parent_class; |
| 28 | |
| 29 | void (*realize)(PCIDevice *dev, Error **errp); |
| 30 | PCIUnregisterFunc *exit; |
| 31 | PCIConfigReadFunc *config_read; |
| 32 | PCIConfigWriteFunc *config_write; |
| 33 | |
| 34 | uint16_t vendor_id; |
| 35 | uint16_t device_id; |
| 36 | uint8_t revision; |
| 37 | uint16_t class_id; |
| 38 | uint16_t subsystem_vendor_id; /* only for header type = 0 */ |
| 39 | uint16_t subsystem_id; /* only for header type = 0 */ |
| 40 | |
| 41 | const char *romfile; /* rom bar */ |
| 42 | |
| 43 | bool sriov_vf_user_creatable; |
| 44 | }; |
| 45 | |
| 46 | enum PCIReqIDType { |
| 47 | PCI_REQ_ID_INVALID = 0, |
| 48 | PCI_REQ_ID_BDF, |
| 49 | PCI_REQ_ID_SECONDARY_BUS, |
| 50 | PCI_REQ_ID_MAX, |
| 51 | }; |
| 52 | typedef enum PCIReqIDType PCIReqIDType; |
| 53 | |
| 54 | struct PCIReqIDCache { |
| 55 | PCIDevice *dev; |
| 56 | PCIReqIDType type; |
| 57 | }; |
| 58 | typedef struct PCIReqIDCache PCIReqIDCache; |
| 59 | |
| 60 | struct PCIDevice { |
| 61 | DeviceState qdev; |
| 62 | bool partially_hotplugged; |
| 63 | bool enabled; |
| 64 | |
| 65 | /* only for s390x */ |
| 66 | char *loadparm; |
| 67 | |
| 68 | /* PCI config space */ |
| 69 | uint8_t *config; |
| 70 | |
| 71 | /* |
| 72 | * Used to enable config checks on load. Note that writable bits are |
| 73 | * never checked even if set in cmask. |
| 74 | */ |
| 75 | uint8_t *cmask; |
| 76 | |
| 77 | /* Used to implement R/W bytes */ |
| 78 | uint8_t *wmask; |
| 79 | |
| 80 | /* Used to implement RW1C(Write 1 to Clear) bytes */ |
| 81 | uint8_t *w1cmask; |
| 82 | |
| 83 | /* Used to allocate config space for capabilities. */ |
| 84 | uint8_t *used; |
| 85 | |
| 86 | /* the following fields are read only */ |
| 87 | int32_t devfn; |
| 88 | /* |
| 89 | * Cached device to fetch requester ID from, to avoid the PCI tree |
| 90 | * walking every time we invoke PCI request (e.g., MSI). For |
| 91 | * conventional PCI root complex, this field is meaningless. |
| 92 | */ |
| 93 | PCIReqIDCache requester_id_cache; |
| 94 | char name[64]; |
| 95 | PCIIORegion io_regions[PCI_NUM_REGIONS]; |
| 96 | AddressSpace bus_master_as; |
| 97 | bool is_master; |
| 98 | MemoryRegion bus_master_container_region; |
| 99 | MemoryRegion bus_master_enable_region; |
| 100 | |
| 101 | /* do not access the following fields */ |
| 102 | PCIConfigReadFunc *config_read; |
| 103 | PCIConfigWriteFunc *config_write; |
| 104 | |
| 105 | /* Legacy PCI VGA regions */ |
| 106 | MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS]; |
| 107 | bool has_vga; |
| 108 | |
| 109 | /* Current IRQ levels. Used internally by the generic PCI code. */ |
| 110 | uint8_t irq_state; |
| 111 | |
| 112 | /* Capability bits */ |
| 113 | uint32_t cap_present; |
| 114 | |
| 115 | /* Offset of PM capability in config space */ |
| 116 | uint8_t pm_cap; |
| 117 | |
| 118 | /* Offset of MSI-X capability in config space */ |
| 119 | uint8_t msix_cap; |
| 120 | |
| 121 | /* MSI-X entries */ |
| 122 | int msix_entries_nr; |
| 123 | |
| 124 | /* Space to store MSIX table & pending bit array */ |
| 125 | uint8_t *msix_table; |
| 126 | uint8_t *msix_pba; |
| 127 | |
| 128 | /* May be used by INTx or MSI during interrupt notification */ |
| 129 | void *irq_opaque; |
| 130 | |
| 131 | MSITriggerFunc *msi_trigger; |
| 132 | MSIPrepareMessageFunc *msi_prepare_message; |
| 133 | MSIxPrepareMessageFunc *msix_prepare_message; |
| 134 | |
| 135 | /* MemoryRegion container for msix exclusive BAR setup */ |
| 136 | MemoryRegion msix_exclusive_bar; |
| 137 | /* Memory Regions for MSIX table and pending bit entries. */ |
| 138 | MemoryRegion msix_table_mmio; |
| 139 | MemoryRegion msix_pba_mmio; |
| 140 | /* Reference-count for entries actually in use by driver. */ |
| 141 | unsigned *msix_entry_used; |
| 142 | /* MSIX function mask set or MSIX disabled */ |
| 143 | bool msix_function_masked; |
| 144 | /* Version id needed for VMState */ |
| 145 | int32_t version_id; |
| 146 | |
| 147 | /* Offset of MSI capability in config space */ |
| 148 | uint8_t msi_cap; |
| 149 | |
| 150 | /* PCI Express */ |
| 151 | PCIExpressDevice exp; |
| 152 | |
| 153 | /* SHPC */ |
| 154 | SHPCDevice *shpc; |
| 155 | |
| 156 | /* Location of option rom */ |
| 157 | char *romfile; |
| 158 | uint32_t romsize; |
| 159 | bool has_rom; |
| 160 | MemoryRegion rom; |
| 161 | int32_t rom_bar; |
| 162 | |
| 163 | /* INTx routing notifier */ |
| 164 | PCIINTxRoutingNotifier intx_routing_notifier; |
| 165 | |
| 166 | /* MSI-X notifiers */ |
| 167 | MSIVectorUseNotifier msix_vector_use_notifier; |
| 168 | MSIVectorReleaseNotifier msix_vector_release_notifier; |
| 169 | MSIVectorPollNotifier msix_vector_poll_notifier; |
| 170 | |
| 171 | /* SPDM */ |
| 172 | uint16_t spdm_port; |
| 173 | SpdmTransportType spdm_trans; |
| 174 | |
| 175 | /* DOE */ |
| 176 | DOECap doe_spdm; |
| 177 | |
| 178 | /* ID of standby device in net_failover pair */ |
| 179 | char *failover_pair_id; |
| 180 | uint32_t acpi_index; |
| 181 | |
| 182 | /* |
| 183 | * Indirect DMA region bounce buffer size as configured for the device. This |
| 184 | * is a configuration parameter that is reflected into bus_master_as when |
| 185 | * realizing the device. |
| 186 | */ |
| 187 | uint32_t max_bounce_buffer_size; |
| 188 | |
| 189 | char *sriov_pf; |
| 190 | }; |
| 191 | |
| 192 | static inline int pci_intx(PCIDevice *pci_dev) |
| 193 | { |
| 194 | return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1; |
| 195 | } |
| 196 | |
| 197 | static inline int pci_is_cxl(const PCIDevice *d) |
| 198 | { |
| 199 | return d->cap_present & QEMU_PCIE_CAP_CXL; |
| 200 | } |
| 201 | |
| 202 | static inline int pci_is_express(const PCIDevice *d) |
| 203 | { |
| 204 | return d->cap_present & QEMU_PCI_CAP_EXPRESS; |
| 205 | } |
| 206 | |
| 207 | static inline int pci_is_express_downstream_port(const PCIDevice *d) |
| 208 | { |
| 209 | uint8_t type; |
| 210 | |
| 211 | if (!pci_is_express(d) || !d->exp.exp_cap) { |
| 212 | return 0; |
| 213 | } |
| 214 | |
| 215 | type = pcie_cap_get_type(d); |
| 216 | |
| 217 | return type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ROOT_PORT; |
| 218 | } |
| 219 | |
| 220 | static inline int pci_is_vf(const PCIDevice *d) |
| 221 | { |
| 222 | return d->sriov_pf || d->exp.sriov_vf.pf != NULL; |
| 223 | } |
| 224 | |
| 225 | static inline uint32_t pci_config_size(const PCIDevice *d) |
| 226 | { |
| 227 | return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE; |
| 228 | } |
| 229 | |
| 230 | static inline uint16_t pci_get_bdf(PCIDevice *dev) |
| 231 | { |
| 232 | return PCI_BUILD_BDF(pci_bus_num(pci_get_bus(dev)), dev->devfn); |
| 233 | } |
| 234 | |
| 235 | uint16_t pci_requester_id(PCIDevice *dev); |
| 236 | |
| 237 | /* DMA access functions */ |
| 238 | static inline AddressSpace *pci_get_address_space(PCIDevice *dev) |
| 239 | { |
| 240 | return &dev->bus_master_as; |
| 241 | } |
| 242 | |
| 243 | /** |
| 244 | * pci_dma_rw: Read from or write to an address space from PCI device. |
| 245 | * |
| 246 | * Return a MemTxResult indicating whether the operation succeeded |
| 247 | * or failed (eg unassigned memory, device rejected the transaction, |
| 248 | * IOMMU fault). |
| 249 | * |
| 250 | * @dev: #PCIDevice doing the memory access |
| 251 | * @addr: address within the #PCIDevice address space |
| 252 | * @buf: buffer with the data transferred |
| 253 | * @len: the number of bytes to read or write |
| 254 | * @dir: indicates the transfer direction |
| 255 | */ |
| 256 | static inline MemTxResult pci_dma_rw(PCIDevice *dev, dma_addr_t addr, |
| 257 | void *buf, dma_addr_t len, |
| 258 | DMADirection dir, MemTxAttrs attrs) |
| 259 | { |
| 260 | return dma_memory_rw(pci_get_address_space(dev), addr, buf, len, |
| 261 | dir, attrs); |
| 262 | } |
| 263 | |
| 264 | /** |
| 265 | * pci_dma_read: Read from an address space from PCI device. |
| 266 | * |
| 267 | * Return a MemTxResult indicating whether the operation succeeded |
| 268 | * or failed (eg unassigned memory, device rejected the transaction, |
| 269 | * IOMMU fault). Called within RCU critical section. |
| 270 | * |
| 271 | * @dev: #PCIDevice doing the memory access |
| 272 | * @addr: address within the #PCIDevice address space |
| 273 | * @buf: buffer with the data transferred |
| 274 | * @len: length of the data transferred |
| 275 | */ |
| 276 | static inline MemTxResult pci_dma_read(PCIDevice *dev, dma_addr_t addr, |
| 277 | void *buf, dma_addr_t len) |
| 278 | { |
| 279 | return pci_dma_rw(dev, addr, buf, len, |
| 280 | DMA_DIRECTION_TO_DEVICE, MEMTXATTRS_UNSPECIFIED); |
| 281 | } |
| 282 | |
| 283 | /** |
| 284 | * pci_dma_write: Write to address space from PCI device. |
| 285 | * |
| 286 | * Return a MemTxResult indicating whether the operation succeeded |
| 287 | * or failed (eg unassigned memory, device rejected the transaction, |
| 288 | * IOMMU fault). |
| 289 | * |
| 290 | * @dev: #PCIDevice doing the memory access |
| 291 | * @addr: address within the #PCIDevice address space |
| 292 | * @buf: buffer with the data transferred |
| 293 | * @len: the number of bytes to write |
| 294 | */ |
| 295 | static inline MemTxResult pci_dma_write(PCIDevice *dev, dma_addr_t addr, |
| 296 | const void *buf, dma_addr_t len) |
| 297 | { |
| 298 | return pci_dma_rw(dev, addr, (void *) buf, len, |
| 299 | DMA_DIRECTION_FROM_DEVICE, MEMTXATTRS_UNSPECIFIED); |
| 300 | } |
| 301 | |
| 302 | #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \ |
| 303 | static inline MemTxResult ld##_l##_pci_dma(PCIDevice *dev, \ |
| 304 | dma_addr_t addr, \ |
| 305 | uint##_bits##_t *val, \ |
| 306 | MemTxAttrs attrs) \ |
| 307 | { \ |
| 308 | return ld##_l##_dma(pci_get_address_space(dev), addr, val, attrs); \ |
| 309 | } \ |
| 310 | static inline MemTxResult st##_s##_pci_dma(PCIDevice *dev, \ |
| 311 | dma_addr_t addr, \ |
| 312 | uint##_bits##_t val, \ |
| 313 | MemTxAttrs attrs) \ |
| 314 | { \ |
| 315 | return st##_s##_dma(pci_get_address_space(dev), addr, val, attrs); \ |
| 316 | } |
| 317 | |
| 318 | PCI_DMA_DEFINE_LDST(ub, b, 8); |
| 319 | PCI_DMA_DEFINE_LDST(uw_le, w_le, 16) |
| 320 | PCI_DMA_DEFINE_LDST(l_le, l_le, 32); |
| 321 | PCI_DMA_DEFINE_LDST(q_le, q_le, 64); |
| 322 | PCI_DMA_DEFINE_LDST(uw_be, w_be, 16) |
| 323 | PCI_DMA_DEFINE_LDST(l_be, l_be, 32); |
| 324 | PCI_DMA_DEFINE_LDST(q_be, q_be, 64); |
| 325 | |
| 326 | #undef PCI_DMA_DEFINE_LDST |
| 327 | |
| 328 | /** |
| 329 | * pci_dma_map: Map device PCI address space range into host virtual address |
| 330 | * @dev: #PCIDevice to be accessed |
| 331 | * @addr: address within that device's address space |
| 332 | * @plen: pointer to length of buffer; updated on return to indicate |
| 333 | * if only a subset of the requested range has been mapped |
| 334 | * @dir: indicates the transfer direction |
| 335 | * |
| 336 | * Return: A host pointer, or %NULL if the resources needed to |
| 337 | * perform the mapping are exhausted (in that case *@plen |
| 338 | * is set to zero). |
| 339 | */ |
| 340 | static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr, |
| 341 | dma_addr_t *plen, DMADirection dir) |
| 342 | { |
| 343 | return dma_memory_map(pci_get_address_space(dev), addr, plen, dir, |
| 344 | MEMTXATTRS_UNSPECIFIED); |
| 345 | } |
| 346 | |
| 347 | static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len, |
| 348 | DMADirection dir, dma_addr_t access_len) |
| 349 | { |
| 350 | dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len); |
| 351 | } |
| 352 | |
| 353 | static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev, |
| 354 | int alloc_hint) |
| 355 | { |
| 356 | qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev)); |
| 357 | } |
| 358 | |
| 359 | extern const VMStateDescription vmstate_pci_device; |
| 360 | |
| 361 | #define VMSTATE_PCI_DEVICE(_field, _state) { \ |
| 362 | .name = (stringify(_field)), \ |
| 363 | .size = sizeof(PCIDevice), \ |
| 364 | .vmsd = &vmstate_pci_device, \ |
| 365 | .flags = VMS_STRUCT, \ |
| 366 | .offset = vmstate_offset_value(_state, _field, PCIDevice), \ |
| 367 | } |
| 368 | |
| 369 | #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \ |
| 370 | .name = (stringify(_field)), \ |
| 371 | .size = sizeof(PCIDevice), \ |
| 372 | .vmsd = &vmstate_pci_device, \ |
| 373 | .flags = VMS_STRUCT | VMS_POINTER, \ |
| 374 | .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \ |
| 375 | } |
| 376 | |
| 377 | #endif |