| 1 | /* |
| 2 | * QEMU Common PCI Host bridge configuration data space access routines. |
| 3 | * |
| 4 | * Copyright (c) 2006 Fabrice Bellard |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to deal |
| 8 | * in the Software without restriction, including without limitation the rights |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 10 | * copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. |
| 23 | */ |
| 24 | |
| 25 | /* Worker routines for a PCI host controller that uses an {address,data} |
| 26 | register pair to access PCI configuration space. */ |
| 27 | |
| 28 | #ifndef PCI_HOST_H |
| 29 | #define PCI_HOST_H |
| 30 | |
| 31 | #include "hw/core/sysbus.h" |
| 32 | #include "qom/object.h" |
| 33 | |
| 34 | #define PCI_HOST_BYPASS_IOMMU "bypass-iommu" |
| 35 | |
| 36 | #define TYPE_PCI_HOST_BRIDGE "pci-host-bridge" |
| 37 | OBJECT_DECLARE_TYPE(PCIHostState, PCIHostBridgeClass, PCI_HOST_BRIDGE) |
| 38 | |
| 39 | struct PCIHostState { |
| 40 | SysBusDevice busdev; |
| 41 | |
| 42 | MemoryRegion conf_mem; |
| 43 | MemoryRegion data_mem; |
| 44 | MemoryRegion mmcfg; |
| 45 | uint32_t config_reg; |
| 46 | bool mig_enabled; |
| 47 | PCIBus *bus; |
| 48 | bool bypass_iommu; |
| 49 | |
| 50 | QLIST_ENTRY(PCIHostState) next; |
| 51 | }; |
| 52 | |
| 53 | struct PCIHostBridgeClass { |
| 54 | SysBusDeviceClass parent_class; |
| 55 | |
| 56 | const char *(*root_bus_path)(PCIHostState *, PCIBus *); |
| 57 | }; |
| 58 | |
| 59 | /* common internal helpers for PCI/PCIe hosts, cut off overflows */ |
| 60 | void pci_host_config_write_common(PCIDevice *pci_dev, uint32_t addr, |
| 61 | uint32_t limit, uint32_t val, uint32_t len); |
| 62 | uint32_t pci_host_config_read_common(PCIDevice *pci_dev, uint32_t addr, |
| 63 | uint32_t limit, uint32_t len); |
| 64 | |
| 65 | void pci_data_write(PCIBus *s, uint32_t addr, uint32_t val, unsigned len); |
| 66 | uint32_t pci_data_read(PCIBus *s, uint32_t addr, unsigned len); |
| 67 | |
| 68 | extern const MemoryRegionOps pci_host_conf_le_ops; |
| 69 | extern const MemoryRegionOps pci_host_conf_be_ops; |
| 70 | extern const MemoryRegionOps pci_host_data_le_ops; |
| 71 | |
| 72 | #endif /* PCI_HOST_H */ |