| 1 | /* |
| 2 | * pcie.h |
| 3 | * |
| 4 | * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp> |
| 5 | * VA Linux Systems Japan K.K. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License along |
| 18 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
| 19 | */ |
| 20 | |
| 21 | #ifndef QEMU_PCIE_H |
| 22 | #define QEMU_PCIE_H |
| 23 | |
| 24 | #include "hw/pci/pci_regs.h" |
| 25 | #include "hw/pci/pcie_regs.h" |
| 26 | #include "hw/pci/pcie_aer.h" |
| 27 | #include "hw/pci/pcie_sriov.h" |
| 28 | #include "hw/core/hotplug.h" |
| 29 | |
| 30 | typedef struct PCIEPort PCIEPort; |
| 31 | typedef struct PCIESlot PCIESlot; |
| 32 | |
| 33 | typedef enum { |
| 34 | /* these bits must match the bits in Slot Control/Status registers. |
| 35 | * PCI_EXP_HP_EV_xxx = PCI_EXP_SLTCTL_xxxE = PCI_EXP_SLTSTA_xxx |
| 36 | * |
| 37 | * Not all the bits of slot control register match with the ones of |
| 38 | * slot status. Not some bits of slot status register is used to |
| 39 | * show status, not to report event occurrence. |
| 40 | * So such bits must be masked out when checking the software |
| 41 | * notification condition. |
| 42 | */ |
| 43 | PCI_EXP_HP_EV_ABP = PCI_EXP_SLTCTL_ABPE, |
| 44 | /* attention button pressed */ |
| 45 | PCI_EXP_HP_EV_PDC = PCI_EXP_SLTCTL_PDCE, |
| 46 | /* presence detect changed */ |
| 47 | PCI_EXP_HP_EV_CCI = PCI_EXP_SLTCTL_CCIE, |
| 48 | /* command completed */ |
| 49 | |
| 50 | PCI_EXP_HP_EV_SUPPORTED = PCI_EXP_HP_EV_ABP | |
| 51 | PCI_EXP_HP_EV_PDC | |
| 52 | PCI_EXP_HP_EV_CCI, |
| 53 | /* supported event mask */ |
| 54 | |
| 55 | /* events not listed aren't supported */ |
| 56 | } PCIExpressHotPlugEvent; |
| 57 | |
| 58 | struct PCIExpressDevice { |
| 59 | /* Offset of express capability in config space */ |
| 60 | uint8_t exp_cap; |
| 61 | |
| 62 | /* SLOT */ |
| 63 | bool hpev_notified; /* Logical AND of conditions for hot plug event. |
| 64 | Following 6.7.3.4: |
| 65 | Software Notification of Hot-Plug Events, an interrupt |
| 66 | is sent whenever the logical and of these conditions |
| 67 | transitions from false to true. */ |
| 68 | |
| 69 | /* AER */ |
| 70 | uint16_t aer_cap; |
| 71 | PCIEAERLog aer_log; |
| 72 | |
| 73 | /* Offset of ATS, PRI and PASID capabilities in config space */ |
| 74 | uint16_t ats_cap; |
| 75 | uint16_t pasid_cap; |
| 76 | uint16_t pri_cap; |
| 77 | |
| 78 | /* ACS */ |
| 79 | uint16_t acs_cap; |
| 80 | |
| 81 | /* SR/IOV */ |
| 82 | uint16_t sriov_cap; |
| 83 | PCIESriovPF sriov_pf; |
| 84 | PCIESriovVF sriov_vf; |
| 85 | }; |
| 86 | |
| 87 | #define COMPAT_PROP_PCP "power_controller_present" |
| 88 | |
| 89 | /* PCI express capability helper functions */ |
| 90 | int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, |
| 91 | uint8_t port, Error **errp); |
| 92 | int pcie_cap_v1_init(PCIDevice *dev, uint8_t offset, |
| 93 | uint8_t type, uint8_t port); |
| 94 | int pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset); |
| 95 | void pcie_cap_exit(PCIDevice *dev); |
| 96 | int pcie_endpoint_cap_v1_init(PCIDevice *dev, uint8_t offset); |
| 97 | void pcie_cap_v1_exit(PCIDevice *dev); |
| 98 | uint8_t pcie_cap_get_type(const PCIDevice *dev); |
| 99 | uint8_t pcie_cap_get_version(const PCIDevice *dev); |
| 100 | void pcie_cap_flags_set_vector(PCIDevice *dev, uint8_t vector); |
| 101 | uint8_t pcie_cap_flags_get_vector(PCIDevice *dev); |
| 102 | |
| 103 | void pcie_cap_deverr_init(PCIDevice *dev); |
| 104 | void pcie_cap_deverr_reset(PCIDevice *dev); |
| 105 | |
| 106 | void pcie_cap_lnkctl_init(PCIDevice *dev); |
| 107 | void pcie_cap_lnkctl_reset(PCIDevice *dev); |
| 108 | |
| 109 | void pcie_cap_slot_init(PCIDevice *dev, PCIESlot *s); |
| 110 | void pcie_cap_slot_reset(PCIDevice *dev); |
| 111 | void pcie_cap_slot_get(PCIDevice *dev, uint16_t *slt_ctl, uint16_t *slt_sta); |
| 112 | void pcie_cap_slot_write_config(PCIDevice *dev, |
| 113 | uint16_t old_slt_ctl, uint16_t old_slt_sta, |
| 114 | uint32_t addr, uint32_t val, int len); |
| 115 | int pcie_cap_slot_post_load(void *opaque, int version_id); |
| 116 | void pcie_cap_slot_push_attention_button(PCIDevice *dev); |
| 117 | void pcie_cap_slot_enable_power(PCIDevice *dev); |
| 118 | |
| 119 | void pcie_cap_root_init(PCIDevice *dev); |
| 120 | void pcie_cap_root_reset(PCIDevice *dev); |
| 121 | |
| 122 | void pcie_cap_flr_init(PCIDevice *dev); |
| 123 | void pcie_cap_flr_write_config(PCIDevice *dev, |
| 124 | uint32_t addr, uint32_t val, int len); |
| 125 | |
| 126 | /* ARI forwarding capability and control */ |
| 127 | void pcie_cap_arifwd_init(PCIDevice *dev); |
| 128 | void pcie_cap_arifwd_reset(PCIDevice *dev); |
| 129 | bool pcie_cap_is_arifwd_enabled(const PCIDevice *dev); |
| 130 | |
| 131 | /* PCI express extended capability helper functions */ |
| 132 | uint16_t pcie_find_capability(PCIDevice *dev, uint16_t cap_id); |
| 133 | void pcie_add_capability(PCIDevice *dev, |
| 134 | uint16_t cap_id, uint8_t cap_ver, |
| 135 | uint16_t offset, uint16_t size); |
| 136 | bool pcie_insert_capability(PCIDevice *dev, uint16_t cap_id, uint8_t cap_ver, |
| 137 | uint16_t offset, uint16_t size); |
| 138 | void pcie_sync_bridge_lnk(PCIDevice *dev); |
| 139 | |
| 140 | void pcie_acs_init(PCIDevice *dev, uint16_t offset); |
| 141 | void pcie_acs_reset(PCIDevice *dev); |
| 142 | |
| 143 | void pcie_ari_init(PCIDevice *dev, uint16_t offset); |
| 144 | void pcie_dev_ser_num_init(PCIDevice *dev, uint16_t offset, uint64_t ser_num); |
| 145 | void pcie_ats_init(PCIDevice *dev, uint16_t offset, bool aligned); |
| 146 | void pcie_cap_fill_link_ep_usp(PCIDevice *dev, PCIExpLinkWidth width, |
| 147 | PCIExpLinkSpeed speed, bool flitmode); |
| 148 | |
| 149 | void pcie_cap_slot_pre_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, |
| 150 | Error **errp); |
| 151 | void pcie_cap_slot_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, |
| 152 | Error **errp); |
| 153 | void pcie_cap_slot_unplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, |
| 154 | Error **errp); |
| 155 | void pcie_cap_slot_unplug_request_cb(HotplugHandler *hotplug_dev, |
| 156 | DeviceState *dev, Error **errp); |
| 157 | |
| 158 | void pcie_pasid_common_init(PCIDevice *dev, uint16_t offset, |
| 159 | uint8_t pasid_width, bool exec_perm, bool priv_mod); |
| 160 | void pcie_pasid_init(PCIDevice *dev, uint16_t offset, uint8_t pasid_width, |
| 161 | bool exec_perm, bool priv_mod); |
| 162 | void pcie_pri_init(PCIDevice *dev, uint16_t offset, uint32_t outstanding_pr_cap, |
| 163 | bool prg_response_pasid_req); |
| 164 | |
| 165 | uint32_t pcie_pri_get_req_alloc(const PCIDevice *dev); |
| 166 | bool pcie_pri_enabled(const PCIDevice *dev); |
| 167 | bool pcie_pasid_enabled(const PCIDevice *dev); |
| 168 | bool pcie_pasid_priv_enabled(PCIDevice *dev); |
| 169 | bool pcie_ats_enabled(const PCIDevice *dev); |
| 170 | #endif /* QEMU_PCIE_H */ |