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1 /*
2 * constants for pcie configurations space from pci express spec.
3 *
4 * TODO:
5 * Those constants and macros should go to Linux pci_regs.h
6 * Once they're merged, they will go away.
7 */
8 #ifndef QEMU_PCIE_REGS_H
9 #define QEMU_PCIE_REGS_H
10
11
12 /* express capability */
13
14 #define PCI_EXP_VER1_SIZEOF 0x14 /* express capability of ver. 1 */
15 #define PCI_EXP_VER2_SIZEOF 0x3c /* express capability of ver. 2 */
16 #define PCI_EXT_CAP_VER_SHIFT 16
17 #define PCI_EXT_CAP_NEXT_SHIFT 20
18 #define PCI_EXT_CAP_NEXT_MASK (0xffc << PCI_EXT_CAP_NEXT_SHIFT)
19
20 #define PCI_EXT_CAP(id, ver, next) \
21 ((id) | \
22 ((ver) << PCI_EXT_CAP_VER_SHIFT) | \
23 ((next) << PCI_EXT_CAP_NEXT_SHIFT))
24
25 #define PCI_EXT_CAP_ALIGN 4
26 #define PCI_EXT_CAP_ALIGNUP(x) \
27 (((x) + PCI_EXT_CAP_ALIGN - 1) & ~(PCI_EXT_CAP_ALIGN - 1))
28
29 /* PCI_EXP_FLAGS */
30 #define PCI_EXP_FLAGS_VER1 1
31 #define PCI_EXP_FLAGS_VER2 2
32 #define PCI_EXP_FLAGS_IRQ_SHIFT ctz32(PCI_EXP_FLAGS_IRQ)
33 #define PCI_EXP_FLAGS_TYPE_SHIFT ctz32(PCI_EXP_FLAGS_TYPE)
34
35 /* PCI_EXP_LINK{CAP, STA} */
36 /* link speed */
37 typedef enum PCIExpLinkSpeed {
38 QEMU_PCI_EXP_LNK_2_5GT = 1,
39 QEMU_PCI_EXP_LNK_5GT,
40 QEMU_PCI_EXP_LNK_8GT,
41 QEMU_PCI_EXP_LNK_16GT,
42 QEMU_PCI_EXP_LNK_32GT,
43 QEMU_PCI_EXP_LNK_64GT,
44 } PCIExpLinkSpeed;
45
46 #define QEMU_PCI_EXP_LNKCAP_MLS(speed) (speed)
47 #define QEMU_PCI_EXP_LNKSTA_CLS QEMU_PCI_EXP_LNKCAP_MLS
48
49 typedef enum PCIExpLinkWidth {
50 QEMU_PCI_EXP_LNK_X1 = 1,
51 QEMU_PCI_EXP_LNK_X2 = 2,
52 QEMU_PCI_EXP_LNK_X4 = 4,
53 QEMU_PCI_EXP_LNK_X8 = 8,
54 QEMU_PCI_EXP_LNK_X12 = 12,
55 QEMU_PCI_EXP_LNK_X16 = 16,
56 QEMU_PCI_EXP_LNK_X32 = 32,
57 } PCIExpLinkWidth;
58
59 #define PCI_EXP_LNK_MLW_SHIFT ctz32(PCI_EXP_LNKCAP_MLW)
60 #define QEMU_PCI_EXP_LNKCAP_MLW(width) (width << PCI_EXP_LNK_MLW_SHIFT)
61 #define QEMU_PCI_EXP_LNKSTA_NLW QEMU_PCI_EXP_LNKCAP_MLW
62
63 /* PCI_EXP_LINKCAP */
64 #define PCI_EXP_LNKCAP_ASPMS_SHIFT ctz32(PCI_EXP_LNKCAP_ASPMS)
65 #define PCI_EXP_LNKCAP_ASPMS_0S (1 << PCI_EXP_LNKCAP_ASPMS_SHIFT)
66
67 #define PCI_EXP_LNKCAP_PN_SHIFT ctz32(PCI_EXP_LNKCAP_PN)
68
69 #define PCI_EXP_SLTCAP_PSN_SHIFT ctz32(PCI_EXP_SLTCAP_PSN)
70
71 #define PCI_EXP_SLTCTL_SUPPORTED \
72 (PCI_EXP_SLTCTL_ABPE | \
73 PCI_EXP_SLTCTL_PDCE | \
74 PCI_EXP_SLTCTL_CCIE | \
75 PCI_EXP_SLTCTL_HPIE | \
76 PCI_EXP_SLTCTL_AIC | \
77 PCI_EXP_SLTCTL_PCC | \
78 PCI_EXP_SLTCTL_EIC)
79
80 #define PCI_EXP_DEVCAP2_EFF 0x100000
81 #define PCI_EXP_DEVCAP2_EETLPP 0x200000
82
83 #define PCI_EXP_DEVCTL2_EETLPPB 0x8000
84
85 /* ARI */
86 #define PCI_ARI_VER 1
87 #define PCI_ARI_SIZEOF 8
88
89 /* PASID */
90 #define PCI_PASID_VER 1
91 #define PCI_EXT_CAP_PASID_MAX_WIDTH 20
92 #define PCI_PASID_CAP_WIDTH_SHIFT 8
93
94 /* PRI */
95 #define PCI_PRI_VER 1
96
97 /* AER */
98 #define PCI_ERR_VER 2
99 #define PCI_ERR_SIZEOF 0x48
100
101 #define PCI_ERR_UNC_SDN 0x00000020 /* surprise down */
102 #define PCI_ERR_UNC_ACSV 0x00200000 /* ACS Violation */
103 #define PCI_ERR_UNC_INTN 0x00400000 /* Internal Error */
104 #define PCI_ERR_UNC_MCBTLP 0x00800000 /* MC Blcoked TLP */
105 #define PCI_ERR_UNC_ATOP_EBLOCKED 0x01000000 /* atomic op egress blocked */
106 #define PCI_ERR_UNC_TLP_PRF_BLOCKED 0x02000000 /* TLP Prefix Blocked */
107 #define PCI_ERR_COR_ADV_NONFATAL 0x00002000 /* Advisory Non-Fatal */
108 #define PCI_ERR_COR_INTERNAL 0x00004000 /* Corrected Internal */
109 #define PCI_ERR_COR_HL_OVERFLOW 0x00008000 /* Header Long Overflow */
110 #define PCI_ERR_CAP_FEP_MASK 0x0000001f
111 #define PCI_ERR_CAP_MHRC 0x00000200
112 #define PCI_ERR_CAP_MHRE 0x00000400
113 #define PCI_ERR_CAP_TLP 0x00000800
114
115 #define PCI_ERR_HEADER_LOG_SIZE 16
116 #define PCI_ERR_TLP_PREFIX_LOG 0x38
117 #define PCI_ERR_TLP_PREFIX_LOG_SIZE 16
118
119 #define PCI_SEC_STATUS_RCV_SYSTEM_ERROR 0x4000
120
121 /* aer root error command/status */
122 #define PCI_ERR_ROOT_CMD_EN_MASK (PCI_ERR_ROOT_CMD_COR_EN | \
123 PCI_ERR_ROOT_CMD_NONFATAL_EN | \
124 PCI_ERR_ROOT_CMD_FATAL_EN)
125
126 #define PCI_ERR_ROOT_IRQ_MAX 32
127 #define PCI_ERR_ROOT_IRQ 0xf8000000
128 #define PCI_ERR_ROOT_IRQ_SHIFT ctz32(PCI_ERR_ROOT_IRQ)
129 #define PCI_ERR_ROOT_STATUS_REPORT_MASK (PCI_ERR_ROOT_COR_RCV | \
130 PCI_ERR_ROOT_MULTI_COR_RCV | \
131 PCI_ERR_ROOT_UNCOR_RCV | \
132 PCI_ERR_ROOT_MULTI_UNCOR_RCV | \
133 PCI_ERR_ROOT_FIRST_FATAL | \
134 PCI_ERR_ROOT_NONFATAL_RCV | \
135 PCI_ERR_ROOT_FATAL_RCV)
136
137 #define PCI_ERR_UNC_SUPPORTED (PCI_ERR_UNC_DLP | \
138 PCI_ERR_UNC_SDN | \
139 PCI_ERR_UNC_POISON_TLP | \
140 PCI_ERR_UNC_FCP | \
141 PCI_ERR_UNC_COMP_TIME | \
142 PCI_ERR_UNC_COMP_ABORT | \
143 PCI_ERR_UNC_UNX_COMP | \
144 PCI_ERR_UNC_RX_OVER | \
145 PCI_ERR_UNC_MALF_TLP | \
146 PCI_ERR_UNC_ECRC | \
147 PCI_ERR_UNC_UNSUP | \
148 PCI_ERR_UNC_ACSV | \
149 PCI_ERR_UNC_INTN | \
150 PCI_ERR_UNC_MCBTLP | \
151 PCI_ERR_UNC_ATOP_EBLOCKED | \
152 PCI_ERR_UNC_TLP_PRF_BLOCKED)
153
154 #define PCI_ERR_UNC_MASK_DEFAULT (PCI_ERR_UNC_INTN | \
155 PCI_ERR_UNC_TLP_PRF_BLOCKED)
156
157 #define PCI_ERR_UNC_SEVERITY_DEFAULT (PCI_ERR_UNC_DLP | \
158 PCI_ERR_UNC_SDN | \
159 PCI_ERR_UNC_FCP | \
160 PCI_ERR_UNC_RX_OVER | \
161 PCI_ERR_UNC_MALF_TLP | \
162 PCI_ERR_UNC_INTN)
163
164 #define PCI_ERR_COR_SUPPORTED (PCI_ERR_COR_RCVR | \
165 PCI_ERR_COR_BAD_TLP | \
166 PCI_ERR_COR_BAD_DLLP | \
167 PCI_ERR_COR_REP_ROLL | \
168 PCI_ERR_COR_REP_TIMER | \
169 PCI_ERR_COR_ADV_NONFATAL | \
170 PCI_ERR_COR_INTERNAL | \
171 PCI_ERR_COR_HL_OVERFLOW)
172
173 #define PCI_ERR_COR_MASK_DEFAULT (PCI_ERR_COR_ADV_NONFATAL | \
174 PCI_ERR_COR_INTERNAL | \
175 PCI_ERR_COR_HL_OVERFLOW)
176
177 /* ACS */
178 #define PCI_ACS_VER 0x1
179 #define PCI_ACS_SIZEOF 8
180
181 /* DOE Capability Register Fields */
182 #define PCI_DOE_VER 0x1
183 #define PCI_DOE_SIZEOF 24
184
185 #endif /* QEMU_PCIE_REGS_H */