| 1 | /* |
| 2 | * QEMU PowerPC PowerNV various definitions |
| 3 | * |
| 4 | * Copyright (c) 2014-2016 BenH, IBM Corporation. |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2.1 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #ifndef PPC_PNV_H |
| 21 | #define PPC_PNV_H |
| 22 | |
| 23 | #include "target/ppc/cpu.h" |
| 24 | #include "hw/core/boards.h" |
| 25 | #include "hw/core/sysbus.h" |
| 26 | #include "hw/ipmi/ipmi.h" |
| 27 | #include "hw/ppc/pnv_pnor.h" |
| 28 | #include "hw/ppc/pnv_mpipl.h" |
| 29 | |
| 30 | #define TYPE_PNV_CHIP "pnv-chip" |
| 31 | |
| 32 | typedef struct PnvCore PnvCore; |
| 33 | typedef struct PnvChip PnvChip; |
| 34 | typedef struct Pnv8Chip Pnv8Chip; |
| 35 | typedef struct Pnv9Chip Pnv9Chip; |
| 36 | typedef struct Pnv10Chip Pnv10Chip; |
| 37 | typedef struct Pnv10Chip Pnv11Chip; |
| 38 | |
| 39 | #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP |
| 40 | #define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX |
| 41 | |
| 42 | #define TYPE_PNV_CHIP_POWER8 PNV_CHIP_TYPE_NAME("power8_v2.0") |
| 43 | DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8, |
| 44 | TYPE_PNV_CHIP_POWER8) |
| 45 | |
| 46 | #define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.2") |
| 47 | DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER9, |
| 48 | TYPE_PNV_CHIP_POWER9) |
| 49 | |
| 50 | #define TYPE_PNV_CHIP_POWER10 PNV_CHIP_TYPE_NAME("power10_v2.0") |
| 51 | DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10, |
| 52 | TYPE_PNV_CHIP_POWER10) |
| 53 | |
| 54 | #define TYPE_PNV_CHIP_POWER11 PNV_CHIP_TYPE_NAME("power11_v2.0") |
| 55 | DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER11, |
| 56 | TYPE_PNV_CHIP_POWER11) |
| 57 | |
| 58 | PnvCore *pnv_chip_find_core(PnvChip *chip, uint32_t core_id); |
| 59 | PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir); |
| 60 | |
| 61 | typedef struct PnvPHB PnvPHB; |
| 62 | |
| 63 | #define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv") |
| 64 | typedef struct PnvMachineClass PnvMachineClass; |
| 65 | typedef struct PnvMachineState PnvMachineState; |
| 66 | DECLARE_OBJ_CHECKERS(PnvMachineState, PnvMachineClass, |
| 67 | PNV_MACHINE, TYPE_PNV_MACHINE) |
| 68 | |
| 69 | |
| 70 | struct PnvMachineClass { |
| 71 | /*< private >*/ |
| 72 | MachineClass parent_class; |
| 73 | |
| 74 | /*< public >*/ |
| 75 | const char *compat; |
| 76 | int compat_size; |
| 77 | int max_smt_threads; |
| 78 | bool has_lpar_per_thread; |
| 79 | bool quirk_tb_big_core; |
| 80 | |
| 81 | void (*dt_power_mgt)(PnvMachineState *pnv, void *fdt); |
| 82 | void (*i2c_init)(PnvMachineState *pnv); |
| 83 | }; |
| 84 | |
| 85 | struct PnvMachineState { |
| 86 | /*< private >*/ |
| 87 | MachineState parent_obj; |
| 88 | |
| 89 | uint32_t initrd_base; |
| 90 | long initrd_size; |
| 91 | |
| 92 | uint32_t num_chips; |
| 93 | PnvChip **chips; |
| 94 | |
| 95 | ISABus *isa_bus; |
| 96 | uint32_t cpld_irqstate; |
| 97 | |
| 98 | IPMIBmc *bmc; |
| 99 | Notifier powerdown_notifier; |
| 100 | |
| 101 | PnvPnor *pnor; |
| 102 | |
| 103 | hwaddr fw_load_addr; |
| 104 | |
| 105 | bool big_core; |
| 106 | bool lpar_per_core; |
| 107 | |
| 108 | Notifier machine_init_done; |
| 109 | MpiplPreservedState mpipl_state; |
| 110 | }; |
| 111 | |
| 112 | PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id); |
| 113 | PnvChip *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb); |
| 114 | |
| 115 | #define PNV_FDT_ADDR 0x01000000 |
| 116 | #define PNV_TIMEBASE_FREQ 512000000ULL |
| 117 | |
| 118 | void pnv_cpu_do_nmi_resume(CPUState *cs); |
| 119 | |
| 120 | /* |
| 121 | * BMC helpers |
| 122 | */ |
| 123 | void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt); |
| 124 | void pnv_bmc_powerdown(IPMIBmc *bmc); |
| 125 | IPMIBmc *pnv_bmc_create(PnvPnor *pnor); |
| 126 | IPMIBmc *pnv_bmc_find(Error **errp); |
| 127 | void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor); |
| 128 | |
| 129 | /* |
| 130 | * POWER8 MMIO base addresses |
| 131 | */ |
| 132 | #define PNV_XSCOM_SIZE 0x800000000ull |
| 133 | #define PNV_XSCOM_BASE(chip) \ |
| 134 | (0x0003fc0000000000ull + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE) |
| 135 | |
| 136 | #define PNV_OCC_COMMON_AREA_SIZE 0x0000000000800000ull |
| 137 | #define PNV_OCC_COMMON_AREA_BASE 0x7fff800000ull |
| 138 | #define PNV_OCC_SENSOR_BASE(chip) (PNV_OCC_COMMON_AREA_BASE + \ |
| 139 | PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id)) |
| 140 | |
| 141 | #define PNV_HOMER_SIZE 0x0000000000400000ull |
| 142 | #define PNV_HOMER_BASE(chip) \ |
| 143 | (0x7ffd800000ull + ((uint64_t)(chip)->chip_id) * PNV_HOMER_SIZE) |
| 144 | |
| 145 | |
| 146 | /* |
| 147 | * XSCOM 0x20109CA defines the ICP BAR: |
| 148 | * |
| 149 | * 0:29 : bits 14 to 43 of address to define 1 MB region. |
| 150 | * 30 : 1 to enable ICP to receive loads/stores against its BAR region |
| 151 | * 31:63 : Constant 0 |
| 152 | * |
| 153 | * Usually defined as : |
| 154 | * |
| 155 | * 0xffffe00200000000 -> 0x0003ffff80000000 |
| 156 | * 0xffffe00600000000 -> 0x0003ffff80100000 |
| 157 | * 0xffffe02200000000 -> 0x0003ffff80800000 |
| 158 | * 0xffffe02600000000 -> 0x0003ffff80900000 |
| 159 | */ |
| 160 | #define PNV_ICP_SIZE 0x0000000000100000ull |
| 161 | #define PNV_ICP_BASE(chip) \ |
| 162 | (0x0003ffff80000000ull + (uint64_t) (chip)->chip_id * PNV_ICP_SIZE) |
| 163 | |
| 164 | |
| 165 | #define PNV_PSIHB_SIZE 0x0000000000100000ull |
| 166 | #define PNV_PSIHB_BASE(chip) \ |
| 167 | (0x0003fffe80000000ull + (uint64_t)(chip)->chip_id * PNV_PSIHB_SIZE) |
| 168 | |
| 169 | #define PNV_PSIHB_FSP_SIZE 0x0000000100000000ull |
| 170 | #define PNV_PSIHB_FSP_BASE(chip) \ |
| 171 | (0x0003ffe000000000ull + (uint64_t)(chip)->chip_id * \ |
| 172 | PNV_PSIHB_FSP_SIZE) |
| 173 | |
| 174 | /* |
| 175 | * POWER9 MMIO base addresses |
| 176 | */ |
| 177 | #define PNV9_CHIP_BASE(chip, base) \ |
| 178 | ((base) + ((uint64_t) (chip)->chip_id << 42)) |
| 179 | |
| 180 | #define PNV9_XIVE_VC_SIZE 0x0000008000000000ull |
| 181 | #define PNV9_XIVE_VC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006010000000000ull) |
| 182 | |
| 183 | #define PNV9_XIVE_PC_SIZE 0x0000001000000000ull |
| 184 | #define PNV9_XIVE_PC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006018000000000ull) |
| 185 | |
| 186 | #define PNV9_LPCM_SIZE 0x0000000100000000ull |
| 187 | #define PNV9_LPCM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030000000000ull) |
| 188 | |
| 189 | #define PNV9_PSIHB_SIZE 0x0000000000100000ull |
| 190 | #define PNV9_PSIHB_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203000000ull) |
| 191 | |
| 192 | #define PNV9_XIVE_IC_SIZE 0x0000000000080000ull |
| 193 | #define PNV9_XIVE_IC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203100000ull) |
| 194 | |
| 195 | #define PNV9_XIVE_TM_SIZE 0x0000000000040000ull |
| 196 | #define PNV9_XIVE_TM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203180000ull) |
| 197 | |
| 198 | #define PNV9_PSIHB_ESB_SIZE 0x0000000000010000ull |
| 199 | #define PNV9_PSIHB_ESB_BASE(chip) PNV9_CHIP_BASE(chip, 0x00060302031c0000ull) |
| 200 | |
| 201 | #define PNV9_XSCOM_SIZE 0x0000000400000000ull |
| 202 | #define PNV9_XSCOM_BASE(chip) PNV9_CHIP_BASE(chip, 0x00603fc00000000ull) |
| 203 | |
| 204 | #define PNV9_OCC_COMMON_AREA_SIZE 0x0000000000800000ull |
| 205 | #define PNV9_OCC_COMMON_AREA_BASE 0x203fff800000ull |
| 206 | #define PNV9_OCC_SENSOR_BASE(chip) (PNV9_OCC_COMMON_AREA_BASE + \ |
| 207 | PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id)) |
| 208 | |
| 209 | #define PNV9_HOMER_BASE(chip) \ |
| 210 | (0x203ffd800000ull + ((uint64_t)(chip)->chip_id) * PNV_HOMER_SIZE) |
| 211 | |
| 212 | /* |
| 213 | * POWER10 MMIO base addresses - 16TB stride per chip |
| 214 | */ |
| 215 | #define PNV10_CHIP_BASE(chip, base) \ |
| 216 | ((base) + ((uint64_t) (chip)->chip_id << 44)) |
| 217 | |
| 218 | #define PNV10_XSCOM_SIZE 0x0000000400000000ull |
| 219 | #define PNV10_XSCOM_BASE(chip) PNV10_CHIP_BASE(chip, 0x00603fc00000000ull) |
| 220 | |
| 221 | #define PNV10_LPCM_SIZE 0x0000000100000000ull |
| 222 | #define PNV10_LPCM_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030000000000ull) |
| 223 | |
| 224 | #define PNV10_XIVE2_IC_SIZE 0x0000000002000000ull |
| 225 | #define PNV10_XIVE2_IC_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030200000000ull) |
| 226 | |
| 227 | #define PNV10_PSIHB_ESB_SIZE 0x0000000000100000ull |
| 228 | #define PNV10_PSIHB_ESB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030202000000ull) |
| 229 | |
| 230 | #define PNV10_PSIHB_SIZE 0x0000000000100000ull |
| 231 | #define PNV10_PSIHB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030203000000ull) |
| 232 | |
| 233 | #define PNV10_XIVE2_TM_SIZE 0x0000000000040000ull |
| 234 | #define PNV10_XIVE2_TM_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030203180000ull) |
| 235 | |
| 236 | #define PNV10_XIVE2_NVC_SIZE 0x0000000008000000ull |
| 237 | #define PNV10_XIVE2_NVC_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030208000000ull) |
| 238 | |
| 239 | #define PNV10_XIVE2_NVPG_SIZE 0x0000010000000000ull |
| 240 | #define PNV10_XIVE2_NVPG_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006040000000000ull) |
| 241 | |
| 242 | #define PNV10_XIVE2_ESB_SIZE 0x0000010000000000ull |
| 243 | #define PNV10_XIVE2_ESB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006050000000000ull) |
| 244 | |
| 245 | #define PNV10_XIVE2_END_SIZE 0x0000020000000000ull |
| 246 | #define PNV10_XIVE2_END_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006060000000000ull) |
| 247 | |
| 248 | #define PNV10_OCC_COMMON_AREA_SIZE 0x0000000000800000ull |
| 249 | #define PNV10_OCC_COMMON_AREA_BASE 0x300fff800000ull |
| 250 | #define PNV10_OCC_SENSOR_BASE(chip) (PNV10_OCC_COMMON_AREA_BASE + \ |
| 251 | PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id)) |
| 252 | |
| 253 | #define PNV10_HOMER_BASE(chip) \ |
| 254 | (0x300ffd800000ll + ((uint64_t)(chip)->chip_id) * PNV_HOMER_SIZE) |
| 255 | |
| 256 | /* Power11 */ |
| 257 | #define PNV11_XSCOM_SIZE PNV10_XSCOM_SIZE |
| 258 | #define PNV11_XSCOM_BASE(chip) PNV10_XSCOM_BASE(chip) |
| 259 | |
| 260 | #define PNV11_LPCM_SIZE PNV10_LPCM_SIZE |
| 261 | #define PNV11_LPCM_BASE(chip) PNV10_LPCM_BASE(chip) |
| 262 | |
| 263 | #define PNV11_PSIHB_ESB_SIZE PNV10_PSIHB_ESB_SIZE |
| 264 | #define PNV11_PSIHB_ESB_BASE(chip) PNV10_PSIHB_ESB_BASE(chip) |
| 265 | |
| 266 | #define PNV11_PSIHB_SIZE PNV10_PSIHB_SIZE |
| 267 | #define PNV11_PSIHB_BASE(chip) PNV10_PSIHB_BASE(chip) |
| 268 | |
| 269 | #define PNV11_XIVE2_IC_SIZE PNV10_XIVE2_IC_SIZE |
| 270 | #define PNV11_XIVE2_IC_BASE(chip) PNV10_XIVE2_IC_BASE(chip) |
| 271 | |
| 272 | #define PNV11_XIVE2_TM_SIZE PNV10_XIVE2_TM_SIZE |
| 273 | #define PNV11_XIVE2_TM_BASE(chip) PNV10_XIVE2_TM_BASE(chip) |
| 274 | |
| 275 | #define PNV11_XIVE2_NVC_SIZE PNV10_XIVE2_NVC_SIZE |
| 276 | #define PNV11_XIVE2_NVC_BASE(chip) PNV10_XIVE2_NVC_BASE(chip) |
| 277 | |
| 278 | #define PNV11_XIVE2_NVPG_SIZE PNV10_XIVE2_NVPG_SIZE |
| 279 | #define PNV11_XIVE2_NVPG_BASE(chip) PNV10_XIVE2_NVPG_BASE(chip) |
| 280 | |
| 281 | #define PNV11_XIVE2_ESB_SIZE PNV10_XIVE2_ESB_SIZE |
| 282 | #define PNV11_XIVE2_ESB_BASE(chip) PNV10_XIVE2_ESB_BASE(chip) |
| 283 | |
| 284 | #define PNV11_XIVE2_END_SIZE PNV10_XIVE2_END_SIZE |
| 285 | #define PNV11_XIVE2_END_BASE(chip) PNV10_XIVE2_END_BASE(chip) |
| 286 | |
| 287 | #define PNV11_OCC_SENSOR_BASE(chip) PNV10_OCC_SENSOR_BASE(chip) |
| 288 | |
| 289 | /* MPIPL helpers */ |
| 290 | void do_mpipl_preserve(PnvMachineState *pnv); |
| 291 | bool do_mpipl_write(PnvMachineState *pnv); |
| 292 | |
| 293 | #endif /* PPC_PNV_H */ |