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1 #ifndef PPC_PNV_CHIP_H
2 #define PPC_PNV_CHIP_H
3
4 #include "hw/pci-host/pnv_phb4.h"
5 #include "hw/ppc/pnv_adu.h"
6 #include "hw/ppc/pnv_chiptod.h"
7 #include "hw/ppc/pnv_core.h"
8 #include "hw/ppc/pnv_homer.h"
9 #include "hw/ppc/pnv_n1_chiplet.h"
10 #include "hw/ppc/pnv_nmmu.h"
11 #include "hw/ssi/pnv_spi.h"
12 #include "hw/ppc/pnv_lpc.h"
13 #include "hw/ppc/pnv_occ.h"
14 #include "hw/ppc/pnv_psi.h"
15 #include "hw/ppc/pnv_sbe.h"
16 #include "hw/ppc/pnv_xive.h"
17 #include "hw/ppc/pnv_i2c.h"
18 #include "hw/core/sysbus.h"
19
20 OBJECT_DECLARE_TYPE(PnvChip, PnvChipClass,
21 PNV_CHIP)
22
23 struct PnvChip {
24 /*< private >*/
25 SysBusDevice parent_obj;
26
27 /*< public >*/
28 uint32_t chip_id;
29 uint64_t ram_start;
30 uint64_t ram_size;
31
32 bool big_core;
33 bool lpar_per_core;
34 uint32_t nr_cores;
35 uint32_t nr_threads;
36 uint64_t cores_mask;
37 PnvCore **cores;
38
39 uint32_t num_pecs;
40
41 MemoryRegion xscom_mmio;
42 MemoryRegion xscom;
43 AddressSpace xscom_as;
44
45 MemoryRegion *fw_mr;
46 gchar *dt_isa_nodename;
47 };
48
49 #define TYPE_PNV8_CHIP "pnv8-chip"
50 DECLARE_INSTANCE_CHECKER(Pnv8Chip, PNV8_CHIP,
51 TYPE_PNV8_CHIP)
52
53 struct Pnv8Chip {
54 /*< private >*/
55 PnvChip parent_obj;
56
57 /*< public >*/
58 MemoryRegion icp_mmio;
59
60 PnvLpcController lpc;
61 Pnv8Psi psi;
62 PnvOCC occ;
63 PnvHomer homer;
64
65 #define PNV8_CHIP_PHB3_MAX 4
66 /*
67 * The array is used to allow quick access to the phbs by
68 * pnv_ics_get_child() and pnv_ics_resend_child().
69 */
70 PnvPHB *phbs[PNV8_CHIP_PHB3_MAX];
71 uint32_t num_phbs;
72
73 XICSFabric *xics;
74 };
75
76 #define TYPE_PNV9_CHIP "pnv9-chip"
77 DECLARE_INSTANCE_CHECKER(Pnv9Chip, PNV9_CHIP,
78 TYPE_PNV9_CHIP)
79
80 struct Pnv9Chip {
81 /*< private >*/
82 PnvChip parent_obj;
83
84 /*< public >*/
85 PnvADU adu;
86 PnvXive xive;
87 Pnv9Psi psi;
88 PnvLpcController lpc;
89 PnvChipTOD chiptod;
90 PnvOCC occ;
91 PnvSBE sbe;
92 PnvHomer homer;
93
94 uint32_t nr_quads;
95 PnvQuad *quads;
96
97 #define PNV9_CHIP_MAX_PEC 3
98 PnvPhb4PecState pecs[PNV9_CHIP_MAX_PEC];
99
100 #define PNV9_CHIP_MAX_I2C 4
101 PnvI2C i2c[PNV9_CHIP_MAX_I2C];
102 };
103
104 /*
105 * A SMT8 fused core is a pair of SMT4 cores.
106 */
107 #define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
108 #define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f)
109
110 #define TYPE_PNV10_CHIP "pnv10-chip"
111 DECLARE_INSTANCE_CHECKER(Pnv10Chip, PNV10_CHIP,
112 TYPE_PNV10_CHIP)
113
114 struct Pnv10Chip {
115 /*< private >*/
116 PnvChip parent_obj;
117
118 /*< public >*/
119 PnvADU adu;
120 PnvXive2 xive;
121 Pnv9Psi psi;
122 PnvLpcController lpc;
123 PnvChipTOD chiptod;
124 PnvOCC occ;
125 PnvSBE sbe;
126 PnvHomer homer;
127 PnvN1Chiplet n1_chiplet;
128 #define PNV10_CHIP_MAX_PIB_SPIC 6
129 PnvSpi pib_spic[PNV10_CHIP_MAX_PIB_SPIC];
130 #define PNV10_CHIP_MAX_NMMU 2
131 PnvNMMU nmmu[PNV10_CHIP_MAX_NMMU];
132
133 uint32_t nr_quads;
134 PnvQuad *quads;
135
136 #define PNV10_CHIP_MAX_PEC 2
137 PnvPhb4PecState pecs[PNV10_CHIP_MAX_PEC];
138
139 #define PNV10_CHIP_MAX_I2C 4
140 PnvI2C i2c[PNV10_CHIP_MAX_I2C];
141 };
142
143 #define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
144 #define PNV10_PIR2CHIP(pir) (((pir) >> 8) & 0x7f)
145 #define PNV10_PIR2THREAD(pir) (((pir) & 0x7f))
146
147 #define TYPE_PNV11_CHIP "pnv11-chip"
148 DECLARE_INSTANCE_CHECKER(Pnv11Chip, PNV11_CHIP,
149 TYPE_PNV11_CHIP)
150
151 /* Power11 core is same as Power10 */
152 typedef struct Pnv10Chip Pnv11Chip;
153
154 struct PnvChipClass {
155 /*< private >*/
156 SysBusDeviceClass parent_class;
157
158 /*< public >*/
159 uint64_t chip_cfam_id;
160 uint64_t cores_mask;
161 uint32_t num_pecs;
162 uint32_t num_phbs;
163
164 uint32_t i2c_num_engines;
165 const int *i2c_ports_per_engine;
166
167 DeviceRealize parent_realize;
168
169 /* Get PIR and TIR values for a CPU thread identified by core/thread id */
170 void (*get_pir_tir)(PnvChip *chip, uint32_t core_id, uint32_t thread_id,
171 uint32_t *pir, uint32_t *tir);
172 void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp);
173 void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu);
174 void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu);
175 void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, GString *buf);
176 void* (*intc_get)(PnvChip *chip);
177 ISABus *(*isa_create)(PnvChip *chip, Error **errp);
178 void (*dt_populate)(PnvChip *chip, void *fdt);
179 void (*pic_print_info)(PnvChip *chip, GString *buf);
180 uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id);
181 uint32_t (*xscom_pcba)(PnvChip *chip, uint64_t addr);
182 };
183
184 #endif