| 1 | /* |
| 2 | * QEMU PowerPC PowerNV Processor I2C model |
| 3 | * |
| 4 | * Copyright (c) 2019-2023, IBM Corporation. |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 7 | */ |
| 8 | |
| 9 | #ifndef PPC_PNV_I2C_H |
| 10 | #define PPC_PNV_I2C_H |
| 11 | |
| 12 | #include "hw/ppc/pnv.h" |
| 13 | #include "hw/i2c/i2c.h" |
| 14 | #include "qemu/fifo8.h" |
| 15 | |
| 16 | #define TYPE_PNV_I2C "pnv-i2c" |
| 17 | #define PNV_I2C(obj) OBJECT_CHECK(PnvI2C, (obj), TYPE_PNV_I2C) |
| 18 | |
| 19 | #define PNV_I2C_REGS 0x20 |
| 20 | |
| 21 | typedef struct PnvI2C { |
| 22 | DeviceState parent; |
| 23 | |
| 24 | struct PnvChip *chip; |
| 25 | |
| 26 | qemu_irq psi_irq; |
| 27 | |
| 28 | uint64_t regs[PNV_I2C_REGS]; |
| 29 | uint32_t engine; |
| 30 | uint32_t num_busses; |
| 31 | I2CBus **busses; |
| 32 | |
| 33 | MemoryRegion xscom_regs; |
| 34 | |
| 35 | Fifo8 fifo; |
| 36 | } PnvI2C; |
| 37 | |
| 38 | #endif /* PPC_PNV_I2C_H */ |