| 1 | /* |
| 2 | * QEMU PowerPC nest pervasive common chiplet model |
| 3 | * |
| 4 | * Copyright (c) 2023, IBM Corporation. |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 7 | */ |
| 8 | |
| 9 | #ifndef PPC_PNV_NEST_CHIPLET_PERVASIVE_H |
| 10 | #define PPC_PNV_NEST_CHIPLET_PERVASIVE_H |
| 11 | |
| 12 | #define TYPE_PNV_NEST_CHIPLET_PERVASIVE "pnv-nest-chiplet-pervasive" |
| 13 | #define PNV_NEST_CHIPLET_PERVASIVE(obj) OBJECT_CHECK(PnvNestChipletPervasive, (obj), TYPE_PNV_NEST_CHIPLET_PERVASIVE) |
| 14 | |
| 15 | typedef struct PnvPervasiveCtrlRegs { |
| 16 | #define PNV_CPLT_CTRL_SIZE 6 |
| 17 | uint64_t cplt_ctrl[PNV_CPLT_CTRL_SIZE]; |
| 18 | uint64_t cplt_cfg0; |
| 19 | uint64_t cplt_cfg1; |
| 20 | uint64_t cplt_stat0; |
| 21 | uint64_t cplt_mask0; |
| 22 | uint64_t ctrl_protect_mode; |
| 23 | uint64_t ctrl_atomic_lock; |
| 24 | } PnvPervasiveCtrlRegs; |
| 25 | |
| 26 | typedef struct PnvNestChipletPervasive { |
| 27 | DeviceState parent; |
| 28 | MemoryRegion xscom_ctrl_regs_mr; |
| 29 | PnvPervasiveCtrlRegs control_regs; |
| 30 | } PnvNestChipletPervasive; |
| 31 | |
| 32 | #endif /*PPC_PNV_NEST_CHIPLET_PERVASIVE_H */ |