| 1 | /* |
| 2 | * QEMU PowerPC nest MMU model |
| 3 | * |
| 4 | * Copyright (c) 2025, IBM Corporation. |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 7 | * |
| 8 | * This code is licensed under the GPL version 2 or later. See the |
| 9 | * COPYING file in the top-level directory. |
| 10 | */ |
| 11 | |
| 12 | #ifndef PPC_PNV_NMMU_H |
| 13 | #define PPC_PNV_NMMU_H |
| 14 | |
| 15 | #define TYPE_PNV_NMMU "pnv-nmmu" |
| 16 | #define PNV_NMMU(obj) OBJECT_CHECK(PnvNMMU, (obj), TYPE_PNV_NMMU) |
| 17 | |
| 18 | typedef struct PnvNMMU { |
| 19 | DeviceState parent; |
| 20 | |
| 21 | struct PnvChip *chip; |
| 22 | |
| 23 | MemoryRegion xscom_regs; |
| 24 | uint32_t nmmu_id; |
| 25 | uint64_t ptcr; |
| 26 | } PnvNMMU; |
| 27 | |
| 28 | #endif /*PPC_PNV_NMMU_H */ |