| 1 | /* |
| 2 | * QEMU PowerPC PowerNV Emulation of a few OCC related registers |
| 3 | * |
| 4 | * Copyright (c) 2015-2022, IBM Corporation. |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2.1 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #ifndef PPC_PNV_OCC_H |
| 21 | #define PPC_PNV_OCC_H |
| 22 | |
| 23 | #include "system/memory.h" |
| 24 | #include "hw/core/qdev.h" |
| 25 | |
| 26 | #define TYPE_PNV_OCC "pnv-occ" |
| 27 | OBJECT_DECLARE_TYPE(PnvOCC, PnvOCCClass, |
| 28 | PNV_OCC) |
| 29 | #define TYPE_PNV8_OCC TYPE_PNV_OCC "-POWER8" |
| 30 | DECLARE_INSTANCE_CHECKER(PnvOCC, PNV8_OCC, |
| 31 | TYPE_PNV8_OCC) |
| 32 | #define TYPE_PNV9_OCC TYPE_PNV_OCC "-POWER9" |
| 33 | DECLARE_INSTANCE_CHECKER(PnvOCC, PNV9_OCC, |
| 34 | TYPE_PNV9_OCC) |
| 35 | #define TYPE_PNV10_OCC TYPE_PNV_OCC "-POWER10" |
| 36 | DECLARE_INSTANCE_CHECKER(PnvOCC, PNV10_OCC, TYPE_PNV10_OCC) |
| 37 | |
| 38 | #define PNV_OCC_SENSOR_DATA_BLOCK_OFFSET 0x00580000 |
| 39 | #define PNV_OCC_SENSOR_DATA_BLOCK_SIZE 0x00025800 |
| 40 | |
| 41 | struct PnvOCC { |
| 42 | DeviceState xd; |
| 43 | |
| 44 | /* OCC dynamic model is driven by this timer. */ |
| 45 | QEMUTimer state_machine_timer; |
| 46 | |
| 47 | /* OCC Misc interrupt */ |
| 48 | uint64_t occmisc; |
| 49 | |
| 50 | /* OCC Flags */ |
| 51 | #define NR_FLAG_REGS 8 |
| 52 | uint32_t occflags[NR_FLAG_REGS]; |
| 53 | |
| 54 | qemu_irq psi_irq; |
| 55 | |
| 56 | /* OCCs operate on regions of HOMER memory */ |
| 57 | PnvHomer *homer; |
| 58 | |
| 59 | MemoryRegion xscom_regs; |
| 60 | MemoryRegion sram_regs; |
| 61 | }; |
| 62 | |
| 63 | struct PnvOCCClass { |
| 64 | DeviceClass parent_class; |
| 65 | |
| 66 | hwaddr opal_shared_memory_offset; /* offset in HOMER */ |
| 67 | uint8_t opal_shared_memory_version; |
| 68 | |
| 69 | int xscom_size; |
| 70 | const MemoryRegionOps *xscom_ops; |
| 71 | }; |
| 72 | |
| 73 | #define PNV_OCC_SENSOR_DATA_BLOCK_BASE(i) \ |
| 74 | (PNV_OCC_SENSOR_DATA_BLOCK_OFFSET + (i) * PNV_OCC_SENSOR_DATA_BLOCK_SIZE) |
| 75 | |
| 76 | #endif /* PPC_PNV_OCC_H */ |