| 1 | /* |
| 2 | * QEMU PowerPC PowerNV XSCOM bus definitions |
| 3 | * |
| 4 | * Copyright (c) 2016, IBM Corporation. |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2.1 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #ifndef PPC_PNV_XSCOM_H |
| 21 | #define PPC_PNV_XSCOM_H |
| 22 | |
| 23 | #include "system/memory.h" |
| 24 | |
| 25 | typedef struct PnvXScomInterface PnvXScomInterface; |
| 26 | typedef struct PnvChip PnvChip; |
| 27 | |
| 28 | #define TYPE_PNV_XSCOM_INTERFACE "pnv-xscom-interface" |
| 29 | #define PNV_XSCOM_INTERFACE(obj) \ |
| 30 | INTERFACE_CHECK(PnvXScomInterface, (obj), TYPE_PNV_XSCOM_INTERFACE) |
| 31 | typedef struct PnvXScomInterfaceClass PnvXScomInterfaceClass; |
| 32 | DECLARE_CLASS_CHECKERS(PnvXScomInterfaceClass, PNV_XSCOM_INTERFACE, |
| 33 | TYPE_PNV_XSCOM_INTERFACE) |
| 34 | |
| 35 | struct PnvXScomInterfaceClass { |
| 36 | InterfaceClass parent; |
| 37 | int (*dt_xscom)(PnvXScomInterface *dev, void *fdt, int offset); |
| 38 | }; |
| 39 | |
| 40 | /* |
| 41 | * Layout of the XSCOM PCB addresses of EX core 1 (POWER 8) |
| 42 | * |
| 43 | * GPIO 0x1100xxxx |
| 44 | * SCOM 0x1101xxxx |
| 45 | * OHA 0x1102xxxx |
| 46 | * CLOCK CTL 0x1103xxxx |
| 47 | * FIR 0x1104xxxx |
| 48 | * THERM 0x1105xxxx |
| 49 | * <reserved> 0x1106xxxx |
| 50 | * .. |
| 51 | * 0x110Exxxx |
| 52 | * PCB SLAVE 0x110Fxxxx |
| 53 | */ |
| 54 | |
| 55 | #define PNV_XSCOM_EX_CORE_BASE 0x10000000ull |
| 56 | |
| 57 | #define PNV_XSCOM_EX_BASE(core) \ |
| 58 | (PNV_XSCOM_EX_CORE_BASE | ((uint64_t)(core) << 24)) |
| 59 | #define PNV_XSCOM_EX_SIZE 0x100000 |
| 60 | |
| 61 | #define PNV_XSCOM_LPC_BASE 0xb0020 |
| 62 | #define PNV_XSCOM_LPC_SIZE 0x4 |
| 63 | |
| 64 | #define PNV_XSCOM_PSIHB_BASE 0x2010900 |
| 65 | #define PNV_XSCOM_PSIHB_SIZE 0x20 |
| 66 | |
| 67 | #define PNV_XSCOM_CHIPTOD_BASE 0x0040000 |
| 68 | #define PNV_XSCOM_CHIPTOD_SIZE 0x31 |
| 69 | |
| 70 | #define PNV_XSCOM_OCC_BASE 0x0066000 |
| 71 | #define PNV_XSCOM_OCC_SIZE 0x6000 |
| 72 | |
| 73 | #define PNV_XSCOM_PBA_BASE 0x2013f00 |
| 74 | #define PNV_XSCOM_PBA_SIZE 0x40 |
| 75 | |
| 76 | #define PNV_XSCOM_PBCQ_NEST_BASE 0x2012000 |
| 77 | #define PNV_XSCOM_PBCQ_NEST_SIZE 0x46 |
| 78 | |
| 79 | #define PNV_XSCOM_PBCQ_PCI_BASE 0x9012000 |
| 80 | #define PNV_XSCOM_PBCQ_PCI_SIZE 0x15 |
| 81 | |
| 82 | #define PNV_XSCOM_PBCQ_SPCI_BASE 0x9013c00 |
| 83 | #define PNV_XSCOM_PBCQ_SPCI_SIZE 0x5 |
| 84 | |
| 85 | #define PNV9_XSCOM_ADU_BASE 0x0090000 |
| 86 | #define PNV9_XSCOM_ADU_SIZE 0x55 |
| 87 | |
| 88 | /* |
| 89 | * Layout of the XSCOM PCB addresses (POWER 9) |
| 90 | */ |
| 91 | #define PNV9_XSCOM_EC_BASE(core) \ |
| 92 | ((uint64_t)(((core) & 0x1F) + 0x20) << 24) |
| 93 | #define PNV9_XSCOM_EC_SIZE 0x100000 |
| 94 | |
| 95 | #define PNV9_XSCOM_EQ_BASE(core) \ |
| 96 | ((uint64_t)(((core) & 0x1C) + 0x40) << 22) |
| 97 | #define PNV9_XSCOM_EQ_SIZE 0x100000 |
| 98 | |
| 99 | #define PNV9_XSCOM_I2CM_BASE 0xa0000 |
| 100 | #define PNV9_XSCOM_I2CM_SIZE 0x1000 |
| 101 | |
| 102 | #define PNV9_XSCOM_CHIPTOD_BASE PNV_XSCOM_CHIPTOD_BASE |
| 103 | #define PNV9_XSCOM_CHIPTOD_SIZE PNV_XSCOM_CHIPTOD_SIZE |
| 104 | |
| 105 | #define PNV9_XSCOM_OCC_BASE PNV_XSCOM_OCC_BASE |
| 106 | #define PNV9_XSCOM_OCC_SIZE 0x8000 |
| 107 | |
| 108 | #define PNV9_XSCOM_SBE_CTRL_BASE 0x00050008 |
| 109 | #define PNV9_XSCOM_SBE_CTRL_SIZE 0x1 |
| 110 | |
| 111 | #define PNV9_XSCOM_SBE_MBOX_BASE 0x000D0050 |
| 112 | #define PNV9_XSCOM_SBE_MBOX_SIZE 0x16 |
| 113 | |
| 114 | #define PNV9_XSCOM_PBA_BASE 0x5012b00 |
| 115 | #define PNV9_XSCOM_PBA_SIZE 0x40 |
| 116 | |
| 117 | #define PNV9_XSCOM_PSIHB_BASE 0x5012900 |
| 118 | #define PNV9_XSCOM_PSIHB_SIZE 0x100 |
| 119 | |
| 120 | #define PNV9_XSCOM_XIVE_BASE 0x5013000 |
| 121 | #define PNV9_XSCOM_XIVE_SIZE 0x300 |
| 122 | |
| 123 | #define PNV9_XSCOM_PEC_NEST_BASE 0x4010c00 |
| 124 | #define PNV9_XSCOM_PEC_NEST_SIZE 0x100 |
| 125 | |
| 126 | #define PNV9_XSCOM_PEC_PCI_BASE 0xd010800 |
| 127 | #define PNV9_XSCOM_PEC_PCI_SIZE 0x200 |
| 128 | |
| 129 | #define PNV9_XSCOM_PEC_NEST_CPLT_BASE 0x0d000000 |
| 130 | |
| 131 | /* XSCOM PCI "pass-through" window to PHB SCOM */ |
| 132 | #define PNV9_XSCOM_PEC_PCI_STK0 0x100 |
| 133 | #define PNV9_XSCOM_PEC_PCI_STK1 0x140 |
| 134 | #define PNV9_XSCOM_PEC_PCI_STK2 0x180 |
| 135 | |
| 136 | #define PNV10_XSCOM_ADU_BASE 0x0090000 |
| 137 | #define PNV10_XSCOM_ADU_SIZE 0x55 |
| 138 | |
| 139 | /* |
| 140 | * Layout of the XSCOM PCB addresses (POWER 10) |
| 141 | */ |
| 142 | #define PNV10_XSCOM_EQ_CHIPLET(core) (0x20 + ((core) >> 2)) |
| 143 | #define PNV10_XSCOM_EQ(chiplet) ((chiplet) << 24) |
| 144 | #define PNV10_XSCOM_EC(proc) \ |
| 145 | ((0x2 << 16) | ((1 << (3 - (proc))) << 12)) |
| 146 | |
| 147 | #define PNV10_XSCOM_QME(chiplet) \ |
| 148 | (PNV10_XSCOM_EQ(chiplet) | (0xE << 16)) |
| 149 | |
| 150 | /* |
| 151 | * Make the region larger by 0x1000 (instead of starting at an offset) so the |
| 152 | * modelled addresses start from 0 |
| 153 | */ |
| 154 | #define PNV10_XSCOM_QME_BASE(core) \ |
| 155 | ((uint64_t) PNV10_XSCOM_QME(PNV10_XSCOM_EQ_CHIPLET(core))) |
| 156 | #define PNV10_XSCOM_QME_SIZE (0x8000 + 0x1000) |
| 157 | |
| 158 | #define PNV10_XSCOM_EQ_BASE(core) \ |
| 159 | ((uint64_t) PNV10_XSCOM_EQ(PNV10_XSCOM_EQ_CHIPLET(core))) |
| 160 | #define PNV10_XSCOM_EQ_SIZE 0x20000 |
| 161 | |
| 162 | #define PNV10_XSCOM_EC_BASE(core) \ |
| 163 | ((uint64_t) PNV10_XSCOM_EQ_BASE(core) | PNV10_XSCOM_EC(core & 0x3)) |
| 164 | #define PNV10_XSCOM_EC_SIZE 0x1000 |
| 165 | |
| 166 | #define PNV10_XSCOM_PSIHB_BASE 0x3011D00 |
| 167 | #define PNV10_XSCOM_PSIHB_SIZE 0x100 |
| 168 | |
| 169 | #define PNV10_XSCOM_I2CM_BASE PNV9_XSCOM_I2CM_BASE |
| 170 | #define PNV10_XSCOM_I2CM_SIZE PNV9_XSCOM_I2CM_SIZE |
| 171 | |
| 172 | #define PNV10_XSCOM_CHIPTOD_BASE PNV9_XSCOM_CHIPTOD_BASE |
| 173 | #define PNV10_XSCOM_CHIPTOD_SIZE PNV9_XSCOM_CHIPTOD_SIZE |
| 174 | |
| 175 | #define PNV10_XSCOM_OCC_BASE PNV9_XSCOM_OCC_BASE |
| 176 | #define PNV10_XSCOM_OCC_SIZE PNV9_XSCOM_OCC_SIZE |
| 177 | |
| 178 | #define PNV10_XSCOM_SBE_CTRL_BASE PNV9_XSCOM_SBE_CTRL_BASE |
| 179 | #define PNV10_XSCOM_SBE_CTRL_SIZE PNV9_XSCOM_SBE_CTRL_SIZE |
| 180 | |
| 181 | #define PNV10_XSCOM_SBE_MBOX_BASE PNV9_XSCOM_SBE_MBOX_BASE |
| 182 | #define PNV10_XSCOM_SBE_MBOX_SIZE PNV9_XSCOM_SBE_MBOX_SIZE |
| 183 | |
| 184 | #define PNV10_XSCOM_PBA_BASE 0x01010CDA |
| 185 | #define PNV10_XSCOM_PBA_SIZE 0x40 |
| 186 | |
| 187 | #define PNV10_XSCOM_XIVE2_BASE 0x2010800 |
| 188 | #define PNV10_XSCOM_XIVE2_SIZE 0x400 |
| 189 | |
| 190 | #define PNV10_XSCOM_N1_CHIPLET_CTRL_REGS_BASE 0x3000000 |
| 191 | #define PNV10_XSCOM_CHIPLET_CTRL_REGS_SIZE 0x400 |
| 192 | |
| 193 | #define PNV10_XSCOM_N1_PB_SCOM_EQ_BASE 0x3011000 |
| 194 | #define PNV10_XSCOM_N1_PB_SCOM_EQ_SIZE 0x200 |
| 195 | |
| 196 | #define PNV10_XSCOM_N1_PB_SCOM_ES_BASE 0x3011300 |
| 197 | #define PNV10_XSCOM_N1_PB_SCOM_ES_SIZE 0x100 |
| 198 | |
| 199 | #define PNV10_XSCOM_NEST0_MMU_BASE 0x2010c40 |
| 200 | #define PNV10_XSCOM_NEST1_MMU_BASE 0x3010c40 |
| 201 | #define PNV10_XSCOM_NMMU_SIZE 0x20 |
| 202 | |
| 203 | #define PNV10_XSCOM_PEC_NEST_BASE 0x3011800 /* index goes downwards ... */ |
| 204 | #define PNV10_XSCOM_PEC_NEST_SIZE 0x100 |
| 205 | |
| 206 | #define PNV10_XSCOM_PEC_NEST_CPLT_BASE 0x08000000 |
| 207 | |
| 208 | #define PNV10_XSCOM_PEC_PCI_BASE 0x8010800 /* index goes upwards ... */ |
| 209 | #define PNV10_XSCOM_PEC_PCI_SIZE 0x200 |
| 210 | |
| 211 | #define PNV10_XSCOM_PIB_SPIC_BASE 0xc0000 |
| 212 | #define PNV10_XSCOM_PIB_SPIC_SIZE 0x20 |
| 213 | |
| 214 | /* |
| 215 | * Power11 core is same as Power10 |
| 216 | */ |
| 217 | #define PNV11_XSCOM_EC_BASE(core) PNV10_XSCOM_EC_BASE(core) |
| 218 | |
| 219 | #define PNV11_XSCOM_ADU_BASE PNV10_XSCOM_ADU_BASE |
| 220 | #define PNV11_XSCOM_ADU_SIZE PNV10_XSCOM_ADU_SIZE |
| 221 | |
| 222 | #define PNV11_XSCOM_QME_BASE(core) PNV10_XSCOM_QME_BASE(core) |
| 223 | |
| 224 | #define PNV11_XSCOM_EQ_BASE(core) PNV10_XSCOM_EQ_BASE(core) |
| 225 | |
| 226 | #define PNV11_XSCOM_PSIHB_BASE PNV10_XSCOM_PSIHB_BASE |
| 227 | #define PNV11_XSCOM_PSIHB_SIZE PNV10_XSCOM_PSIHB_SIZE |
| 228 | |
| 229 | #define PNV11_XSCOM_I2CM_BASE PNV10_XSCOM_I2CM_BASE |
| 230 | #define PNV11_XSCOM_I2CM_SIZE PNV10_XSCOM_I2CM_SIZE |
| 231 | |
| 232 | #define PNV11_XSCOM_CHIPTOD_BASE PNV10_XSCOM_CHIPTOD_BASE |
| 233 | #define PNV11_XSCOM_CHIPTOD_SIZE PNV10_XSCOM_CHIPTOD_SIZE |
| 234 | |
| 235 | #define PNV11_XSCOM_OCC_BASE PNV10_XSCOM_OCC_BASE |
| 236 | #define PNV11_XSCOM_OCC_SIZE PNV10_XSCOM_OCC_SIZE |
| 237 | |
| 238 | #define PNV11_XSCOM_SBE_CTRL_BASE PNV10_XSCOM_SBE_CTRL_BASE |
| 239 | #define PNV11_XSCOM_SBE_CTRL_SIZE PNV10_XSCOM_SBE_CTRL_SIZE |
| 240 | |
| 241 | #define PNV11_XSCOM_SBE_MBOX_BASE PNV10_XSCOM_SBE_MBOX_BASE |
| 242 | #define PNV11_XSCOM_SBE_MBOX_SIZE PNV10_XSCOM_SBE_MBOX_SIZE |
| 243 | |
| 244 | #define PNV11_XSCOM_PBA_BASE PNV10_XSCOM_PBA_BASE |
| 245 | #define PNV11_XSCOM_PBA_SIZE PNV10_XSCOM_PBA_SIZE |
| 246 | |
| 247 | #define PNV11_XSCOM_XIVE2_BASE PNV10_XSCOM_XIVE2_BASE |
| 248 | #define PNV11_XSCOM_XIVE2_SIZE PNV10_XSCOM_XIVE2_SIZE |
| 249 | |
| 250 | #define PNV11_XSCOM_N1_CHIPLET_CTRL_REGS_BASE \ |
| 251 | PNV10_XSCOM_N1_CHIPLET_CTRL_REGS_BASE |
| 252 | #define PNV11_XSCOM_CHIPLET_CTRL_REGS_SIZE PNV10_XSCOM_CHIPLET_CTRL_REGS_SIZE |
| 253 | |
| 254 | #define PNV11_XSCOM_N1_PB_SCOM_EQ_BASE PNV10_XSCOM_N1_PB_SCOM_EQ_BASE |
| 255 | #define PNV11_XSCOM_N1_PB_SCOM_EQ_SIZE PNV10_XSCOM_N1_PB_SCOM_EQ_SIZE |
| 256 | |
| 257 | #define PNV11_XSCOM_N1_PB_SCOM_ES_BASE PNV10_XSCOM_N1_PB_SCOM_ES_BASE |
| 258 | #define PNV11_XSCOM_N1_PB_SCOM_ES_SIZE PNV10_XSCOM_N1_PB_SCOM_ES_SIZE |
| 259 | |
| 260 | #define PNV11_XSCOM_PIB_SPIC_BASE PNV10_XSCOM_PIB_SPIC_BASE |
| 261 | #define PNV11_XSCOM_PIB_SPIC_SIZE PNV10_XSCOM_PIB_SPIC_SIZE |
| 262 | |
| 263 | void pnv_xscom_init(PnvChip *chip, uint64_t size, hwaddr addr); |
| 264 | int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset, |
| 265 | uint64_t xscom_base, uint64_t xscom_size, |
| 266 | const char *compat, int compat_size); |
| 267 | |
| 268 | void pnv_xscom_add_subregion(PnvChip *chip, hwaddr offset, |
| 269 | MemoryRegion *mr); |
| 270 | void pnv_xscom_region_init(MemoryRegion *mr, |
| 271 | Object *owner, |
| 272 | const MemoryRegionOps *ops, |
| 273 | void *opaque, |
| 274 | const char *name, |
| 275 | uint64_t size); |
| 276 | |
| 277 | #endif /* PPC_PNV_XSCOM_H */ |