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1 /*
2 * QEMU PowerPC 4xx emulation shared definitions
3 *
4 * Copyright (c) 2007 Jocelyn Mayer
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #ifndef PPC4XX_H
26 #define PPC4XX_H
27
28 #include "hw/ppc/ppc.h"
29 #include "system/memory.h"
30 #include "hw/core/sysbus.h"
31
32 /*
33 * Generic DCR device
34 */
35 #define TYPE_PPC4xx_DCR_DEVICE "ppc4xx-dcr-device"
36 OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxDcrDeviceState, PPC4xx_DCR_DEVICE);
37 struct Ppc4xxDcrDeviceState {
38 SysBusDevice parent_obj;
39
40 PowerPCCPU *cpu;
41 };
42
43 void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn, void *opaque,
44 dcr_read_cb dcr_read, dcr_write_cb dcr_write);
45 bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu,
46 Error **errp);
47
48 /* Memory Access Layer (MAL) */
49 #define TYPE_PPC4xx_MAL "ppc4xx-mal"
50 OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxMalState, PPC4xx_MAL);
51 struct Ppc4xxMalState {
52 Ppc4xxDcrDeviceState parent_obj;
53
54 qemu_irq irqs[4];
55 uint32_t cfg;
56 uint32_t esr;
57 uint32_t ier;
58 uint32_t txcasr;
59 uint32_t txcarr;
60 uint32_t txeobisr;
61 uint32_t txdeir;
62 uint32_t rxcasr;
63 uint32_t rxcarr;
64 uint32_t rxeobisr;
65 uint32_t rxdeir;
66 uint32_t *txctpr;
67 uint32_t *rxctpr;
68 uint32_t *rcbs;
69 uint8_t txcnum;
70 uint8_t rxcnum;
71 };
72
73 /* Peripheral local bus arbitrer */
74 #define TYPE_PPC4xx_PLB "ppc4xx-plb"
75 OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxPlbState, PPC4xx_PLB);
76 struct Ppc4xxPlbState {
77 Ppc4xxDcrDeviceState parent_obj;
78
79 uint32_t acr;
80 uint32_t bear;
81 uint32_t besr;
82 };
83
84 /* Peripheral controller */
85 #define TYPE_PPC4xx_EBC "ppc4xx-ebc"
86 OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxEbcState, PPC4xx_EBC);
87 struct Ppc4xxEbcState {
88 Ppc4xxDcrDeviceState parent_obj;
89
90 uint32_t addr;
91 uint32_t bcr[8];
92 uint32_t bap[8];
93 uint32_t bear;
94 uint32_t besr0;
95 uint32_t besr1;
96 uint32_t cfg;
97 };
98
99 /* SDRAM DDR controller */
100 typedef struct {
101 MemoryRegion ram;
102 MemoryRegion container; /* used for clipping */
103 hwaddr base;
104 hwaddr size;
105 uint32_t bcr;
106 } Ppc4xxSdramBank;
107
108 #define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n)) & 0x03) << 29)
109 #define SDR0_DDR0_DDRM_DDR1 0x20000000
110 #define SDR0_DDR0_DDRM_DDR2 0x40000000
111
112 #define TYPE_PPC4xx_SDRAM_DDR "ppc4xx-sdram-ddr"
113 OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxSdramDdrState, PPC4xx_SDRAM_DDR);
114 struct Ppc4xxSdramDdrState {
115 Ppc4xxDcrDeviceState parent_obj;
116
117 MemoryRegion *dram_mr;
118 uint32_t nbanks; /* Banks to use from 4, e.g. when board has less slots */
119 Ppc4xxSdramBank bank[4];
120 qemu_irq irq;
121
122 uint32_t addr;
123 uint32_t besr0;
124 uint32_t besr1;
125 uint32_t bear;
126 uint32_t cfg;
127 uint32_t status;
128 uint32_t rtr;
129 uint32_t pmit;
130 uint32_t tr;
131 uint32_t ecccfg;
132 uint32_t eccesr;
133 };
134
135 void ppc4xx_sdram_ddr_enable(Ppc4xxSdramDdrState *s);
136
137 /* SDRAM DDR2 controller */
138 #define TYPE_PPC4xx_SDRAM_DDR2 "ppc4xx-sdram-ddr2"
139 OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxSdramDdr2State, PPC4xx_SDRAM_DDR2);
140 struct Ppc4xxSdramDdr2State {
141 Ppc4xxDcrDeviceState parent_obj;
142
143 MemoryRegion *dram_mr;
144 uint32_t nbanks; /* Banks to use from 4, e.g. when board has less slots */
145 Ppc4xxSdramBank bank[4];
146
147 uint32_t addr;
148 uint32_t mcopt2;
149 };
150
151 void ppc4xx_sdram_ddr2_enable(Ppc4xxSdramDdr2State *s);
152
153 #endif /* PPC4XX_H */