| 1 | #ifndef HW_SPAPR_H |
| 2 | #define HW_SPAPR_H |
| 3 | |
| 4 | #include "qemu/units.h" |
| 5 | #include "system/dma.h" |
| 6 | #include "hw/core/boards.h" |
| 7 | #include "hw/ppc/spapr_common.h" |
| 8 | #include "hw/ppc/spapr_drc.h" |
| 9 | #include "hw/mem/pc-dimm.h" |
| 10 | #include "hw/ppc/spapr_ovec.h" |
| 11 | #include "hw/ppc/spapr_irq.h" |
| 12 | #include "qom/object.h" |
| 13 | #include "hw/ppc/spapr_xive.h" /* For SpaprXive */ |
| 14 | #include "hw/ppc/xics.h" /* For ICSState */ |
| 15 | #include "hw/ppc/spapr_tpm_proxy.h" |
| 16 | #include "hw/ppc/spapr_nested.h" /* For SpaprMachineStateNested */ |
| 17 | #include "hw/ppc/spapr_fadump.h" /* For FadumpMemStruct */ |
| 18 | |
| 19 | struct SpaprVioBus; |
| 20 | struct SpaprPhbState; |
| 21 | struct SpaprNvram; |
| 22 | |
| 23 | typedef struct SpaprEventLogEntry SpaprEventLogEntry; |
| 24 | typedef struct SpaprEventSource SpaprEventSource; |
| 25 | typedef struct SpaprPendingHpt SpaprPendingHpt; |
| 26 | |
| 27 | typedef struct Vof Vof; |
| 28 | |
| 29 | #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL |
| 30 | #define SPAPR_ENTRY_POINT 0x100 |
| 31 | |
| 32 | #define SPAPR_TIMEBASE_FREQ 512000000ULL |
| 33 | |
| 34 | #define TYPE_SPAPR_RTC "spapr-rtc" |
| 35 | |
| 36 | OBJECT_DECLARE_SIMPLE_TYPE(SpaprRtcState, SPAPR_RTC) |
| 37 | |
| 38 | struct SpaprRtcState { |
| 39 | /*< private >*/ |
| 40 | DeviceState parent_obj; |
| 41 | int64_t ns_offset; |
| 42 | }; |
| 43 | |
| 44 | typedef struct SpaprDimmState SpaprDimmState; |
| 45 | |
| 46 | #define TYPE_SPAPR_MACHINE "spapr-machine" |
| 47 | OBJECT_DECLARE_TYPE(SpaprMachineState, SpaprMachineClass, SPAPR_MACHINE) |
| 48 | |
| 49 | typedef enum { |
| 50 | SPAPR_RESIZE_HPT_DEFAULT = 0, |
| 51 | SPAPR_RESIZE_HPT_DISABLED, |
| 52 | SPAPR_RESIZE_HPT_ENABLED, |
| 53 | SPAPR_RESIZE_HPT_REQUIRED, |
| 54 | } SpaprResizeHpt; |
| 55 | |
| 56 | /** |
| 57 | * Capabilities |
| 58 | */ |
| 59 | |
| 60 | /* Hardware Transactional Memory */ |
| 61 | #define SPAPR_CAP_HTM 0x00 |
| 62 | /* Vector Scalar Extensions */ |
| 63 | #define SPAPR_CAP_VSX 0x01 |
| 64 | /* Decimal Floating Point */ |
| 65 | #define SPAPR_CAP_DFP 0x02 |
| 66 | /* Cache Flush on Privilege Change */ |
| 67 | #define SPAPR_CAP_CFPC 0x03 |
| 68 | /* Speculation Barrier Bounds Checking */ |
| 69 | #define SPAPR_CAP_SBBC 0x04 |
| 70 | /* Indirect Branch Serialisation */ |
| 71 | #define SPAPR_CAP_IBS 0x05 |
| 72 | /* HPT Maximum Page Size (encoded as a shift) */ |
| 73 | #define SPAPR_CAP_HPT_MAXPAGESIZE 0x06 |
| 74 | /* Nested KVM-HV */ |
| 75 | #define SPAPR_CAP_NESTED_KVM_HV 0x07 |
| 76 | /* Large Decrementer */ |
| 77 | #define SPAPR_CAP_LARGE_DECREMENTER 0x08 |
| 78 | /* Count Cache Flush Assist HW Instruction */ |
| 79 | #define SPAPR_CAP_CCF_ASSIST 0x09 |
| 80 | /* Implements PAPR FWNMI option */ |
| 81 | #define SPAPR_CAP_FWNMI 0x0A |
| 82 | /* Support H_RPT_INVALIDATE */ |
| 83 | #define SPAPR_CAP_RPT_INVALIDATE 0x0B |
| 84 | /* Support for AIL modes */ |
| 85 | #define SPAPR_CAP_AIL_MODE_3 0x0C |
| 86 | /* Nested PAPR */ |
| 87 | #define SPAPR_CAP_NESTED_PAPR 0x0D |
| 88 | /* DAWR1 */ |
| 89 | #define SPAPR_CAP_DAWR1 0x0E |
| 90 | /* Num Caps */ |
| 91 | #define SPAPR_CAP_NUM (SPAPR_CAP_DAWR1 + 1) |
| 92 | |
| 93 | /* |
| 94 | * Capability Values |
| 95 | */ |
| 96 | /* Bool Caps */ |
| 97 | #define SPAPR_CAP_OFF 0x00 |
| 98 | #define SPAPR_CAP_ON 0x01 |
| 99 | |
| 100 | /* Custom Caps */ |
| 101 | |
| 102 | /* Generic */ |
| 103 | #define SPAPR_CAP_BROKEN 0x00 |
| 104 | #define SPAPR_CAP_WORKAROUND 0x01 |
| 105 | #define SPAPR_CAP_FIXED 0x02 |
| 106 | /* SPAPR_CAP_IBS (cap-ibs) */ |
| 107 | #define SPAPR_CAP_FIXED_IBS 0x02 |
| 108 | #define SPAPR_CAP_FIXED_CCD 0x03 |
| 109 | #define SPAPR_CAP_FIXED_NA 0x10 /* Lets leave a bit of a gap... */ |
| 110 | |
| 111 | #define FDT_MAX_SIZE 0x200000 |
| 112 | |
| 113 | /* Max number of NUMA nodes */ |
| 114 | #define NUMA_NODES_MAX_NUM (MAX_NODES) |
| 115 | |
| 116 | /* |
| 117 | * NUMA FORM1 macros. FORM1_DIST_REF_POINTS was taken from |
| 118 | * MAX_DISTANCE_REF_POINTS in arch/powerpc/mm/numa.h from Linux |
| 119 | * kernel source. It represents the amount of associativity domains |
| 120 | * for non-CPU resources. |
| 121 | * |
| 122 | * FORM1_NUMA_ASSOC_SIZE is the base array size of an ibm,associativity |
| 123 | * array for any non-CPU resource. |
| 124 | */ |
| 125 | #define FORM1_DIST_REF_POINTS 4 |
| 126 | #define FORM1_NUMA_ASSOC_SIZE (FORM1_DIST_REF_POINTS + 1) |
| 127 | |
| 128 | /* |
| 129 | * FORM2 NUMA affinity has a single associativity domain, giving |
| 130 | * us a assoc size of 2. |
| 131 | */ |
| 132 | #define FORM2_DIST_REF_POINTS 1 |
| 133 | #define FORM2_NUMA_ASSOC_SIZE (FORM2_DIST_REF_POINTS + 1) |
| 134 | |
| 135 | typedef struct SpaprCapabilities SpaprCapabilities; |
| 136 | struct SpaprCapabilities { |
| 137 | uint8_t caps[SPAPR_CAP_NUM]; |
| 138 | }; |
| 139 | |
| 140 | /** |
| 141 | * SpaprMachineClass: |
| 142 | */ |
| 143 | struct SpaprMachineClass { |
| 144 | MachineClass parent_class; |
| 145 | |
| 146 | bool pre_5_1_assoc_refpoints; |
| 147 | bool pre_5_2_numa_associativity; |
| 148 | bool pre_6_2_numa_affinity; |
| 149 | SpaprResizeHpt resize_hpt_default; |
| 150 | SpaprCapabilities default_caps; |
| 151 | SpaprIrq *irq; |
| 152 | }; |
| 153 | |
| 154 | #define WDT_MAX_WATCHDOGS 4 /* Maximum number of watchdog devices */ |
| 155 | |
| 156 | #define TYPE_SPAPR_WDT "spapr-wdt" |
| 157 | OBJECT_DECLARE_SIMPLE_TYPE(SpaprWatchdog, SPAPR_WDT) |
| 158 | |
| 159 | typedef struct SpaprWatchdog { |
| 160 | /*< private >*/ |
| 161 | DeviceState parent_obj; |
| 162 | /*< public >*/ |
| 163 | |
| 164 | QEMUTimer timer; |
| 165 | uint8_t action; /* One of PSERIES_WDTF_ACTION_xxx */ |
| 166 | uint8_t leave_others; /* leaveOtherWatchdogsRunningOnTimeout */ |
| 167 | } SpaprWatchdog; |
| 168 | |
| 169 | /** |
| 170 | * SpaprMachineState: |
| 171 | */ |
| 172 | struct SpaprMachineState { |
| 173 | /*< private >*/ |
| 174 | MachineState parent_obj; |
| 175 | |
| 176 | struct SpaprVioBus *vio_bus; |
| 177 | QLIST_HEAD(, SpaprPhbState) phbs; |
| 178 | struct SpaprNvram *nvram; |
| 179 | SpaprRtcState rtc; |
| 180 | |
| 181 | SpaprResizeHpt resize_hpt; |
| 182 | void *htab; |
| 183 | uint32_t htab_shift; |
| 184 | uint64_t patb_entry; /* Process tbl registered in H_REGISTER_PROC_TBL */ |
| 185 | SpaprPendingHpt *pending_hpt; /* in-progress resize */ |
| 186 | |
| 187 | hwaddr rma_size; |
| 188 | uint32_t fdt_size; |
| 189 | uint32_t fdt_initial_size; |
| 190 | void *fdt_blob; |
| 191 | uint8_t fdt_rng_seed[32]; |
| 192 | uint64_t hashpkey_val; |
| 193 | long kernel_size; |
| 194 | bool kernel_le; |
| 195 | uint64_t kernel_addr; |
| 196 | uint32_t initrd_base; |
| 197 | long initrd_size; |
| 198 | Vof *vof; |
| 199 | uint64_t rtc_offset; /* Now used only during incoming migration */ |
| 200 | struct PPCTimebase tb; |
| 201 | bool want_stdout_path; |
| 202 | uint32_t vsmt; /* Virtual SMT mode (KVM's "core stride") */ |
| 203 | |
| 204 | /* Nested HV support (TCG only) */ |
| 205 | SpaprMachineStateNested nested; |
| 206 | |
| 207 | Notifier epow_notifier; |
| 208 | QTAILQ_HEAD(, SpaprEventLogEntry) pending_events; |
| 209 | bool use_hotplug_event_source; |
| 210 | SpaprEventSource *event_sources; |
| 211 | |
| 212 | /* ibm,client-architecture-support option negotiation */ |
| 213 | bool cas_pre_isa3_guest; |
| 214 | SpaprOptionVector *ov5; /* QEMU-supported option vectors */ |
| 215 | SpaprOptionVector *ov5_cas; /* negotiated (via CAS) option vectors */ |
| 216 | uint32_t max_compat_pvr; |
| 217 | |
| 218 | /* Migration state */ |
| 219 | int htab_save_index; |
| 220 | bool htab_first_pass; |
| 221 | int htab_fd; |
| 222 | |
| 223 | /* Pending DIMM unplug cache. It is populated when a LMB |
| 224 | * unplug starts. It can be regenerated if a migration |
| 225 | * occurs during the unplug process. */ |
| 226 | QTAILQ_HEAD(, SpaprDimmState) pending_dimm_unplugs; |
| 227 | |
| 228 | /* State related to FWNMI option */ |
| 229 | |
| 230 | /* System Reset and Machine Check Notification Routine addresses |
| 231 | * registered by "ibm,nmi-register" RTAS call. |
| 232 | */ |
| 233 | target_ulong fwnmi_system_reset_addr; |
| 234 | target_ulong fwnmi_machine_check_addr; |
| 235 | |
| 236 | /* Machine Check FWNMI synchronization, fwnmi_machine_check_interlock is |
| 237 | * set to -1 if a FWNMI machine check is not in progress, else is set to |
| 238 | * the CPU that was delivered the machine check, and is set back to -1 |
| 239 | * when that CPU makes an "ibm,nmi-interlock" RTAS call. The cond is used |
| 240 | * to synchronize other CPUs. |
| 241 | */ |
| 242 | int fwnmi_machine_check_interlock; |
| 243 | QemuCond fwnmi_machine_check_interlock_cond; |
| 244 | |
| 245 | /* Set by -boot */ |
| 246 | char *boot_device; |
| 247 | |
| 248 | /*< public >*/ |
| 249 | char *kvm_type; |
| 250 | char *host_model; |
| 251 | char *host_serial; |
| 252 | |
| 253 | int32_t irq_map_nr; |
| 254 | unsigned long *irq_map; |
| 255 | SpaprIrq *irq; |
| 256 | qemu_irq *qirqs; |
| 257 | SpaprInterruptController *active_intc; |
| 258 | ICSState *ics; |
| 259 | SpaprXive *xive; |
| 260 | |
| 261 | bool cmd_line_caps[SPAPR_CAP_NUM]; |
| 262 | SpaprCapabilities def, eff, mig; |
| 263 | |
| 264 | SpaprTpmProxy *tpm_proxy; |
| 265 | |
| 266 | uint32_t FORM1_assoc_array[NUMA_NODES_MAX_NUM][FORM1_NUMA_ASSOC_SIZE]; |
| 267 | uint32_t FORM2_assoc_array[NUMA_NODES_MAX_NUM][FORM2_NUMA_ASSOC_SIZE]; |
| 268 | |
| 269 | Error *fwnmi_migration_blocker; |
| 270 | |
| 271 | SpaprWatchdog wds[WDT_MAX_WATCHDOGS]; |
| 272 | |
| 273 | /* Fadump State */ |
| 274 | bool fadump_registered; |
| 275 | bool fadump_dump_active; |
| 276 | FadumpMemStruct registered_fdm; |
| 277 | }; |
| 278 | |
| 279 | #define H_SUCCESS 0 |
| 280 | #define H_BUSY 1 /* Hardware busy -- retry later */ |
| 281 | #define H_CLOSED 2 /* Resource closed */ |
| 282 | #define H_NOT_AVAILABLE 3 |
| 283 | #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */ |
| 284 | #define H_PARTIAL 5 |
| 285 | #define H_IN_PROGRESS 14 /* Kind of like busy */ |
| 286 | #define H_PAGE_REGISTERED 15 |
| 287 | #define H_PARTIAL_STORE 16 |
| 288 | #define H_PENDING 17 /* returned from H_POLL_PENDING */ |
| 289 | #define H_CONTINUE 18 /* Returned from H_Join on success */ |
| 290 | #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */ |
| 291 | #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \ |
| 292 | is a good time to retry */ |
| 293 | #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \ |
| 294 | is a good time to retry */ |
| 295 | #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \ |
| 296 | is a good time to retry */ |
| 297 | #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \ |
| 298 | is a good time to retry */ |
| 299 | #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \ |
| 300 | is a good time to retry */ |
| 301 | #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \ |
| 302 | is a good time to retry */ |
| 303 | #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */ |
| 304 | #define H_HARDWARE -1 /* Hardware error */ |
| 305 | #define H_FUNCTION -2 /* Function not supported */ |
| 306 | #define H_PRIVILEGE -3 /* Caller not privileged */ |
| 307 | #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ |
| 308 | #define H_BAD_MODE -5 /* Illegal msr value */ |
| 309 | #define H_PTEG_FULL -6 /* PTEG is full */ |
| 310 | #define H_NOT_FOUND -7 /* PTE was not found" */ |
| 311 | #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */ |
| 312 | #define H_NO_MEM -9 |
| 313 | #define H_AUTHORITY -10 |
| 314 | #define H_PERMISSION -11 |
| 315 | #define H_DROPPED -12 |
| 316 | #define H_SOURCE_PARM -13 |
| 317 | #define H_DEST_PARM -14 |
| 318 | #define H_REMOTE_PARM -15 |
| 319 | #define H_RESOURCE -16 |
| 320 | #define H_ADAPTER_PARM -17 |
| 321 | #define H_RH_PARM -18 |
| 322 | #define H_RCQ_PARM -19 |
| 323 | #define H_SCQ_PARM -20 |
| 324 | #define H_EQ_PARM -21 |
| 325 | #define H_RT_PARM -22 |
| 326 | #define H_ST_PARM -23 |
| 327 | #define H_SIGT_PARM -24 |
| 328 | #define H_TOKEN_PARM -25 |
| 329 | #define H_MLENGTH_PARM -27 |
| 330 | #define H_MEM_PARM -28 |
| 331 | #define H_MEM_ACCESS_PARM -29 |
| 332 | #define H_ATTR_PARM -30 |
| 333 | #define H_PORT_PARM -31 |
| 334 | #define H_MCG_PARM -32 |
| 335 | #define H_VL_PARM -33 |
| 336 | #define H_TSIZE_PARM -34 |
| 337 | #define H_TRACE_PARM -35 |
| 338 | |
| 339 | #define H_MASK_PARM -37 |
| 340 | #define H_MCG_FULL -38 |
| 341 | #define H_ALIAS_EXIST -39 |
| 342 | #define H_P_COUNTER -40 |
| 343 | #define H_TABLE_FULL -41 |
| 344 | #define H_ALT_TABLE -42 |
| 345 | #define H_MR_CONDITION -43 |
| 346 | #define H_NOT_ENOUGH_RESOURCES -44 |
| 347 | #define H_R_STATE -45 |
| 348 | #define H_RESCINDEND -46 |
| 349 | #define H_P2 -55 |
| 350 | #define H_P3 -56 |
| 351 | #define H_P4 -57 |
| 352 | #define H_P5 -58 |
| 353 | #define H_P6 -59 |
| 354 | #define H_P7 -60 |
| 355 | #define H_P8 -61 |
| 356 | #define H_P9 -62 |
| 357 | #define H_NOOP -63 |
| 358 | #define H_UNSUPPORTED -67 |
| 359 | #define H_OVERLAP -68 |
| 360 | #define H_STATE -75 |
| 361 | #define H_IN_USE -77 |
| 362 | #define H_INVALID_ELEMENT_VALUE -81 |
| 363 | #define H_UNSUPPORTED_FLAG -256 |
| 364 | #define H_MULTI_THREADS_ACTIVE -9005 |
| 365 | |
| 366 | |
| 367 | /* Long Busy is a condition that can be returned by the firmware |
| 368 | * when a call cannot be completed now, but the identical call |
| 369 | * should be retried later. This prevents calls blocking in the |
| 370 | * firmware for long periods of time. Annoyingly the firmware can return |
| 371 | * a range of return codes, hinting at how long we should wait before |
| 372 | * retrying. If you don't care for the hint, the macro below is a good |
| 373 | * way to check for the long_busy return codes |
| 374 | */ |
| 375 | #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \ |
| 376 | && (x <= H_LONG_BUSY_END_RANGE)) |
| 377 | |
| 378 | /* Flags */ |
| 379 | #define H_LARGE_PAGE (1ULL<<(63-16)) |
| 380 | #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */ |
| 381 | #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */ |
| 382 | #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */ |
| 383 | #define H_PAGE_STATE_CHANGE (1ULL<<(63-28)) |
| 384 | #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30))) |
| 385 | #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED) |
| 386 | #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31))) |
| 387 | #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE |
| 388 | #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */ |
| 389 | #define H_ANDCOND (1ULL<<(63-33)) |
| 390 | #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */ |
| 391 | #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */ |
| 392 | #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */ |
| 393 | #define H_COPY_PAGE (1ULL<<(63-49)) |
| 394 | #define H_N (1ULL<<(63-61)) |
| 395 | #define H_PP1 (1ULL<<(63-62)) |
| 396 | #define H_PP2 (1ULL<<(63-63)) |
| 397 | |
| 398 | /* Values for 2nd argument to H_SET_MODE */ |
| 399 | #define H_SET_MODE_RESOURCE_SET_CIABR 1 |
| 400 | #define H_SET_MODE_RESOURCE_SET_DAWR0 2 |
| 401 | #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 |
| 402 | #define H_SET_MODE_RESOURCE_LE 4 |
| 403 | #define H_SET_MODE_RESOURCE_SET_DAWR1 5 |
| 404 | |
| 405 | /* Flags for H_SET_MODE_RESOURCE_LE */ |
| 406 | #define H_SET_MODE_ENDIAN_BIG 0 |
| 407 | #define H_SET_MODE_ENDIAN_LITTLE 1 |
| 408 | |
| 409 | /* VASI States */ |
| 410 | #define H_VASI_INVALID 0 |
| 411 | #define H_VASI_ENABLED 1 |
| 412 | #define H_VASI_ABORTED 2 |
| 413 | #define H_VASI_SUSPENDING 3 |
| 414 | #define H_VASI_SUSPENDED 4 |
| 415 | #define H_VASI_RESUMED 5 |
| 416 | #define H_VASI_COMPLETED 6 |
| 417 | |
| 418 | /* DABRX flags */ |
| 419 | #define H_DABRX_HYPERVISOR (1ULL<<(63-61)) |
| 420 | #define H_DABRX_KERNEL (1ULL<<(63-62)) |
| 421 | #define H_DABRX_USER (1ULL<<(63-63)) |
| 422 | |
| 423 | /* Values for KVM_PPC_GET_CPU_CHAR & H_GET_CPU_CHARACTERISTICS */ |
| 424 | #define H_CPU_CHAR_SPEC_BAR_ORI31 PPC_BIT(0) |
| 425 | #define H_CPU_CHAR_BCCTRL_SERIALISED PPC_BIT(1) |
| 426 | #define H_CPU_CHAR_L1D_FLUSH_ORI30 PPC_BIT(2) |
| 427 | #define H_CPU_CHAR_L1D_FLUSH_TRIG2 PPC_BIT(3) |
| 428 | #define H_CPU_CHAR_L1D_THREAD_PRIV PPC_BIT(4) |
| 429 | #define H_CPU_CHAR_HON_BRANCH_HINTS PPC_BIT(5) |
| 430 | #define H_CPU_CHAR_THR_RECONF_TRIG PPC_BIT(6) |
| 431 | #define H_CPU_CHAR_CACHE_COUNT_DIS PPC_BIT(7) |
| 432 | #define H_CPU_CHAR_BCCTR_FLUSH_ASSIST PPC_BIT(9) |
| 433 | |
| 434 | #define H_CPU_BEHAV_FAVOUR_SECURITY PPC_BIT(0) |
| 435 | #define H_CPU_BEHAV_L1D_FLUSH_PR PPC_BIT(1) |
| 436 | #define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR PPC_BIT(2) |
| 437 | #define H_CPU_BEHAV_FLUSH_COUNT_CACHE PPC_BIT(5) |
| 438 | #define H_CPU_BEHAV_NO_L1D_FLUSH_ENTRY PPC_BIT(7) |
| 439 | #define H_CPU_BEHAV_NO_L1D_FLUSH_UACCESS PPC_BIT(8) |
| 440 | |
| 441 | /* Each control block has to be on a 4K boundary */ |
| 442 | #define H_CB_ALIGNMENT 4096 |
| 443 | |
| 444 | /* pSeries hypervisor opcodes */ |
| 445 | #define H_REMOVE 0x04 |
| 446 | #define H_ENTER 0x08 |
| 447 | #define H_READ 0x0c |
| 448 | #define H_CLEAR_MOD 0x10 |
| 449 | #define H_CLEAR_REF 0x14 |
| 450 | #define H_PROTECT 0x18 |
| 451 | #define H_GET_TCE 0x1c |
| 452 | #define H_PUT_TCE 0x20 |
| 453 | #define H_SET_SPRG0 0x24 |
| 454 | #define H_SET_DABR 0x28 |
| 455 | #define H_PAGE_INIT 0x2c |
| 456 | #define H_SET_ASR 0x30 |
| 457 | #define H_ASR_ON 0x34 |
| 458 | #define H_ASR_OFF 0x38 |
| 459 | #define H_LOGICAL_CI_LOAD 0x3c |
| 460 | #define H_LOGICAL_CI_STORE 0x40 |
| 461 | #define H_LOGICAL_CACHE_LOAD 0x44 |
| 462 | #define H_LOGICAL_CACHE_STORE 0x48 |
| 463 | #define H_LOGICAL_ICBI 0x4c |
| 464 | #define H_LOGICAL_DCBF 0x50 |
| 465 | #define H_GET_TERM_CHAR 0x54 |
| 466 | #define H_PUT_TERM_CHAR 0x58 |
| 467 | #define H_REAL_TO_LOGICAL 0x5c |
| 468 | #define H_HYPERVISOR_DATA 0x60 |
| 469 | #define H_EOI 0x64 |
| 470 | #define H_CPPR 0x68 |
| 471 | #define H_IPI 0x6c |
| 472 | #define H_IPOLL 0x70 |
| 473 | #define H_XIRR 0x74 |
| 474 | #define H_PERFMON 0x7c |
| 475 | #define H_MIGRATE_DMA 0x78 |
| 476 | #define H_REGISTER_VPA 0xDC |
| 477 | #define H_CEDE 0xE0 |
| 478 | #define H_CONFER 0xE4 |
| 479 | #define H_PROD 0xE8 |
| 480 | #define H_GET_PPP 0xEC |
| 481 | #define H_SET_PPP 0xF0 |
| 482 | #define H_PURR 0xF4 |
| 483 | #define H_PIC 0xF8 |
| 484 | #define H_REG_CRQ 0xFC |
| 485 | #define H_FREE_CRQ 0x100 |
| 486 | #define H_VIO_SIGNAL 0x104 |
| 487 | #define H_SEND_CRQ 0x108 |
| 488 | #define H_COPY_RDMA 0x110 |
| 489 | #define H_REGISTER_LOGICAL_LAN 0x114 |
| 490 | #define H_FREE_LOGICAL_LAN 0x118 |
| 491 | #define H_ADD_LOGICAL_LAN_BUFFER 0x11C |
| 492 | #define H_SEND_LOGICAL_LAN 0x120 |
| 493 | #define H_BULK_REMOVE 0x124 |
| 494 | #define H_MULTICAST_CTRL 0x130 |
| 495 | #define H_SET_XDABR 0x134 |
| 496 | #define H_STUFF_TCE 0x138 |
| 497 | #define H_PUT_TCE_INDIRECT 0x13C |
| 498 | #define H_CHANGE_LOGICAL_LAN_MAC 0x14C |
| 499 | #define H_VTERM_PARTNER_INFO 0x150 |
| 500 | #define H_REGISTER_VTERM 0x154 |
| 501 | #define H_FREE_VTERM 0x158 |
| 502 | #define H_RESET_EVENTS 0x15C |
| 503 | #define H_ALLOC_RESOURCE 0x160 |
| 504 | #define H_FREE_RESOURCE 0x164 |
| 505 | #define H_MODIFY_QP 0x168 |
| 506 | #define H_QUERY_QP 0x16C |
| 507 | #define H_REREGISTER_PMR 0x170 |
| 508 | #define H_REGISTER_SMR 0x174 |
| 509 | #define H_QUERY_MR 0x178 |
| 510 | #define H_QUERY_MW 0x17C |
| 511 | #define H_QUERY_HCA 0x180 |
| 512 | #define H_QUERY_PORT 0x184 |
| 513 | #define H_MODIFY_PORT 0x188 |
| 514 | #define H_DEFINE_AQP1 0x18C |
| 515 | #define H_GET_TRACE_BUFFER 0x190 |
| 516 | #define H_DEFINE_AQP0 0x194 |
| 517 | #define H_RESIZE_MR 0x198 |
| 518 | #define H_ATTACH_MCQP 0x19C |
| 519 | #define H_DETACH_MCQP 0x1A0 |
| 520 | #define H_CREATE_RPT 0x1A4 |
| 521 | #define H_REMOVE_RPT 0x1A8 |
| 522 | #define H_REGISTER_RPAGES 0x1AC |
| 523 | #define H_DISABLE_AND_GETC 0x1B0 |
| 524 | #define H_ERROR_DATA 0x1B4 |
| 525 | #define H_GET_HCA_INFO 0x1B8 |
| 526 | #define H_GET_PERF_COUNT 0x1BC |
| 527 | #define H_MANAGE_TRACE 0x1C0 |
| 528 | #define H_GET_CPU_CHARACTERISTICS 0x1C8 |
| 529 | #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4 |
| 530 | #define H_QUERY_INT_STATE 0x1E4 |
| 531 | #define H_POLL_PENDING 0x1D8 |
| 532 | #define H_ILLAN_ATTRIBUTES 0x244 |
| 533 | #define H_MODIFY_HEA_QP 0x250 |
| 534 | #define H_QUERY_HEA_QP 0x254 |
| 535 | #define H_QUERY_HEA 0x258 |
| 536 | #define H_QUERY_HEA_PORT 0x25C |
| 537 | #define H_MODIFY_HEA_PORT 0x260 |
| 538 | #define H_REG_BCMC 0x264 |
| 539 | #define H_DEREG_BCMC 0x268 |
| 540 | #define H_REGISTER_HEA_RPAGES 0x26C |
| 541 | #define H_DISABLE_AND_GET_HEA 0x270 |
| 542 | #define H_GET_HEA_INFO 0x274 |
| 543 | #define H_ALLOC_HEA_RESOURCE 0x278 |
| 544 | #define H_ADD_CONN 0x284 |
| 545 | #define H_DEL_CONN 0x288 |
| 546 | #define H_JOIN 0x298 |
| 547 | #define H_VASI_STATE 0x2A4 |
| 548 | #define H_ENABLE_CRQ 0x2B0 |
| 549 | #define H_GET_EM_PARMS 0x2B8 |
| 550 | #define H_SET_MPP 0x2D0 |
| 551 | #define H_GET_MPP 0x2D4 |
| 552 | #define H_HOME_NODE_ASSOCIATIVITY 0x2EC |
| 553 | #define H_XIRR_X 0x2FC |
| 554 | #define H_RANDOM 0x300 |
| 555 | #define H_SET_MODE 0x31C |
| 556 | #define H_RESIZE_HPT_PREPARE 0x36C |
| 557 | #define H_RESIZE_HPT_COMMIT 0x370 |
| 558 | #define H_CLEAN_SLB 0x374 |
| 559 | #define H_INVALIDATE_PID 0x378 |
| 560 | #define H_REGISTER_PROC_TBL 0x37C |
| 561 | #define H_SIGNAL_SYS_RESET 0x380 |
| 562 | |
| 563 | #define H_INT_GET_SOURCE_INFO 0x3A8 |
| 564 | #define H_INT_SET_SOURCE_CONFIG 0x3AC |
| 565 | #define H_INT_GET_SOURCE_CONFIG 0x3B0 |
| 566 | #define H_INT_GET_QUEUE_INFO 0x3B4 |
| 567 | #define H_INT_SET_QUEUE_CONFIG 0x3B8 |
| 568 | #define H_INT_GET_QUEUE_CONFIG 0x3BC |
| 569 | #define H_INT_SET_OS_REPORTING_LINE 0x3C0 |
| 570 | #define H_INT_GET_OS_REPORTING_LINE 0x3C4 |
| 571 | #define H_INT_ESB 0x3C8 |
| 572 | #define H_INT_SYNC 0x3CC |
| 573 | #define H_INT_RESET 0x3D0 |
| 574 | #define H_SCM_READ_METADATA 0x3E4 |
| 575 | #define H_SCM_WRITE_METADATA 0x3E8 |
| 576 | #define H_SCM_BIND_MEM 0x3EC |
| 577 | #define H_SCM_UNBIND_MEM 0x3F0 |
| 578 | #define H_SCM_UNBIND_ALL 0x3FC |
| 579 | #define H_SCM_HEALTH 0x400 |
| 580 | #define H_RPT_INVALIDATE 0x448 |
| 581 | #define H_SCM_FLUSH 0x44C |
| 582 | #define H_WATCHDOG 0x45C |
| 583 | #define H_GUEST_GET_CAPABILITIES 0x460 |
| 584 | #define H_GUEST_SET_CAPABILITIES 0x464 |
| 585 | #define H_GUEST_CREATE 0x470 |
| 586 | #define H_GUEST_CREATE_VCPU 0x474 |
| 587 | #define H_GUEST_GET_STATE 0x478 |
| 588 | #define H_GUEST_SET_STATE 0x47C |
| 589 | #define H_GUEST_RUN_VCPU 0x480 |
| 590 | #define H_GUEST_DELETE 0x488 |
| 591 | |
| 592 | #define MAX_HCALL_OPCODE H_GUEST_DELETE |
| 593 | |
| 594 | /* The hcalls above are standardized in PAPR and implemented by pHyp |
| 595 | * as well. |
| 596 | * |
| 597 | * We also need some hcalls which are specific to qemu / KVM-on-POWER. |
| 598 | * We put those into the 0xf000-0xfffc range which is reserved by PAPR |
| 599 | * for "platform-specific" hcalls. |
| 600 | */ |
| 601 | #define KVMPPC_HCALL_BASE 0xf000 |
| 602 | #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) |
| 603 | #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1) |
| 604 | /* Client Architecture support */ |
| 605 | #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2) |
| 606 | #define KVMPPC_H_UPDATE_DT (KVMPPC_HCALL_BASE + 0x3) |
| 607 | /* 0x4 was used for KVMPPC_H_UPDATE_PHANDLE in SLOF */ |
| 608 | #define KVMPPC_H_VOF_CLIENT (KVMPPC_HCALL_BASE + 0x5) |
| 609 | |
| 610 | /* Platform-specific hcalls used for nested HV KVM */ |
| 611 | #define KVMPPC_H_SET_PARTITION_TABLE (KVMPPC_HCALL_BASE + 0x800) |
| 612 | #define KVMPPC_H_ENTER_NESTED (KVMPPC_HCALL_BASE + 0x804) |
| 613 | #define KVMPPC_H_TLB_INVALIDATE (KVMPPC_HCALL_BASE + 0x808) |
| 614 | #define KVMPPC_H_COPY_TOFROM_GUEST (KVMPPC_HCALL_BASE + 0x80C) |
| 615 | |
| 616 | #define KVMPPC_HCALL_MAX KVMPPC_H_COPY_TOFROM_GUEST |
| 617 | |
| 618 | /* |
| 619 | * The hcall range 0xEF00 to 0xEF80 is reserved for use in facilitating |
| 620 | * Secure VM mode via an Ultravisor / Protected Execution Facility |
| 621 | */ |
| 622 | #define SVM_HCALL_BASE 0xEF00 |
| 623 | #define SVM_H_TPM_COMM 0xEF10 |
| 624 | #define SVM_HCALL_MAX SVM_H_TPM_COMM |
| 625 | |
| 626 | typedef struct SpaprDeviceTreeUpdateHeader { |
| 627 | uint32_t version_id; |
| 628 | } SpaprDeviceTreeUpdateHeader; |
| 629 | |
| 630 | #define hcall_dprintf(fmt, ...) \ |
| 631 | do { \ |
| 632 | qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \ |
| 633 | } while (0) |
| 634 | |
| 635 | typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, SpaprMachineState *sm, |
| 636 | target_ulong opcode, |
| 637 | target_ulong *args); |
| 638 | |
| 639 | void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); |
| 640 | void spapr_unregister_hypercall(target_ulong opcode); |
| 641 | target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, |
| 642 | target_ulong *args); |
| 643 | |
| 644 | target_ulong vhyp_mmu_resize_hpt_prepare(PowerPCCPU *cpu, |
| 645 | SpaprMachineState *spapr, |
| 646 | target_ulong shift); |
| 647 | target_ulong vhyp_mmu_resize_hpt_commit(PowerPCCPU *cpu, |
| 648 | SpaprMachineState *spapr, |
| 649 | target_ulong flags, |
| 650 | target_ulong shift); |
| 651 | bool is_ram_address(SpaprMachineState *spapr, hwaddr addr); |
| 652 | void push_sregs_to_kvm_pr(SpaprMachineState *spapr); |
| 653 | |
| 654 | /* Virtual Processor Area structure constants */ |
| 655 | #define VPA_MIN_SIZE 640 |
| 656 | #define VPA_SIZE_OFFSET 0x4 |
| 657 | #define VPA_SHARED_PROC_OFFSET 0x9 |
| 658 | #define VPA_SHARED_PROC_VAL 0x2 |
| 659 | #define VPA_DISPATCH_COUNTER 0x100 |
| 660 | |
| 661 | /* ibm,set-eeh-option */ |
| 662 | #define RTAS_EEH_DISABLE 0 |
| 663 | #define RTAS_EEH_ENABLE 1 |
| 664 | #define RTAS_EEH_THAW_IO 2 |
| 665 | #define RTAS_EEH_THAW_DMA 3 |
| 666 | |
| 667 | /* ibm,get-config-addr-info2 */ |
| 668 | #define RTAS_GET_PE_ADDR 0 |
| 669 | #define RTAS_GET_PE_MODE 1 |
| 670 | #define RTAS_PE_MODE_NONE 0 |
| 671 | #define RTAS_PE_MODE_NOT_SHARED 1 |
| 672 | #define RTAS_PE_MODE_SHARED 2 |
| 673 | |
| 674 | /* ibm,read-slot-reset-state2 */ |
| 675 | #define RTAS_EEH_PE_STATE_NORMAL 0 |
| 676 | #define RTAS_EEH_PE_STATE_RESET 1 |
| 677 | #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2 |
| 678 | #define RTAS_EEH_PE_STATE_STOPPED_DMA 4 |
| 679 | #define RTAS_EEH_PE_STATE_UNAVAIL 5 |
| 680 | #define RTAS_EEH_NOT_SUPPORT 0 |
| 681 | #define RTAS_EEH_SUPPORT 1 |
| 682 | #define RTAS_EEH_PE_UNAVAIL_INFO 1000 |
| 683 | #define RTAS_EEH_PE_RECOVER_INFO 0 |
| 684 | |
| 685 | /* ibm,set-slot-reset */ |
| 686 | #define RTAS_SLOT_RESET_DEACTIVATE 0 |
| 687 | #define RTAS_SLOT_RESET_HOT 1 |
| 688 | #define RTAS_SLOT_RESET_FUNDAMENTAL 3 |
| 689 | |
| 690 | /* ibm,slot-error-detail */ |
| 691 | #define RTAS_SLOT_TEMP_ERR_LOG 1 |
| 692 | #define RTAS_SLOT_PERM_ERR_LOG 2 |
| 693 | |
| 694 | /* RTAS return codes */ |
| 695 | #define RTAS_OUT_SUCCESS 0 |
| 696 | #define RTAS_OUT_NO_ERRORS_FOUND 1 |
| 697 | #define RTAS_OUT_HW_ERROR -1 |
| 698 | #define RTAS_OUT_BUSY -2 |
| 699 | #define RTAS_OUT_PARAM_ERROR -3 |
| 700 | #define RTAS_OUT_NOT_SUPPORTED -3 |
| 701 | #define RTAS_OUT_NO_SUCH_INDICATOR -3 |
| 702 | #define RTAS_OUT_DUMP_ALREADY_REGISTERED -9 |
| 703 | #define RTAS_OUT_DUMP_ACTIVE -10 |
| 704 | #define RTAS_OUT_NOT_AUTHORIZED -9002 |
| 705 | #define RTAS_OUT_SYSPARM_PARAM_ERROR -9999 |
| 706 | |
| 707 | /* DDW pagesize mask values from ibm,query-pe-dma-window */ |
| 708 | #define RTAS_DDW_PGSIZE_4K 0x01 |
| 709 | #define RTAS_DDW_PGSIZE_64K 0x02 |
| 710 | #define RTAS_DDW_PGSIZE_16M 0x04 |
| 711 | #define RTAS_DDW_PGSIZE_32M 0x08 |
| 712 | #define RTAS_DDW_PGSIZE_64M 0x10 |
| 713 | #define RTAS_DDW_PGSIZE_128M 0x20 |
| 714 | #define RTAS_DDW_PGSIZE_256M 0x40 |
| 715 | #define RTAS_DDW_PGSIZE_16G 0x80 |
| 716 | #define RTAS_DDW_PGSIZE_2M 0x100 |
| 717 | |
| 718 | /* RTAS tokens */ |
| 719 | #define RTAS_TOKEN_BASE 0x2000 |
| 720 | |
| 721 | #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00) |
| 722 | #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01) |
| 723 | #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02) |
| 724 | #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03) |
| 725 | #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04) |
| 726 | #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05) |
| 727 | #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06) |
| 728 | #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07) |
| 729 | #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08) |
| 730 | #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09) |
| 731 | #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A) |
| 732 | #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B) |
| 733 | #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C) |
| 734 | #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D) |
| 735 | #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E) |
| 736 | #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F) |
| 737 | #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10) |
| 738 | #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11) |
| 739 | #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12) |
| 740 | #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13) |
| 741 | #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14) |
| 742 | #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15) |
| 743 | #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16) |
| 744 | #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17) |
| 745 | #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18) |
| 746 | #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19) |
| 747 | #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A) |
| 748 | #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B) |
| 749 | #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C) |
| 750 | #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D) |
| 751 | #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E) |
| 752 | #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F) |
| 753 | #define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20) |
| 754 | #define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21) |
| 755 | #define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22) |
| 756 | #define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23) |
| 757 | #define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24) |
| 758 | #define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25) |
| 759 | #define RTAS_IBM_QUERY_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x26) |
| 760 | #define RTAS_IBM_CREATE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x27) |
| 761 | #define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28) |
| 762 | #define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29) |
| 763 | #define RTAS_IBM_SUSPEND_ME (RTAS_TOKEN_BASE + 0x2A) |
| 764 | #define RTAS_IBM_NMI_REGISTER (RTAS_TOKEN_BASE + 0x2B) |
| 765 | #define RTAS_IBM_NMI_INTERLOCK (RTAS_TOKEN_BASE + 0x2C) |
| 766 | #define RTAS_CONFIGURE_KERNEL_DUMP (RTAS_TOKEN_BASE + 0x2D) |
| 767 | |
| 768 | #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2E) |
| 769 | |
| 770 | /* RTAS ibm,get-system-parameter token values */ |
| 771 | #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 |
| 772 | #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42 |
| 773 | #define RTAS_SYSPARM_UUID 48 |
| 774 | |
| 775 | /* RTAS indicator/sensor types |
| 776 | * |
| 777 | * as defined by PAPR+ 2.7 7.3.5.4, Table 41 |
| 778 | * |
| 779 | * NOTE: currently only DR-related sensors are implemented here |
| 780 | */ |
| 781 | #define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001 |
| 782 | #define RTAS_SENSOR_TYPE_DR 9002 |
| 783 | #define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003 |
| 784 | #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE |
| 785 | |
| 786 | /* Possible values for the platform-processor-diagnostics-run-mode parameter |
| 787 | * of the RTAS ibm,get-system-parameter call. |
| 788 | */ |
| 789 | #define DIAGNOSTICS_RUN_MODE_DISABLED 0 |
| 790 | #define DIAGNOSTICS_RUN_MODE_STAGGERED 1 |
| 791 | #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2 |
| 792 | #define DIAGNOSTICS_RUN_MODE_PERIODIC 3 |
| 793 | |
| 794 | static inline uint64_t ppc64_phys_to_real(uint64_t addr) |
| 795 | { |
| 796 | return addr & ~0xF000000000000000ULL; |
| 797 | } |
| 798 | |
| 799 | uint32_t rtas_ld(target_ulong phys, int n); |
| 800 | uint64_t rtas_ldq(target_ulong phys, int n); |
| 801 | void rtas_st(target_ulong phys, int n, uint32_t val); |
| 802 | |
| 803 | typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, SpaprMachineState *sm, |
| 804 | uint32_t token, |
| 805 | uint32_t nargs, target_ulong args, |
| 806 | uint32_t nret, target_ulong rets); |
| 807 | void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn); |
| 808 | target_ulong spapr_rtas_call(PowerPCCPU *cpu, SpaprMachineState *sm, |
| 809 | uint32_t token, uint32_t nargs, target_ulong args, |
| 810 | uint32_t nret, target_ulong rets); |
| 811 | void spapr_dt_rtas_tokens(void *fdt, int rtas); |
| 812 | void spapr_load_rtas(SpaprMachineState *spapr, void *fdt, hwaddr addr); |
| 813 | |
| 814 | #define SPAPR_TCE_PAGE_SHIFT 12 |
| 815 | #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT) |
| 816 | #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1) |
| 817 | |
| 818 | #define SPAPR_VIO_BASE_LIOBN 0x00000000 |
| 819 | #define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg)) |
| 820 | #define SPAPR_PCI_LIOBN(phb_index, window_num) \ |
| 821 | (0x80000000 | ((phb_index) << 8) | (window_num)) |
| 822 | #define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000)) |
| 823 | #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff) |
| 824 | |
| 825 | #define RTAS_MIN_SIZE 20 /* hv_rtas_size in SLOF */ |
| 826 | #define RTAS_ERROR_LOG_MAX 2048 |
| 827 | |
| 828 | /* Offset from rtas-base where error log is placed */ |
| 829 | #define RTAS_ERROR_LOG_OFFSET 0x30 |
| 830 | |
| 831 | #define RTAS_EVENT_SCAN_RATE 1 |
| 832 | |
| 833 | /* This helper should be used to encode interrupt specifiers when the related |
| 834 | * "interrupt-controller" node has its "#interrupt-cells" property set to 2 (ie, |
| 835 | * VIO devices, RTAS event sources and PHBs). |
| 836 | */ |
| 837 | static inline void spapr_dt_irq(uint32_t *intspec, int irq, bool is_lsi) |
| 838 | { |
| 839 | intspec[0] = cpu_to_be32(irq); |
| 840 | intspec[1] = is_lsi ? cpu_to_be32(1) : 0; |
| 841 | } |
| 842 | |
| 843 | |
| 844 | #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" |
| 845 | OBJECT_DECLARE_SIMPLE_TYPE(SpaprTceTable, SPAPR_TCE_TABLE) |
| 846 | |
| 847 | #define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region" |
| 848 | DECLARE_INSTANCE_CHECKER(IOMMUMemoryRegion, SPAPR_IOMMU_MEMORY_REGION, |
| 849 | TYPE_SPAPR_IOMMU_MEMORY_REGION) |
| 850 | |
| 851 | struct SpaprTceTable { |
| 852 | DeviceState parent; |
| 853 | uint32_t liobn; |
| 854 | uint32_t nb_table; |
| 855 | uint64_t bus_offset; |
| 856 | uint32_t page_shift; |
| 857 | uint64_t *table; |
| 858 | uint32_t mig_nb_table; |
| 859 | uint64_t *mig_table; |
| 860 | bool bypass; |
| 861 | bool need_vfio; |
| 862 | bool skipping_replay; |
| 863 | bool def_win; |
| 864 | int fd; |
| 865 | MemoryRegion root; |
| 866 | IOMMUMemoryRegion iommu; |
| 867 | struct SpaprVioDevice *vdev; /* for @bypass migration compatibility only */ |
| 868 | QLIST_ENTRY(SpaprTceTable) list; |
| 869 | }; |
| 870 | |
| 871 | SpaprTceTable *spapr_tce_find_by_liobn(target_ulong liobn); |
| 872 | |
| 873 | struct SpaprEventLogEntry { |
| 874 | uint32_t summary; |
| 875 | uint32_t extended_length; |
| 876 | void *extended_log; |
| 877 | QTAILQ_ENTRY(SpaprEventLogEntry) next; |
| 878 | }; |
| 879 | |
| 880 | void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space); |
| 881 | void spapr_events_init(SpaprMachineState *sm); |
| 882 | void spapr_dt_events(SpaprMachineState *sm, void *fdt); |
| 883 | void close_htab_fd(SpaprMachineState *spapr); |
| 884 | void spapr_setup_hpt(SpaprMachineState *spapr); |
| 885 | void spapr_free_hpt(SpaprMachineState *spapr); |
| 886 | void spapr_check_mmu_mode(bool guest_radix); |
| 887 | SpaprTceTable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn); |
| 888 | void spapr_tce_table_enable(SpaprTceTable *tcet, |
| 889 | uint32_t page_shift, uint64_t bus_offset, |
| 890 | uint32_t nb_table); |
| 891 | void spapr_tce_table_disable(SpaprTceTable *tcet); |
| 892 | void spapr_tce_set_need_vfio(SpaprTceTable *tcet, bool need_vfio); |
| 893 | |
| 894 | MemoryRegion *spapr_tce_get_iommu(SpaprTceTable *tcet); |
| 895 | int spapr_dma_dt(void *fdt, int node_off, const char *propname, |
| 896 | uint32_t liobn, uint64_t window, uint32_t size); |
| 897 | int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, |
| 898 | SpaprTceTable *tcet); |
| 899 | void spapr_pci_switch_vga(SpaprMachineState *spapr, bool big_endian); |
| 900 | void spapr_hotplug_req_add_by_index(SpaprDrc *drc); |
| 901 | void spapr_hotplug_req_remove_by_index(SpaprDrc *drc); |
| 902 | void spapr_hotplug_req_add_by_count(SpaprDrcType drc_type, |
| 903 | uint32_t count); |
| 904 | void spapr_hotplug_req_remove_by_count(SpaprDrcType drc_type, |
| 905 | uint32_t count); |
| 906 | void spapr_hotplug_req_add_by_count_indexed(SpaprDrcType drc_type, |
| 907 | uint32_t count, uint32_t index); |
| 908 | void spapr_hotplug_req_remove_by_count_indexed(SpaprDrcType drc_type, |
| 909 | uint32_t count, uint32_t index); |
| 910 | int spapr_hpt_shift_for_ramsize(uint64_t ramsize); |
| 911 | int spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, Error **errp); |
| 912 | void spapr_clear_pending_events(SpaprMachineState *spapr); |
| 913 | void spapr_clear_pending_hotplug_events(SpaprMachineState *spapr); |
| 914 | void spapr_memory_unplug_rollback(SpaprMachineState *spapr, DeviceState *dev); |
| 915 | int spapr_max_server_number(SpaprMachineState *spapr); |
| 916 | void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, |
| 917 | uint64_t pte0, uint64_t pte1); |
| 918 | void spapr_mce_req_event(PowerPCCPU *cpu, bool recovered); |
| 919 | |
| 920 | /* DRC callbacks. */ |
| 921 | void spapr_core_release(DeviceState *dev); |
| 922 | int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, |
| 923 | void *fdt, int *fdt_start_offset, Error **errp); |
| 924 | void spapr_lmb_release(DeviceState *dev); |
| 925 | int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, |
| 926 | void *fdt, int *fdt_start_offset, Error **errp); |
| 927 | void spapr_phb_release(DeviceState *dev); |
| 928 | int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, |
| 929 | void *fdt, int *fdt_start_offset, Error **errp); |
| 930 | |
| 931 | void spapr_rtc_read(SpaprRtcState *rtc, struct tm *tm, uint32_t *ns); |
| 932 | int spapr_rtc_import_offset(SpaprRtcState *rtc, int64_t legacy_offset); |
| 933 | |
| 934 | #define TYPE_SPAPR_RNG "spapr-rng" |
| 935 | |
| 936 | #define SPAPR_MEMORY_BLOCK_SIZE ((hwaddr)1 << 28) /* 256MB */ |
| 937 | |
| 938 | /* 1GB alignment for hotplug memory region */ |
| 939 | #define SPAPR_DEVICE_MEM_ALIGN (1 * GiB) |
| 940 | |
| 941 | /* |
| 942 | * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory |
| 943 | * property under ibm,dynamic-reconfiguration-memory node. |
| 944 | */ |
| 945 | #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6 |
| 946 | |
| 947 | /* |
| 948 | * Defines for flag value in ibm,dynamic-memory property under |
| 949 | * ibm,dynamic-reconfiguration-memory node. |
| 950 | */ |
| 951 | #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008 |
| 952 | #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020 |
| 953 | #define SPAPR_LMB_FLAGS_RESERVED 0x00000080 |
| 954 | #define SPAPR_LMB_FLAGS_HOTREMOVABLE 0x00000100 |
| 955 | |
| 956 | void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg); |
| 957 | |
| 958 | #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) |
| 959 | |
| 960 | int spapr_get_vcpu_id(PowerPCCPU *cpu); |
| 961 | bool spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp); |
| 962 | PowerPCCPU *spapr_find_cpu(int vcpu_id); |
| 963 | |
| 964 | int spapr_caps_pre_load(void *opaque); |
| 965 | int spapr_caps_pre_save(void *opaque); |
| 966 | |
| 967 | /* |
| 968 | * Handling of optional capabilities |
| 969 | */ |
| 970 | extern const VMStateDescription vmstate_spapr_cap_htm; |
| 971 | extern const VMStateDescription vmstate_spapr_cap_vsx; |
| 972 | extern const VMStateDescription vmstate_spapr_cap_dfp; |
| 973 | extern const VMStateDescription vmstate_spapr_cap_cfpc; |
| 974 | extern const VMStateDescription vmstate_spapr_cap_sbbc; |
| 975 | extern const VMStateDescription vmstate_spapr_cap_ibs; |
| 976 | extern const VMStateDescription vmstate_spapr_cap_hpt_maxpagesize; |
| 977 | extern const VMStateDescription vmstate_spapr_cap_nested_kvm_hv; |
| 978 | extern const VMStateDescription vmstate_spapr_cap_nested_papr; |
| 979 | extern const VMStateDescription vmstate_spapr_cap_large_decr; |
| 980 | extern const VMStateDescription vmstate_spapr_cap_ccf_assist; |
| 981 | extern const VMStateDescription vmstate_spapr_cap_fwnmi; |
| 982 | extern const VMStateDescription vmstate_spapr_cap_rpt_invalidate; |
| 983 | extern const VMStateDescription vmstate_spapr_cap_ail_mode_3; |
| 984 | extern const VMStateDescription vmstate_spapr_wdt; |
| 985 | extern const VMStateDescription vmstate_spapr_cap_dawr1; |
| 986 | |
| 987 | static inline uint8_t spapr_get_cap(SpaprMachineState *spapr, int cap) |
| 988 | { |
| 989 | return spapr->eff.caps[cap]; |
| 990 | } |
| 991 | |
| 992 | void spapr_caps_init(SpaprMachineState *spapr); |
| 993 | void spapr_caps_apply(SpaprMachineState *spapr); |
| 994 | void spapr_caps_cpu_apply(SpaprMachineState *spapr, PowerPCCPU *cpu); |
| 995 | void spapr_caps_add_properties(SpaprMachineClass *smc); |
| 996 | int spapr_caps_post_migration(SpaprMachineState *spapr); |
| 997 | |
| 998 | bool spapr_check_pagesize(SpaprMachineState *spapr, hwaddr pagesize, |
| 999 | Error **errp); |
| 1000 | /* |
| 1001 | * XIVE definitions |
| 1002 | */ |
| 1003 | #define SPAPR_OV5_XIVE_LEGACY 0x0 |
| 1004 | #define SPAPR_OV5_XIVE_EXPLOIT 0x40 |
| 1005 | #define SPAPR_OV5_XIVE_BOTH 0x80 /* Only to advertise on the platform */ |
| 1006 | |
| 1007 | void spapr_set_all_lpcrs(target_ulong value, target_ulong mask); |
| 1008 | void spapr_init_all_lpcrs(target_ulong value, target_ulong mask); |
| 1009 | hwaddr spapr_get_rtas_addr(void); |
| 1010 | bool spapr_memory_hot_unplug_supported(SpaprMachineState *spapr); |
| 1011 | |
| 1012 | void spapr_vof_reset(SpaprMachineState *spapr, void *fdt, Error **errp); |
| 1013 | void spapr_vof_quiesce(MachineState *ms); |
| 1014 | bool spapr_vof_setprop(MachineState *ms, const char *path, const char *propname, |
| 1015 | void *val, int vallen); |
| 1016 | target_ulong spapr_h_vof_client(PowerPCCPU *cpu, SpaprMachineState *spapr, |
| 1017 | target_ulong opcode, target_ulong *args); |
| 1018 | target_ulong spapr_vof_client_architecture_support(MachineState *ms, |
| 1019 | CPUState *cs, |
| 1020 | target_ulong ovec_addr); |
| 1021 | void spapr_vof_client_dt_finalize(SpaprMachineState *spapr, void *fdt); |
| 1022 | |
| 1023 | /* H_WATCHDOG */ |
| 1024 | void spapr_watchdog_init(SpaprMachineState *spapr); |
| 1025 | void spapr_register_nested_hv(void); |
| 1026 | void spapr_unregister_nested_hv(void); |
| 1027 | void spapr_nested_reset(SpaprMachineState *spapr); |
| 1028 | void spapr_register_nested_papr(void); |
| 1029 | void spapr_unregister_nested_papr(void); |
| 1030 | |
| 1031 | #endif /* HW_SPAPR_H */ |