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1 /*
2 * QEMU PowerPC sPAPR IRQ backend definitions
3 *
4 * Copyright (c) 2018, IBM Corporation.
5 *
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
8 */
9
10 #ifndef HW_SPAPR_IRQ_H
11 #define HW_SPAPR_IRQ_H
12
13 #include "target/ppc/cpu-qom.h"
14 #include "qom/object.h"
15
16 /*
17 * The XIVE IRQ backend uses the same layout as the XICS backend but
18 * covers the full range of the IRQ number space. The IRQ numbers for
19 * the CPU IPIs are allocated at the bottom of this space, below 4K,
20 * to preserve compatibility with XICS which does not use that range.
21 */
22
23 /*
24 * CPU IPI range (XIVE only)
25 */
26 #define SPAPR_IRQ_IPI 0x0
27 #define SPAPR_IRQ_NR_IPIS 0x1000
28
29 /*
30 * IRQ range offsets per device type
31 */
32
33 #define SPAPR_XIRQ_BASE XICS_IRQ_BASE /* 0x1000 */
34 #define SPAPR_IRQ_EPOW (SPAPR_XIRQ_BASE + 0x0000)
35 #define SPAPR_IRQ_HOTPLUG (SPAPR_XIRQ_BASE + 0x0001)
36 #define SPAPR_IRQ_VIO (SPAPR_XIRQ_BASE + 0x0100) /* 256 VIO devices */
37 #define SPAPR_IRQ_PCI_LSI (SPAPR_XIRQ_BASE + 0x0200) /* 32+ PHBs devices */
38
39 /* Offset of the dynamic range covered by the bitmap allocator */
40 #define SPAPR_IRQ_MSI (SPAPR_XIRQ_BASE + 0x0300)
41
42 #define SPAPR_NR_XIRQS 0x1000
43 #define SPAPR_IRQ_NR_MSIS (SPAPR_XIRQ_BASE + SPAPR_NR_XIRQS - SPAPR_IRQ_MSI)
44
45 struct SpaprMachineState;
46
47 typedef struct SpaprInterruptController SpaprInterruptController;
48
49 #define TYPE_SPAPR_INTC "spapr-interrupt-controller"
50 #define SPAPR_INTC(obj) \
51 INTERFACE_CHECK(SpaprInterruptController, (obj), TYPE_SPAPR_INTC)
52 typedef struct SpaprInterruptControllerClass SpaprInterruptControllerClass;
53 DECLARE_CLASS_CHECKERS(SpaprInterruptControllerClass, SPAPR_INTC,
54 TYPE_SPAPR_INTC)
55
56 struct SpaprInterruptControllerClass {
57 InterfaceClass parent;
58
59 int (*activate)(SpaprInterruptController *intc, uint32_t nr_servers,
60 Error **errp);
61 void (*deactivate)(SpaprInterruptController *intc);
62
63 /*
64 * These methods will typically be called on all intcs, active and
65 * inactive
66 */
67 int (*cpu_intc_create)(SpaprInterruptController *intc,
68 PowerPCCPU *cpu, Error **errp);
69 void (*cpu_intc_reset)(SpaprInterruptController *intc, PowerPCCPU *cpu);
70 void (*cpu_intc_destroy)(SpaprInterruptController *intc, PowerPCCPU *cpu);
71 int (*claim_irq)(SpaprInterruptController *intc, int irq, bool lsi,
72 Error **errp);
73 void (*free_irq)(SpaprInterruptController *intc, int irq);
74
75 /* These methods should only be called on the active intc */
76 void (*set_irq)(SpaprInterruptController *intc, int irq, int val);
77 void (*print_info)(SpaprInterruptController *intc, GString *buf);
78 void (*dt)(SpaprInterruptController *intc, uint32_t nr_servers,
79 void *fdt, uint32_t phandle);
80 int (*post_load)(SpaprInterruptController *intc, int version_id);
81 };
82
83 void spapr_irq_update_active_intc(struct SpaprMachineState *spapr);
84
85 int spapr_irq_cpu_intc_create(struct SpaprMachineState *spapr,
86 PowerPCCPU *cpu, Error **errp);
87 void spapr_irq_cpu_intc_reset(struct SpaprMachineState *spapr, PowerPCCPU *cpu);
88 void spapr_irq_cpu_intc_destroy(struct SpaprMachineState *spapr, PowerPCCPU *cpu);
89 void spapr_irq_print_info(struct SpaprMachineState *spapr, GString *buf);
90 void spapr_irq_dt(struct SpaprMachineState *spapr, uint32_t nr_servers,
91 void *fdt, uint32_t phandle);
92
93 int spapr_irq_msi_alloc(struct SpaprMachineState *spapr, uint32_t num, bool align,
94 Error **errp);
95 void spapr_irq_msi_free(struct SpaprMachineState *spapr, int irq, uint32_t num);
96
97 typedef struct SpaprIrq {
98 bool xics;
99 bool xive;
100 } SpaprIrq;
101
102 extern SpaprIrq spapr_irq_xics;
103 extern SpaprIrq spapr_irq_xive;
104 extern SpaprIrq spapr_irq_dual;
105
106 void spapr_irq_init(struct SpaprMachineState *spapr, Error **errp);
107 int spapr_irq_claim(struct SpaprMachineState *spapr, int irq, bool lsi, Error **errp);
108 void spapr_irq_free(struct SpaprMachineState *spapr, int irq, int num);
109 qemu_irq spapr_qirq(struct SpaprMachineState *spapr, int irq);
110 int spapr_irq_post_load(struct SpaprMachineState *spapr, int version_id);
111 void spapr_irq_reset(struct SpaprMachineState *spapr, Error **errp);
112 int spapr_irq_get_phandle(struct SpaprMachineState *spapr, void *fdt, Error **errp);
113
114 typedef int (*SpaprInterruptControllerInitKvm)(SpaprInterruptController *,
115 uint32_t, Error **);
116
117 int spapr_irq_init_kvm(SpaprInterruptControllerInitKvm fn,
118 SpaprInterruptController *intc,
119 uint32_t nr_servers,
120 Error **errp);
121
122 /*
123 * XICS legacy routines
124 */
125 int spapr_irq_find(struct SpaprMachineState *spapr, int num, bool align, Error **errp);
126 #define spapr_irq_findone(spapr, errp) spapr_irq_find(spapr, 1, false, errp)
127
128 #endif