| 1 | /* |
| 2 | * QEMU PowerPC XIVE internal structure definitions |
| 3 | * |
| 4 | * |
| 5 | * The XIVE structures are accessed by the HW and their format is |
| 6 | * architected to be big-endian. Some macros are provided to ease |
| 7 | * access to the different fields. |
| 8 | * |
| 9 | * |
| 10 | * Copyright (c) 2016-2024, IBM Corporation. |
| 11 | * |
| 12 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 13 | */ |
| 14 | |
| 15 | #ifndef PPC_XIVE_REGS_H |
| 16 | #define PPC_XIVE_REGS_H |
| 17 | |
| 18 | #include "qemu/bswap.h" |
| 19 | #include "qemu/host-utils.h" |
| 20 | |
| 21 | /* |
| 22 | * Interrupt source number encoding on PowerBUS |
| 23 | */ |
| 24 | /* |
| 25 | * Trigger data definition |
| 26 | * |
| 27 | * The trigger definition is used for triggers both for HW source |
| 28 | * interrupts (PHB, PSI), as well as for rerouting interrupts between |
| 29 | * Interrupt Controller. |
| 30 | * |
| 31 | * HW source controllers set bit0 of word0 to ‘0’ as they provide EAS |
| 32 | * information (EAS block + EAS index) in the 8 byte data and not END |
| 33 | * information, which is use for rerouting interrupts. |
| 34 | * |
| 35 | * bit1 of word0 to ‘1’ signals that the state bit check has been |
| 36 | * performed. |
| 37 | */ |
| 38 | #define XIVE_TRIGGER_END PPC_BIT(0) |
| 39 | #define XIVE_TRIGGER_PQ PPC_BIT(1) |
| 40 | |
| 41 | /* |
| 42 | * QEMU macros to manipulate the trigger payload in native endian |
| 43 | */ |
| 44 | #define XIVE_EAS_BLOCK(n) (((n) >> 28) & 0xf) |
| 45 | #define XIVE_EAS_INDEX(n) ((n) & 0x0fffffff) |
| 46 | #define XIVE_EAS(blk, idx) ((uint32_t)(blk) << 28 | (idx)) |
| 47 | |
| 48 | #define TM_SHIFT 16 |
| 49 | |
| 50 | /* |
| 51 | * TIMA addresses are 12-bits (4k page). |
| 52 | * The MSB indicates a special op with side effect, which can be |
| 53 | * refined with bit 10 (see below). |
| 54 | * The registers, logically grouped in 4 rings (a quad-word each), are |
| 55 | * defined on the 6 LSBs (offset below 0x40) |
| 56 | * In between, we can add a cache line index from 0...3 (ie, 0, 0x80, |
| 57 | * 0x100, 0x180) to select a specific snooper. Those 'snoop port |
| 58 | * address' bits should be dropped when processing the operations as |
| 59 | * they are all equivalent. |
| 60 | */ |
| 61 | #define TM_ADDRESS_MASK 0xC3F |
| 62 | #define TM_SPECIAL_OP 0x800 |
| 63 | #define TM_RING_OFFSET 0x30 |
| 64 | #define TM_REG_OFFSET 0x3F |
| 65 | |
| 66 | /* TM register offsets */ |
| 67 | #define TM_QW0_USER 0x000 /* All rings */ |
| 68 | #define TM_QW1_OS 0x010 /* Ring 0..2 */ |
| 69 | #define TM_QW2_HV_POOL 0x020 /* Ring 0..1 */ |
| 70 | #define TM_QW3_HV_PHYS 0x030 /* Ring 0..1 */ |
| 71 | |
| 72 | /* Byte offsets inside a QW QW0 QW1 QW2 QW3 */ |
| 73 | #define TM_NSR 0x0 /* + + - + */ |
| 74 | #define TM_CPPR 0x1 /* - + - + */ |
| 75 | #define TM_IPB 0x2 /* - + + + */ |
| 76 | #define TM_LSMFB 0x3 /* - + + + */ |
| 77 | #define TM_ACK_CNT 0x4 /* - + - - */ |
| 78 | #define TM_INC 0x5 /* - + - + */ |
| 79 | #define TM_LGS 0x5 /* + + + + */ /* Rename P10 */ |
| 80 | #define TM_AGE 0x6 /* - + - + */ |
| 81 | #define TM_T 0x6 /* - + - + */ /* Rename P10 */ |
| 82 | #define TM_PIPR 0x7 /* - + - + */ |
| 83 | #define TM_OGEN 0xF /* - + - - */ /* P10 only */ |
| 84 | |
| 85 | #define TM_WORD0 0x0 |
| 86 | #define TM_WORD1 0x4 |
| 87 | |
| 88 | /* |
| 89 | * QW word 2 contains the valid bit at the top and other fields |
| 90 | * depending on the QW. |
| 91 | */ |
| 92 | #define TM_WORD2 0x8 |
| 93 | #define TM_QW0W2_VU PPC_BIT32(0) |
| 94 | #define TM_QW0W2_LOGIC_SERV PPC_BITMASK32(1, 31) /* XX 2,31 ? */ |
| 95 | #define TM_QW1W2_VO PPC_BIT32(0) |
| 96 | #define TM_QW1W2_OS_CAM PPC_BITMASK32(8, 31) |
| 97 | #define TM_QW2W2_VP PPC_BIT32(0) |
| 98 | #define TM_QW2W2_POOL_CAM PPC_BITMASK32(8, 31) |
| 99 | #define TM_QW3W2_VT PPC_BIT32(0) |
| 100 | #define TM_QW3W2_LP PPC_BIT32(6) |
| 101 | #define TM_QW3W2_LE PPC_BIT32(7) |
| 102 | #define TM_QW3W2_T PPC_BIT32(31) |
| 103 | #define TM_QW3B8_VT PPC_BIT8(0) |
| 104 | |
| 105 | /* |
| 106 | * In addition to normal loads to "peek" and writes (only when invalid) |
| 107 | * using 4 and 8 bytes accesses, the above registers support these |
| 108 | * "special" byte operations: |
| 109 | * |
| 110 | * - Byte load from QW0[NSR] - User level NSR (EBB) |
| 111 | * - Byte store to QW0[NSR] - User level NSR (EBB) |
| 112 | * - Byte load/store to QW1[CPPR] and QW3[CPPR] - CPPR access |
| 113 | * - Byte load from QW3[TM_WORD2] - Read VT||00000||LP||LE on thrd 0 |
| 114 | * otherwise VT||0000000 |
| 115 | * - Byte store to QW3[TM_WORD2] - Set VT bit (and LP/LE if present) |
| 116 | * |
| 117 | * Then we have all these "special" CI ops at these offset that trigger |
| 118 | * all sorts of side effects: |
| 119 | */ |
| 120 | #define TM_SPC_ACK_EBB 0x800 /* Load8 ack EBB to reg */ |
| 121 | #define TM_SPC_ACK_OS_REG 0x810 /* Load16 ack OS irq to reg */ |
| 122 | #define TM_SPC_PUSH_USR_CTX 0x808 /* Store32 Push/Validate user context */ |
| 123 | #define TM_SPC_PULL_USR_CTX 0x808 /* Load32 Pull/Invalidate user */ |
| 124 | /* context */ |
| 125 | #define TM_SPC_SET_OS_PENDING 0x812 /* Store8 Set OS irq pending bit */ |
| 126 | #define TM_SPC_PULL_OS_CTX_G2 0x810 /* Load32/Load64 Pull/Invalidate OS */ |
| 127 | /* context to reg */ |
| 128 | #define TM_SPC_PULL_OS_CTX 0x818 /* Load32/Load64 Pull/Invalidate OS */ |
| 129 | /* context to reg */ |
| 130 | #define TM_SPC_PULL_POOL_CTX_G2 0x820 /* Load32/Load64 Pull/Invalidate Pool */ |
| 131 | /* context to reg */ |
| 132 | #define TM_SPC_PULL_POOL_CTX 0x828 /* Load32/Load64 Pull/Invalidate Pool */ |
| 133 | /* context to reg */ |
| 134 | #define TM_SPC_ACK_HV_REG 0x830 /* Load16 ack HV irq to reg */ |
| 135 | #define TM_SPC_PULL_PHYS_CTX_G2 0x830 /* Load32 Pull phys ctx to reg */ |
| 136 | #define TM_SPC_PULL_PHYS_CTX 0x838 /* Load8 Pull phys ctx to reg */ |
| 137 | #define TM_SPC_PULL_USR_CTX_OL 0xc08 /* Store8 Pull/Inval usr ctx to odd */ |
| 138 | /* line */ |
| 139 | #define TM_SPC_ACK_OS_EL 0xc10 /* Store8 ack OS irq to even line */ |
| 140 | #define TM_SPC_PULL_OS_CTX_OL 0xc18 /* Pull/Invalidate OS context to */ |
| 141 | /* odd Thread reporting line */ |
| 142 | #define TM_SPC_ACK_HV_POOL_EL 0xc20 /* Store8 ack HV evt pool to even */ |
| 143 | /* line */ |
| 144 | #define TM_SPC_ACK_HV_EL 0xc30 /* Store8 ack HV irq to even line */ |
| 145 | #define TM_SPC_PULL_PHYS_CTX_OL 0xc38 /* Pull phys ctx to odd cache line */ |
| 146 | /* XXX more... */ |
| 147 | |
| 148 | /* |
| 149 | * NSR fields for the various QW ack types |
| 150 | * |
| 151 | * P10 has an extra bit in QW3 for the group level instead of the |
| 152 | * reserved 'i' bit. Since it is not used and we don't support group |
| 153 | * interrupts on P9, we use the P10 definition for the group level so |
| 154 | * that we can have common macros for the NSR |
| 155 | */ |
| 156 | #define TM_QW0_NSR_EB PPC_BIT8(0) |
| 157 | #define TM_QW1_NSR_EO PPC_BIT8(0) |
| 158 | #define TM_QW3_NSR_HE PPC_BITMASK8(0, 1) |
| 159 | #define TM_QW3_NSR_HE_NONE 0 |
| 160 | #define TM_QW3_NSR_HE_POOL 1 |
| 161 | #define TM_QW3_NSR_HE_PHYS 2 |
| 162 | #define TM_QW3_NSR_HE_LSI 3 |
| 163 | #define TM_NSR_GRP_LVL PPC_BITMASK8(2, 7) |
| 164 | /* |
| 165 | * On P10, the format of the 6-bit group level is: 2 bits for the |
| 166 | * crowd size and 4 bits for the group size. Since group/crowd size is |
| 167 | * always a power of 2, we encode the log. For example, group_level=4 |
| 168 | * means crowd size = 0 and group size = 16 (2^4) |
| 169 | * Same encoding is used in the NVP and NVGC structures for |
| 170 | * PGoFirst and PGoNext fields |
| 171 | */ |
| 172 | |
| 173 | /* |
| 174 | * EAS (Event Assignment Structure) |
| 175 | * |
| 176 | * One per interrupt source. Targets an interrupt to a given Event |
| 177 | * Notification Descriptor (END) and provides the corresponding |
| 178 | * logical interrupt number (END data) |
| 179 | */ |
| 180 | typedef struct XiveEAS { |
| 181 | /* |
| 182 | * Use a single 64-bit definition to make it easier to perform |
| 183 | * atomic updates |
| 184 | */ |
| 185 | uint64_t w; |
| 186 | #define EAS_VALID PPC_BIT(0) |
| 187 | #define EAS_END_BLOCK PPC_BITMASK(4, 7) /* Destination END block# */ |
| 188 | #define EAS_END_INDEX PPC_BITMASK(8, 31) /* Destination END index */ |
| 189 | #define EAS_MASKED PPC_BIT(32) /* Masked */ |
| 190 | #define EAS_END_DATA PPC_BITMASK(33, 63) /* Data written to the END */ |
| 191 | } XiveEAS; |
| 192 | |
| 193 | #define xive_eas_is_valid(eas) (be64_to_cpu((eas)->w) & EAS_VALID) |
| 194 | #define xive_eas_is_masked(eas) (be64_to_cpu((eas)->w) & EAS_MASKED) |
| 195 | |
| 196 | void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, GString *buf); |
| 197 | |
| 198 | static inline uint64_t xive_get_field64(uint64_t mask, uint64_t word) |
| 199 | { |
| 200 | return (be64_to_cpu(word) & mask) >> ctz64(mask); |
| 201 | } |
| 202 | |
| 203 | static inline uint64_t xive_set_field64(uint64_t mask, uint64_t word, |
| 204 | uint64_t value) |
| 205 | { |
| 206 | uint64_t tmp = |
| 207 | (be64_to_cpu(word) & ~mask) | ((value << ctz64(mask)) & mask); |
| 208 | return cpu_to_be64(tmp); |
| 209 | } |
| 210 | |
| 211 | static inline uint32_t xive_get_field32(uint32_t mask, uint32_t word) |
| 212 | { |
| 213 | return (be32_to_cpu(word) & mask) >> ctz32(mask); |
| 214 | } |
| 215 | |
| 216 | static inline uint32_t xive_set_field32(uint32_t mask, uint32_t word, |
| 217 | uint32_t value) |
| 218 | { |
| 219 | uint32_t tmp = |
| 220 | (be32_to_cpu(word) & ~mask) | ((value << ctz32(mask)) & mask); |
| 221 | return cpu_to_be32(tmp); |
| 222 | } |
| 223 | |
| 224 | /* Event Notification Descriptor (END) */ |
| 225 | typedef struct XiveEND { |
| 226 | uint32_t w0; |
| 227 | #define END_W0_VALID PPC_BIT32(0) /* "v" bit */ |
| 228 | #define END_W0_ENQUEUE PPC_BIT32(1) /* "q" bit */ |
| 229 | #define END_W0_UCOND_NOTIFY PPC_BIT32(2) /* "n" bit */ |
| 230 | #define END_W0_BACKLOG PPC_BIT32(3) /* "b" bit */ |
| 231 | #define END_W0_PRECL_ESC_CTL PPC_BIT32(4) /* "p" bit */ |
| 232 | #define END_W0_ESCALATE_CTL PPC_BIT32(5) /* "e" bit */ |
| 233 | #define END_W0_UNCOND_ESCALATE PPC_BIT32(6) /* "u" bit - DD2.0 */ |
| 234 | #define END_W0_SILENT_ESCALATE PPC_BIT32(7) /* "s" bit - DD2.0 */ |
| 235 | #define END_W0_QSIZE PPC_BITMASK32(12, 15) |
| 236 | #define END_W0_SW0 PPC_BIT32(16) |
| 237 | #define END_W0_FIRMWARE END_W0_SW0 /* Owned by FW */ |
| 238 | #define END_QSIZE_4K 0 |
| 239 | #define END_QSIZE_64K 4 |
| 240 | #define END_W0_HWDEP PPC_BITMASK32(24, 31) |
| 241 | uint32_t w1; |
| 242 | #define END_W1_ESn PPC_BITMASK32(0, 1) |
| 243 | #define END_W1_ESn_P PPC_BIT32(0) |
| 244 | #define END_W1_ESn_Q PPC_BIT32(1) |
| 245 | #define END_W1_ESe PPC_BITMASK32(2, 3) |
| 246 | #define END_W1_ESe_P PPC_BIT32(2) |
| 247 | #define END_W1_ESe_Q PPC_BIT32(3) |
| 248 | #define END_W1_GENERATION PPC_BIT32(9) |
| 249 | #define END_W1_PAGE_OFF PPC_BITMASK32(10, 31) |
| 250 | uint32_t w2; |
| 251 | #define END_W2_MIGRATION_REG PPC_BITMASK32(0, 3) |
| 252 | #define END_W2_OP_DESC_HI PPC_BITMASK32(4, 31) |
| 253 | uint32_t w3; |
| 254 | #define END_W3_OP_DESC_LO PPC_BITMASK32(0, 31) |
| 255 | uint32_t w4; |
| 256 | #define END_W4_ESC_END_BLOCK PPC_BITMASK32(4, 7) |
| 257 | #define END_W4_ESC_END_INDEX PPC_BITMASK32(8, 31) |
| 258 | uint32_t w5; |
| 259 | #define END_W5_ESC_END_DATA PPC_BITMASK32(1, 31) |
| 260 | uint32_t w6; |
| 261 | #define END_W6_FORMAT_BIT PPC_BIT32(8) |
| 262 | #define END_W6_NVT_BLOCK PPC_BITMASK32(9, 12) |
| 263 | #define END_W6_NVT_INDEX PPC_BITMASK32(13, 31) |
| 264 | uint32_t w7; |
| 265 | #define END_W7_F0_IGNORE PPC_BIT32(0) |
| 266 | #define END_W7_F0_BLK_GROUPING PPC_BIT32(1) |
| 267 | #define END_W7_F0_PRIORITY PPC_BITMASK32(8, 15) |
| 268 | #define END_W7_F1_WAKEZ PPC_BIT32(0) |
| 269 | #define END_W7_F1_LOG_SERVER_ID PPC_BITMASK32(1, 31) |
| 270 | } XiveEND; |
| 271 | |
| 272 | #define xive_end_is_valid(end) (be32_to_cpu((end)->w0) & END_W0_VALID) |
| 273 | #define xive_end_is_enqueue(end) (be32_to_cpu((end)->w0) & END_W0_ENQUEUE) |
| 274 | #define xive_end_is_notify(end) (be32_to_cpu((end)->w0) & END_W0_UCOND_NOTIFY) |
| 275 | #define xive_end_is_backlog(end) (be32_to_cpu((end)->w0) & END_W0_BACKLOG) |
| 276 | #define xive_end_is_escalate(end) (be32_to_cpu((end)->w0) & END_W0_ESCALATE_CTL) |
| 277 | #define xive_end_is_uncond_escalation(end) \ |
| 278 | (be32_to_cpu((end)->w0) & END_W0_UNCOND_ESCALATE) |
| 279 | #define xive_end_is_silent_escalation(end) \ |
| 280 | (be32_to_cpu((end)->w0) & END_W0_SILENT_ESCALATE) |
| 281 | #define xive_end_is_firmware(end) \ |
| 282 | (be32_to_cpu((end)->w0) & END_W0_FIRMWARE) |
| 283 | |
| 284 | static inline uint64_t xive_end_qaddr(XiveEND *end) |
| 285 | { |
| 286 | return ((uint64_t) be32_to_cpu(end->w2) & 0x0fffffff) << 32 | |
| 287 | be32_to_cpu(end->w3); |
| 288 | } |
| 289 | |
| 290 | void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, GString *buf); |
| 291 | void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, GString *buf); |
| 292 | void xive_end_eas_pic_print_info(XiveEND *end, uint32_t end_idx, GString *buf); |
| 293 | |
| 294 | /* Notification Virtual Target (NVT) */ |
| 295 | typedef struct XiveNVT { |
| 296 | uint32_t w0; |
| 297 | #define NVT_W0_VALID PPC_BIT32(0) |
| 298 | uint32_t w1; |
| 299 | #define NVT_W1_EQ_BLOCK PPC_BITMASK32(0, 3) |
| 300 | #define NVT_W1_EQ_INDEX PPC_BITMASK32(4, 31) |
| 301 | uint32_t w2; |
| 302 | uint32_t w3; |
| 303 | uint32_t w4; |
| 304 | #define NVT_W4_IPB PPC_BITMASK32(16, 23) |
| 305 | uint32_t w5; |
| 306 | uint32_t w6; |
| 307 | uint32_t w7; |
| 308 | uint32_t w8; |
| 309 | #define NVT_W8_GRP_VALID PPC_BIT32(0) |
| 310 | uint32_t w9; |
| 311 | uint32_t wa; |
| 312 | uint32_t wb; |
| 313 | uint32_t wc; |
| 314 | uint32_t wd; |
| 315 | uint32_t we; |
| 316 | uint32_t wf; |
| 317 | } XiveNVT; |
| 318 | |
| 319 | #define xive_nvt_is_valid(nvt) (be32_to_cpu((nvt)->w0) & NVT_W0_VALID) |
| 320 | |
| 321 | /* |
| 322 | * The VP number space in a block is defined by the END_W6_NVT_INDEX |
| 323 | * field of the XIVE END |
| 324 | */ |
| 325 | #define XIVE_NVT_SHIFT 19 |
| 326 | #define XIVE_NVT_COUNT (1 << XIVE_NVT_SHIFT) |
| 327 | |
| 328 | static inline uint32_t xive_nvt_cam_line(uint8_t nvt_blk, uint32_t nvt_idx) |
| 329 | { |
| 330 | return (nvt_blk << XIVE_NVT_SHIFT) | nvt_idx; |
| 331 | } |
| 332 | |
| 333 | static inline uint32_t xive_nvt_idx(uint32_t cam_line) |
| 334 | { |
| 335 | return cam_line & ((1 << XIVE_NVT_SHIFT) - 1); |
| 336 | } |
| 337 | |
| 338 | static inline uint32_t xive_nvt_blk(uint32_t cam_line) |
| 339 | { |
| 340 | return (cam_line >> XIVE_NVT_SHIFT) & 0xf; |
| 341 | } |
| 342 | |
| 343 | #endif /* PPC_XIVE_REGS_H */ |