| 1 | /* |
| 2 | * QEMU RISC-V Boot Helper |
| 3 | * |
| 4 | * Copyright (c) 2017 SiFive, Inc. |
| 5 | * Copyright (c) 2019 Alistair Francis <alistair.francis@wdc.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it |
| 8 | * under the terms and conditions of the GNU General Public License, |
| 9 | * version 2 or later, as published by the Free Software Foundation. |
| 10 | * |
| 11 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 14 | * more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License along with |
| 17 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #ifndef RISCV_BOOT_H |
| 21 | #define RISCV_BOOT_H |
| 22 | |
| 23 | #include "exec/cpu-defs.h" |
| 24 | #include "hw/core/loader.h" |
| 25 | #include "hw/riscv/riscv_hart.h" |
| 26 | |
| 27 | #define RISCV32_BIOS_BIN "opensbi-riscv32-generic-fw_dynamic.bin" |
| 28 | #define RISCV64_BIOS_BIN "opensbi-riscv64-generic-fw_dynamic.bin" |
| 29 | |
| 30 | typedef struct RISCVBootInfo { |
| 31 | /* First contiguous RAM region. If size is zero then assume entire RAM */ |
| 32 | hwaddr ram_low_start; |
| 33 | hwaddr ram_low_size; |
| 34 | |
| 35 | ssize_t kernel_size; |
| 36 | hwaddr image_low_addr; |
| 37 | hwaddr image_high_addr; |
| 38 | |
| 39 | hwaddr initrd_start; |
| 40 | ssize_t initrd_size; |
| 41 | |
| 42 | bool is_32bit; |
| 43 | } RISCVBootInfo; |
| 44 | |
| 45 | bool riscv_is_32bit(RISCVHartArrayState *harts); |
| 46 | |
| 47 | char *riscv_plic_hart_config_string(int hart_count); |
| 48 | |
| 49 | void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartArrayState *harts); |
| 50 | void riscv_boot_info_init_discontig_mem(RISCVBootInfo *info, |
| 51 | RISCVHartArrayState *harts, |
| 52 | hwaddr low_start, hwaddr low_size); |
| 53 | vaddr riscv_calc_kernel_start_addr(RISCVBootInfo *info, |
| 54 | hwaddr firmware_end_addr); |
| 55 | hwaddr riscv_find_and_load_firmware(MachineState *machine, |
| 56 | RISCVBootInfo *info, |
| 57 | const char *default_machine_firmware, |
| 58 | hwaddr *firmware_load_addr, |
| 59 | symbol_fn_t sym_cb); |
| 60 | const char *riscv_default_firmware_name(RISCVHartArrayState *harts); |
| 61 | char *riscv_find_firmware(const char *firmware_filename, |
| 62 | const char *default_machine_firmware); |
| 63 | hwaddr riscv_load_firmware(MachineState *machine, |
| 64 | const RISCVBootInfo *info, |
| 65 | const char *firmware_filename, |
| 66 | hwaddr *firmware_load_addr, |
| 67 | symbol_fn_t sym_cb); |
| 68 | void riscv_load_kernel(MachineState *machine, |
| 69 | RISCVBootInfo *info, |
| 70 | vaddr kernel_start_addr, |
| 71 | bool load_initrd, |
| 72 | symbol_fn_t sym_cb); |
| 73 | uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size, |
| 74 | MachineState *ms, RISCVBootInfo *info); |
| 75 | void riscv_load_fdt(hwaddr fdt_addr, void *fdt); |
| 76 | void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts, |
| 77 | hwaddr saddr, |
| 78 | hwaddr rom_base, hwaddr rom_size, |
| 79 | uint64_t kernel_entry, |
| 80 | uint64_t fdt_load_addr); |
| 81 | void riscv_rom_copy_firmware_info(MachineState *machine, |
| 82 | RISCVHartArrayState *harts, |
| 83 | hwaddr rom_base, |
| 84 | hwaddr rom_size, |
| 85 | uint32_t reset_vec_size, |
| 86 | uint64_t kernel_entry); |
| 87 | void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr); |
| 88 | void riscv_setup_firmware_boot(MachineState *machine); |
| 89 | |
| 90 | #endif /* RISCV_BOOT_H */ |