| 1 | /* |
| 2 | * Coherent Processing System emulation. |
| 3 | * |
| 4 | * Copyright (c) 2016 Imagination Technologies |
| 5 | * |
| 6 | * Copyright (c) 2025 MIPS |
| 7 | * |
| 8 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 9 | * |
| 10 | */ |
| 11 | |
| 12 | #ifndef RISCV_CPS_H |
| 13 | #define RISCV_CPS_H |
| 14 | |
| 15 | #include "hw/core/sysbus.h" |
| 16 | #include "hw/misc/riscv_cmgcr.h" |
| 17 | #include "hw/misc/riscv_cpc.h" |
| 18 | #include "target/riscv/cpu.h" |
| 19 | #include "qom/object.h" |
| 20 | |
| 21 | #define TYPE_RISCV_CPS "riscv-cps" |
| 22 | OBJECT_DECLARE_SIMPLE_TYPE(RISCVCPSState, RISCV_CPS) |
| 23 | |
| 24 | /* The model supports up to 64 harts. */ |
| 25 | #define MAX_HARTS 64 |
| 26 | |
| 27 | /* The global CM base for the boston-aia model. */ |
| 28 | #define GLOBAL_CM_BASE 0x16100000 |
| 29 | /* The CM block is 512 KiB. */ |
| 30 | #define CM_SIZE (1ULL << 19) |
| 31 | |
| 32 | /* |
| 33 | * The mhartid bits has cluster at bit 16, core at bit 4, and hart at |
| 34 | * bit 0. |
| 35 | */ |
| 36 | |
| 37 | #define MHARTID_CLUSTER_SHIFT 16 |
| 38 | #define MHARTID_CORE_SHIFT 4 |
| 39 | #define MHARTID_HART_SHIFT 0 |
| 40 | |
| 41 | #define APLIC_NUM_SOURCES 0x35 /* Arbitray maximum number of interrupts. */ |
| 42 | #define APLIC_NUM_PRIO_BITS 3 |
| 43 | #define AIA_PLIC_M_OFFSET 0x40000 |
| 44 | #define AIA_PLIC_M_SIZE 0x8000 |
| 45 | #define AIA_PLIC_S_OFFSET 0x60000 |
| 46 | #define AIA_PLIC_S_SIZE 0x8000 |
| 47 | #define AIA_CLINT_OFFSET 0x50000 |
| 48 | |
| 49 | typedef struct RISCVCPSState { |
| 50 | SysBusDevice parent_obj; |
| 51 | |
| 52 | uint32_t num_vp; |
| 53 | uint32_t num_hart; |
| 54 | uint32_t num_core; |
| 55 | uint64_t gcr_base; |
| 56 | char *cpu_type; |
| 57 | |
| 58 | MemoryRegion container; |
| 59 | RISCVGCRState gcr; |
| 60 | RISCVCPCState cpc; |
| 61 | |
| 62 | DeviceState *aplic; |
| 63 | CPUState **cpus; |
| 64 | } RISCVCPSState; |
| 65 | |
| 66 | #endif |