| 1 | /* |
| 2 | * RISC-V board helpers for FDT generation. |
| 3 | * |
| 4 | * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 7 | */ |
| 8 | |
| 9 | #ifndef RISCV_VIRT_FDT_H |
| 10 | #define RISCV_VIRT_FDT_H |
| 11 | |
| 12 | #include "target/riscv/cpu.h" |
| 13 | |
| 14 | void *create_board_device_tree(const char *model, const char *compatible, |
| 15 | int *fdt_size); |
| 16 | void create_fdt_socket_memory(void *fdt, hwaddr addr, uint64_t size, |
| 17 | int socket_id, bool numa_enabled); |
| 18 | void create_fdt_clint(void *fdt, hwaddr addr, uint64_t size, |
| 19 | uint32_t *intc_phandles, int num_harts); |
| 20 | void create_fdt_socket_clint(void *fdt, hwaddr addr, uint64_t size, |
| 21 | int socket_id, uint32_t *intc_phandles, |
| 22 | int num_harts, bool numa_enabled); |
| 23 | void fdt_create_cpu_socket_subnode(void *fdt, uint64_t timebase_frequency); |
| 24 | void create_fdt_socket_cpus(void *fdt, RISCVCPU *socket_harts, |
| 25 | int socket_id, int num_harts_socket, |
| 26 | int socket_hartid_base, uint32_t *phandle, |
| 27 | uint32_t *intc_phandles, bool numa_enabled, |
| 28 | bool is_32_bit); |
| 29 | void create_fdt_socket_cpu_sifive(void *fdt, char *clust_name, |
| 30 | int cpu_id, int socket_id, |
| 31 | int socket_hartid_base, uint32_t *phandle, |
| 32 | uint32_t *intc_phandles); |
| 33 | void create_fdt_plic(void *fdt, hwaddr addr, uint64_t size, |
| 34 | uint32_t plic_phandle, uint32_t int_cells, |
| 35 | uint32_t addr_cells, uint32_t *plic_cells, |
| 36 | uint32_t cells_size, uint32_t ndev_sources, |
| 37 | bool numa_enabled, int socket); |
| 38 | void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name); |
| 39 | #endif |