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1 /*
2 * QEMU RISC-V Virt Board Compatible with kendryte K230 SDK
3 *
4 * Copyright (c) 2025 Chao Liu <chao.liu.zevorn@gmail.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0-or-later
7 *
8 * Provides a board compatible with the kendryte K230 SDK
9 *
10 * K230 Technical Reference Manual V0.3.1 (2024-11-18):
11 * https://github.com/revyos/external-docs/blob/master/K230/en-us/K230_Technical_Reference_Manual_V0.3.1_20241118.pdf
12 *
13 * For more information, see <https://www.kendryte.com/en/proDetail/230>
14 */
15 #ifndef HW_K230_H
16 #define HW_K230_H
17
18 #include "hw/core/boards.h"
19 #include "hw/misc/k230_ddr.h"
20 #include "hw/riscv/riscv_hart.h"
21 #include "hw/watchdog/k230_wdt.h"
22 #include "hw/dma/k230_gsdma.h"
23 #include "hw/misc/k230_decomp_gzip.h"
24
25 #define C908_CPU_HARTID (0)
26
27 #define TYPE_RISCV_K230_SOC "riscv.k230.soc"
28 #define RISCV_K230_SOC(obj) \
29 OBJECT_CHECK(K230SoCState, (obj), TYPE_RISCV_K230_SOC)
30
31 typedef struct K230SoCState {
32 /*< private >*/
33 DeviceState parent_obj;
34
35 /*< public >*/
36 RISCVHartArrayState c908_cpu; /* Small core */
37
38 K230DDRCfgState ddr_cfg;
39 K230DDRPhyState ddr_phy;
40 K230WdtState wdt[2];
41 K230GSDMAState gsdma;
42 K230DecompGzipState decomp_gzip;
43 MemoryRegion sram;
44 MemoryRegion bootrom;
45
46 DeviceState *c908_plic;
47 } K230SoCState;
48
49 #define TYPE_RISCV_K230_MACHINE MACHINE_TYPE_NAME("k230")
50 #define RISCV_K230_MACHINE(obj) \
51 OBJECT_CHECK(K230MachineState, (obj), TYPE_RISCV_K230_MACHINE)
52
53 typedef struct K230MachineState {
54 /*< private >*/
55 MachineState parent_obj;
56
57 /*< public >*/
58 K230SoCState soc;
59 Notifier machine_done;
60 } K230MachineState;
61
62 enum {
63 K230_DEV_DDRC,
64 K230_DEV_KPU_L2_CACHE,
65 K230_DEV_SRAM,
66 K230_DEV_KPU_CFG,
67 K230_DEV_FFT,
68 K230_DEV_AI_2D_ENGINE,
69 K230_DEV_GSDMA,
70 K230_DEV_DMA,
71 K230_DEV_DECOMP_GZIP,
72 K230_DEV_NON_AI_2D,
73 K230_DEV_ISP,
74 K230_DEV_DEWARP,
75 K230_DEV_RX_CSI,
76 K230_DEV_H264,
77 K230_DEV_2P5D,
78 K230_DEV_VO,
79 K230_DEV_VO_CFG,
80 K230_DEV_3D_ENGINE,
81 K230_DEV_PMU,
82 K230_DEV_RTC,
83 K230_DEV_CMU,
84 K230_DEV_RMU,
85 K230_DEV_BOOT,
86 K230_DEV_PWR,
87 K230_DEV_MAILBOX,
88 K230_DEV_IOMUX,
89 K230_DEV_TIMER,
90 K230_DEV_WDT0,
91 K230_DEV_WDT1,
92 K230_DEV_TS,
93 K230_DEV_HDI,
94 K230_DEV_STC,
95 K230_DEV_BOOTROM,
96 K230_DEV_SECURITY,
97 K230_DEV_UART0,
98 K230_DEV_UART1,
99 K230_DEV_UART2,
100 K230_DEV_UART3,
101 K230_DEV_UART4,
102 K230_DEV_I2C0,
103 K230_DEV_I2C1,
104 K230_DEV_I2C2,
105 K230_DEV_I2C3,
106 K230_DEV_I2C4,
107 K230_DEV_PWM,
108 K230_DEV_GPIO0,
109 K230_DEV_GPIO1,
110 K230_DEV_ADC,
111 K230_DEV_CODEC,
112 K230_DEV_I2S,
113 K230_DEV_USB0,
114 K230_DEV_USB1,
115 K230_DEV_SD0,
116 K230_DEV_SD1,
117 K230_DEV_QSPI0,
118 K230_DEV_QSPI1,
119 K230_DEV_SPI,
120 K230_DEV_HI_SYS_CFG,
121 K230_DEV_DDRC_CFG,
122 K230_DEV_DDR_PHY,
123 K230_DEV_FLASH,
124 K230_DEV_PLIC,
125 K230_DEV_CLINT,
126 };
127
128 enum {
129 /*
130 * K230 TRM v0.3.1 section 2.4 lists peripheral interrupt bits; SDK
131 * DTBs expose the corresponding PLIC IDs as bit + 16.
132 */
133 K230_UART0_IRQ = 16,
134 K230_UART1_IRQ = 17,
135 K230_UART2_IRQ = 18,
136 K230_UART3_IRQ = 19,
137 K230_UART4_IRQ = 20,
138 K230_WDT0_IRQ = 107,
139 K230_WDT1_IRQ = 108,
140 K230_GSDMA_IRQ = 140,
141 };
142
143 #define K230_UART_COUNT 5
144
145 /*
146 * Integrates with the interrupt controller (PLIC),
147 * which can process 208 interrupt external sources
148 */
149 #define K230_PLIC_NUM_SOURCES 208
150 #define K230_PLIC_NUM_PRIORITIES 7
151 #define K230_PLIC_PRIORITY_BASE 0x00
152 #define K230_PLIC_PENDING_BASE 0x1000
153 #define K230_PLIC_ENABLE_BASE 0x2000
154 #define K230_PLIC_ENABLE_STRIDE 0x80
155 #define K230_PLIC_CONTEXT_BASE 0x200000
156 #define K230_PLIC_CONTEXT_STRIDE 0x1000
157
158 #endif