| 1 | /* |
| 2 | * QOM type definitions for riscv32 / riscv64 machines |
| 3 | * |
| 4 | * Copyright (c) rev.ng Labs Srl. |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 7 | */ |
| 8 | |
| 9 | #ifndef HW_RISCV_MACHINES_QOM_H |
| 10 | #define HW_RISCV_MACHINES_QOM_H |
| 11 | |
| 12 | #include "hw/core/boards.h" |
| 13 | |
| 14 | #define TYPE_TARGET_RISCV32_MACHINE \ |
| 15 | "target-info-riscv32-machine" |
| 16 | |
| 17 | #define TYPE_TARGET_RISCV64_MACHINE \ |
| 18 | "target-info-riscv64-machine" |
| 19 | |
| 20 | /* |
| 21 | * Interfaces specifying whether a given QOM object is available in |
| 22 | * qemu-system-riscv32, qemu-system-riscv64, or both. |
| 23 | */ |
| 24 | |
| 25 | extern const InterfaceInfo riscv32_machine_interfaces[]; |
| 26 | extern const InterfaceInfo riscv64_machine_interfaces[]; |
| 27 | extern const InterfaceInfo riscv32_64_machine_interfaces[]; |
| 28 | |
| 29 | /* |
| 30 | * Helper macros for defining machines available in qemu-system-riscv32, |
| 31 | * qemu-system-riscv64, or both. |
| 32 | */ |
| 33 | |
| 34 | #define DEFINE_MACHINE_RISCV32(namestr, machine_initfn) \ |
| 35 | DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \ |
| 36 | riscv32_machine_interfaces) |
| 37 | |
| 38 | #define DEFINE_MACHINE_RISCV64(namestr, machine_initfn) \ |
| 39 | DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \ |
| 40 | riscv64_machine_interfaces) |
| 41 | |
| 42 | #define DEFINE_MACHINE_RISCV32_64(namestr, machine_initfn) \ |
| 43 | DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \ |
| 44 | riscv32_64_machine_interfaces) |
| 45 | |
| 46 | #endif |