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1 /*
2 * Microchip PolarFire SoC machine interface
3 *
4 * Copyright (c) 2020 Wind River Systems, Inc.
5 *
6 * Author:
7 * Bin Meng <bin.meng@windriver.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2 or later, as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #ifndef HW_MICROCHIP_PFSOC_H
23 #define HW_MICROCHIP_PFSOC_H
24
25 #include "hw/core/boards.h"
26 #include "hw/char/mchp_pfsoc_mmuart.h"
27 #include "hw/cpu/cluster.h"
28 #include "hw/dma/sifive_pdma.h"
29 #include "hw/misc/mchp_pfsoc_dmc.h"
30 #include "hw/misc/mchp_pfsoc_ioscb.h"
31 #include "hw/misc/mchp_pfsoc_sysreg.h"
32 #include "hw/net/cadence_gem.h"
33 #include "hw/sd/cadence_sdhci.h"
34 #include "hw/riscv/riscv_hart.h"
35
36 typedef struct MicrochipPFSoCState {
37 /*< private >*/
38 DeviceState parent_obj;
39
40 /*< public >*/
41 CPUClusterState e_cluster;
42 CPUClusterState u_cluster;
43 RISCVHartArrayState e_cpus;
44 RISCVHartArrayState u_cpus;
45 DeviceState *plic;
46 MchpPfSoCDdrSgmiiPhyState ddr_sgmii_phy;
47 MchpPfSoCDdrCfgState ddr_cfg;
48 MchpPfSoCIoscbState ioscb;
49 MchpPfSoCMMUartState *serial0;
50 MchpPfSoCMMUartState *serial1;
51 MchpPfSoCMMUartState *serial2;
52 MchpPfSoCMMUartState *serial3;
53 MchpPfSoCMMUartState *serial4;
54 MchpPfSoCSysregState sysreg;
55 SiFivePDMAState dma;
56 CadenceGEMState gem0;
57 CadenceGEMState gem1;
58 CadenceSDHCIState sdhci;
59 } MicrochipPFSoCState;
60
61 #define TYPE_MICROCHIP_PFSOC "microchip.pfsoc"
62 #define MICROCHIP_PFSOC(obj) \
63 OBJECT_CHECK(MicrochipPFSoCState, (obj), TYPE_MICROCHIP_PFSOC)
64
65 typedef struct MicrochipIcicleKitState {
66 /*< private >*/
67 MachineState parent_obj;
68
69 /*< public >*/
70 uint32_t clint_timebase_freq;
71 MicrochipPFSoCState soc;
72 } MicrochipIcicleKitState;
73
74 #define TYPE_MICROCHIP_ICICLE_KIT_MACHINE \
75 MACHINE_TYPE_NAME("microchip-icicle-kit")
76 #define MICROCHIP_ICICLE_KIT_MACHINE(obj) \
77 OBJECT_CHECK(MicrochipIcicleKitState, (obj), \
78 TYPE_MICROCHIP_ICICLE_KIT_MACHINE)
79
80 enum {
81 MICROCHIP_PFSOC_RSVD0,
82 MICROCHIP_PFSOC_DEBUG,
83 MICROCHIP_PFSOC_E51_DTIM,
84 MICROCHIP_PFSOC_BUSERR_UNIT0,
85 MICROCHIP_PFSOC_BUSERR_UNIT1,
86 MICROCHIP_PFSOC_BUSERR_UNIT2,
87 MICROCHIP_PFSOC_BUSERR_UNIT3,
88 MICROCHIP_PFSOC_BUSERR_UNIT4,
89 MICROCHIP_PFSOC_CLINT,
90 MICROCHIP_PFSOC_L2CC,
91 MICROCHIP_PFSOC_DMA,
92 MICROCHIP_PFSOC_L2LIM,
93 MICROCHIP_PFSOC_PLIC,
94 MICROCHIP_PFSOC_MMUART0,
95 MICROCHIP_PFSOC_WDOG0,
96 MICROCHIP_PFSOC_SYSREG,
97 MICROCHIP_PFSOC_AXISW,
98 MICROCHIP_PFSOC_MPUCFG,
99 MICROCHIP_PFSOC_FMETER,
100 MICROCHIP_PFSOC_DDR_SGMII_PHY,
101 MICROCHIP_PFSOC_EMMC_SD,
102 MICROCHIP_PFSOC_DDR_CFG,
103 MICROCHIP_PFSOC_MMUART1,
104 MICROCHIP_PFSOC_MMUART2,
105 MICROCHIP_PFSOC_MMUART3,
106 MICROCHIP_PFSOC_MMUART4,
107 MICROCHIP_PFSOC_WDOG1,
108 MICROCHIP_PFSOC_WDOG2,
109 MICROCHIP_PFSOC_WDOG3,
110 MICROCHIP_PFSOC_WDOG4,
111 MICROCHIP_PFSOC_SPI0,
112 MICROCHIP_PFSOC_SPI1,
113 MICROCHIP_PFSOC_I2C0,
114 MICROCHIP_PFSOC_I2C1,
115 MICROCHIP_PFSOC_CAN0,
116 MICROCHIP_PFSOC_CAN1,
117 MICROCHIP_PFSOC_GEM0,
118 MICROCHIP_PFSOC_GEM1,
119 MICROCHIP_PFSOC_GPIO0,
120 MICROCHIP_PFSOC_GPIO1,
121 MICROCHIP_PFSOC_GPIO2,
122 MICROCHIP_PFSOC_RTC,
123 MICROCHIP_PFSOC_ENVM_CFG,
124 MICROCHIP_PFSOC_ENVM_DATA,
125 MICROCHIP_PFSOC_USB,
126 MICROCHIP_PFSOC_QSPI_XIP,
127 MICROCHIP_PFSOC_IOSCB,
128 MICROCHIP_PFSOC_FABRIC_FIC0,
129 MICROCHIP_PFSOC_FABRIC_FIC1,
130 MICROCHIP_PFSOC_FABRIC_FIC3,
131 MICROCHIP_PFSOC_DRAM_LO,
132 MICROCHIP_PFSOC_DRAM_LO_ALIAS,
133 MICROCHIP_PFSOC_DRAM_HI,
134 MICROCHIP_PFSOC_DRAM_HI_ALIAS
135 };
136
137 enum {
138 MICROCHIP_PFSOC_DMA_IRQ0 = 5,
139 MICROCHIP_PFSOC_DMA_IRQ1 = 6,
140 MICROCHIP_PFSOC_DMA_IRQ2 = 7,
141 MICROCHIP_PFSOC_DMA_IRQ3 = 8,
142 MICROCHIP_PFSOC_DMA_IRQ4 = 9,
143 MICROCHIP_PFSOC_DMA_IRQ5 = 10,
144 MICROCHIP_PFSOC_DMA_IRQ6 = 11,
145 MICROCHIP_PFSOC_DMA_IRQ7 = 12,
146 MICROCHIP_PFSOC_GEM0_IRQ = 64,
147 MICROCHIP_PFSOC_GEM1_IRQ = 70,
148 MICROCHIP_PFSOC_EMMC_SD_IRQ = 88,
149 MICROCHIP_PFSOC_MMUART0_IRQ = 90,
150 MICROCHIP_PFSOC_MMUART1_IRQ = 91,
151 MICROCHIP_PFSOC_MMUART2_IRQ = 92,
152 MICROCHIP_PFSOC_MMUART3_IRQ = 93,
153 MICROCHIP_PFSOC_MMUART4_IRQ = 94,
154 MICROCHIP_PFSOC_MAILBOX_IRQ = 96,
155 };
156
157 #define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT 1
158 #define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT 4
159
160 #define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 187
161 #define MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES 7
162 #define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE 0x00
163 #define MICROCHIP_PFSOC_PLIC_PENDING_BASE 0x1000
164 #define MICROCHIP_PFSOC_PLIC_ENABLE_BASE 0x2000
165 #define MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE 0x80
166 #define MICROCHIP_PFSOC_PLIC_CONTEXT_BASE 0x200000
167 #define MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE 0x1000
168
169 #endif /* HW_MICROCHIP_PFSOC_H */