| 1 | /* |
| 2 | * QEMU RISC-V Board Compatible with OpenTitan FPGA platform |
| 3 | * |
| 4 | * Copyright (c) 2020 Western Digital |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms and conditions of the GNU General Public License, |
| 8 | * version 2 or later, as published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | * more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License along with |
| 16 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 17 | */ |
| 18 | |
| 19 | #ifndef HW_OPENTITAN_H |
| 20 | #define HW_OPENTITAN_H |
| 21 | |
| 22 | #include "hw/riscv/riscv_hart.h" |
| 23 | #include "hw/intc/sifive_plic.h" |
| 24 | #include "hw/char/ibex_uart.h" |
| 25 | #include "hw/timer/ibex_timer.h" |
| 26 | #include "hw/ssi/ibex_spi_host.h" |
| 27 | #include "hw/core/boards.h" |
| 28 | #include "qom/object.h" |
| 29 | |
| 30 | #define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc" |
| 31 | OBJECT_DECLARE_SIMPLE_TYPE(LowRISCIbexSoCState, RISCV_IBEX_SOC) |
| 32 | |
| 33 | enum { |
| 34 | OPENTITAN_SPI_HOST0, |
| 35 | OPENTITAN_SPI_HOST1, |
| 36 | OPENTITAN_NUM_SPI_HOSTS, |
| 37 | }; |
| 38 | |
| 39 | struct LowRISCIbexSoCState { |
| 40 | /*< private >*/ |
| 41 | SysBusDevice parent_obj; |
| 42 | |
| 43 | /*< public >*/ |
| 44 | RISCVHartArrayState cpus; |
| 45 | SiFivePLICState plic; |
| 46 | IbexUartState uart; |
| 47 | IbexTimerState timer; |
| 48 | IbexSPIHostState spi_host[OPENTITAN_NUM_SPI_HOSTS]; |
| 49 | |
| 50 | uint32_t resetvec; |
| 51 | |
| 52 | MemoryRegion flash_mem; |
| 53 | MemoryRegion rom; |
| 54 | MemoryRegion flash_alias; |
| 55 | }; |
| 56 | |
| 57 | #define TYPE_OPENTITAN_MACHINE MACHINE_TYPE_NAME("opentitan") |
| 58 | OBJECT_DECLARE_SIMPLE_TYPE(OpenTitanState, OPENTITAN_MACHINE) |
| 59 | |
| 60 | typedef struct OpenTitanState { |
| 61 | /*< private >*/ |
| 62 | MachineState parent_obj; |
| 63 | |
| 64 | /*< public >*/ |
| 65 | LowRISCIbexSoCState soc; |
| 66 | } OpenTitanState; |
| 67 | |
| 68 | enum { |
| 69 | IBEX_DEV_ROM, |
| 70 | IBEX_DEV_RAM, |
| 71 | IBEX_DEV_FLASH, |
| 72 | IBEX_DEV_FLASH_VIRTUAL, |
| 73 | IBEX_DEV_UART, |
| 74 | IBEX_DEV_SPI_DEVICE, |
| 75 | IBEX_DEV_SPI_HOST0, |
| 76 | IBEX_DEV_SPI_HOST1, |
| 77 | IBEX_DEV_GPIO, |
| 78 | IBEX_DEV_I2C, |
| 79 | IBEX_DEV_PATTGEN, |
| 80 | IBEX_DEV_TIMER, |
| 81 | IBEX_DEV_SENSOR_CTRL, |
| 82 | IBEX_DEV_OTP_CTRL, |
| 83 | IBEX_DEV_LC_CTRL, |
| 84 | IBEX_DEV_PWRMGR, |
| 85 | IBEX_DEV_RSTMGR, |
| 86 | IBEX_DEV_CLKMGR, |
| 87 | IBEX_DEV_PINMUX, |
| 88 | IBEX_DEV_AON_TIMER, |
| 89 | IBEX_DEV_USBDEV, |
| 90 | IBEX_DEV_FLASH_CTRL, |
| 91 | IBEX_DEV_PLIC, |
| 92 | IBEX_DEV_AES, |
| 93 | IBEX_DEV_HMAC, |
| 94 | IBEX_DEV_KMAC, |
| 95 | IBEX_DEV_KEYMGR, |
| 96 | IBEX_DEV_CSRNG, |
| 97 | IBEX_DEV_ENTROPY, |
| 98 | IBEX_DEV_EDNO, |
| 99 | IBEX_DEV_EDN1, |
| 100 | IBEX_DEV_ALERT_HANDLER, |
| 101 | IBEX_DEV_SRAM_CTRL, |
| 102 | IBEX_DEV_OTBN, |
| 103 | IBEX_DEV_IBEX_CFG, |
| 104 | }; |
| 105 | |
| 106 | enum { |
| 107 | IBEX_UART0_TX_WATERMARK_IRQ = 1, |
| 108 | IBEX_UART0_RX_WATERMARK_IRQ = 2, |
| 109 | IBEX_UART0_TX_EMPTY_IRQ = 3, |
| 110 | IBEX_UART0_RX_OVERFLOW_IRQ = 4, |
| 111 | IBEX_UART0_RX_FRAME_ERR_IRQ = 5, |
| 112 | IBEX_UART0_RX_BREAK_ERR_IRQ = 6, |
| 113 | IBEX_UART0_RX_TIMEOUT_IRQ = 7, |
| 114 | IBEX_UART0_RX_PARITY_ERR_IRQ = 8, |
| 115 | IBEX_TIMER_TIMEREXPIRED0_0 = 124, |
| 116 | IBEX_SPI_HOST0_ERR_IRQ = 131, |
| 117 | IBEX_SPI_HOST0_SPI_EVENT_IRQ = 132, |
| 118 | IBEX_SPI_HOST1_ERR_IRQ = 133, |
| 119 | IBEX_SPI_HOST1_SPI_EVENT_IRQ = 134, |
| 120 | }; |
| 121 | |
| 122 | #endif |