| 1 | /* |
| 2 | * Tenstorrent Atlantis RISC-V System on Chip |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 5 | * |
| 6 | * Copyright 2025 Tenstorrent, Joel Stanley <joel@jms.id.au> |
| 7 | */ |
| 8 | |
| 9 | #ifndef HW_RISCV_TT_ATLANTIS_H |
| 10 | #define HW_RISCV_TT_ATLANTIS_H |
| 11 | |
| 12 | #include "hw/core/boards.h" |
| 13 | #include "hw/core/sysbus.h" |
| 14 | #include "hw/i2c/designware_i2c.h" |
| 15 | #include "hw/intc/riscv_imsic.h" |
| 16 | #include "hw/riscv/riscv_hart.h" |
| 17 | |
| 18 | #define TYPE_TT_ATLANTIS_MACHINE MACHINE_TYPE_NAME("tt-atlantis") |
| 19 | OBJECT_DECLARE_SIMPLE_TYPE(TTAtlantisState, TT_ATLANTIS_MACHINE) |
| 20 | |
| 21 | #define TT_ATL_NUM_I2C 5 |
| 22 | |
| 23 | struct TTAtlantisState { |
| 24 | /*< private >*/ |
| 25 | MachineState parent; |
| 26 | |
| 27 | /*< public >*/ |
| 28 | Notifier machine_done; |
| 29 | const MemMapEntry *memmap; |
| 30 | |
| 31 | RISCVHartArrayState soc; |
| 32 | DeviceState *irqchip; |
| 33 | DesignWareI2CState i2c[TT_ATL_NUM_I2C]; |
| 34 | |
| 35 | int fdt_size; |
| 36 | }; |
| 37 | |
| 38 | enum { |
| 39 | TT_ATL_I2C0_IRQ = 33, |
| 40 | TT_ATL_I2C1_IRQ = 34, |
| 41 | TT_ATL_I2C2_IRQ = 35, |
| 42 | TT_ATL_I2C3_IRQ = 36, |
| 43 | TT_ATL_I2C4_IRQ = 37, |
| 44 | TT_ATL_UART1_IRQ = 39, |
| 45 | }; |
| 46 | |
| 47 | enum { |
| 48 | TT_ATL_ACLINT, |
| 49 | TT_ATL_BOOTROM, |
| 50 | TT_ATL_DDR_LO, |
| 51 | TT_ATL_DDR_HI, |
| 52 | TT_ATL_I2C0, |
| 53 | TT_ATL_I2C1, |
| 54 | TT_ATL_I2C2, |
| 55 | TT_ATL_I2C3, |
| 56 | TT_ATL_I2C4, |
| 57 | TT_ATL_MAPLIC, |
| 58 | TT_ATL_MIMSIC, |
| 59 | TT_ATL_SAPLIC, |
| 60 | TT_ATL_SIMSIC, |
| 61 | TT_ATL_UART1, |
| 62 | }; |
| 63 | |
| 64 | #endif |