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1 /*
2 * QEMU RISC-V VirtIO machine interface
3 *
4 * Copyright (c) 2017 SiFive, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19 #ifndef HW_RISCV_VIRT_H
20 #define HW_RISCV_VIRT_H
21
22 #include "hw/core/boards.h"
23 #include "hw/riscv/riscv_hart.h"
24 #include "hw/core/sysbus.h"
25 #include "hw/block/flash.h"
26 #include "hw/intc/riscv_imsic.h"
27
28 #define VIRT_CPUS_MAX_BITS 9
29 #define VIRT_CPUS_MAX (1 << VIRT_CPUS_MAX_BITS)
30 #define VIRT_SOCKETS_MAX_BITS 2
31 #define VIRT_SOCKETS_MAX (1 << VIRT_SOCKETS_MAX_BITS)
32
33 #define TYPE_RISCV_VIRT_MACHINE MACHINE_TYPE_NAME("virt")
34 typedef struct RISCVVirtState RISCVVirtState;
35 DECLARE_INSTANCE_CHECKER(RISCVVirtState, RISCV_VIRT_MACHINE,
36 TYPE_RISCV_VIRT_MACHINE)
37
38 typedef enum RISCVVirtAIAType {
39 VIRT_AIA_TYPE_NONE = 0,
40 VIRT_AIA_TYPE_APLIC,
41 VIRT_AIA_TYPE_APLIC_IMSIC,
42 } RISCVVirtAIAType;
43
44 struct RISCVVirtState {
45 /*< private >*/
46 MachineState parent;
47
48 /*< public >*/
49 Notifier machine_done;
50 DeviceState *platform_bus_dev;
51 RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
52 DeviceState *irqchip[VIRT_SOCKETS_MAX];
53 PFlashCFI01 *flash[2];
54 FWCfgState *fw_cfg;
55
56 int fdt_size;
57 bool have_aclint;
58 RISCVVirtAIAType aia_type;
59 int aia_guests;
60 char *oem_id;
61 char *oem_table_id;
62 bool uart1_present;
63 OnOffAuto acpi;
64 const MemMapEntry *memmap;
65 struct GPEXHost *gpex_host;
66 OnOffAuto iommu_sys;
67 uint16_t pci_iommu_bdf;
68 uint16_t num_sources;
69 };
70
71 enum {
72 VIRT_DEBUG,
73 VIRT_MROM,
74 VIRT_TEST,
75 VIRT_RTC,
76 VIRT_CLINT,
77 VIRT_ACLINT_SSWI,
78 VIRT_PLIC,
79 VIRT_APLIC_M,
80 VIRT_APLIC_S,
81 VIRT_UART0,
82 VIRT_VIRTIO,
83 VIRT_UART1,
84 VIRT_FW_CFG,
85 VIRT_IMSIC_M,
86 VIRT_IMSIC_S,
87 VIRT_FLASH,
88 VIRT_DRAM,
89 VIRT_PCIE_MMIO,
90 VIRT_PCIE_PIO,
91 VIRT_PLATFORM_BUS,
92 VIRT_PCIE_ECAM,
93 VIRT_IOMMU_SYS,
94 };
95
96 enum {
97 UART0_IRQ = 10,
98 RTC_IRQ = 11,
99 UART1_IRQ = 12,
100 VIRTIO_IRQ = 1, /* 1 to 8 */
101 VIRTIO_COUNT = 8,
102 PCIE_IRQ = 0x20, /* 32 to 35 */
103 IOMMU_SYS_IRQ = 0x24, /* 36-39 */
104 VIRT_PLATFORM_BUS_IRQ = 64, /* 64 to 95 */
105 };
106
107 #define VIRT_PLATFORM_BUS_NUM_IRQS 32
108
109 #define VIRT_IRQCHIP_NUM_MSIS 255
110 #define VIRT_IRQCHIP_NUM_SOURCES 96
111 #define VIRT_IRQCHIP_NUM_PRIO_BITS 3
112 #define VIRT_IRQCHIP_MAX_GUESTS_BITS 3
113 #define VIRT_IRQCHIP_MAX_GUESTS ((1U << VIRT_IRQCHIP_MAX_GUESTS_BITS) - 1U)
114
115 #define VIRT_PLIC_PRIORITY_BASE 0x00
116 #define VIRT_PLIC_PENDING_BASE 0x1000
117 #define VIRT_PLIC_ENABLE_BASE 0x2000
118 #define VIRT_PLIC_ENABLE_STRIDE 0x80
119 #define VIRT_PLIC_CONTEXT_BASE 0x200000
120 #define VIRT_PLIC_CONTEXT_STRIDE 0x1000
121 #define VIRT_PLIC_SIZE(__num_context) \
122 (VIRT_PLIC_CONTEXT_BASE + (__num_context) * VIRT_PLIC_CONTEXT_STRIDE)
123
124 #define FDT_PCI_ADDR_CELLS 3
125 #define FDT_PCI_INT_CELLS 1
126 #define FDT_PLIC_ADDR_CELLS 0
127 #define FDT_PLIC_INT_CELLS 1
128 #define FDT_APLIC_INT_CELLS 2
129 #define FDT_APLIC_ADDR_CELLS 0
130 #define FDT_IMSIC_INT_CELLS 0
131 #define FDT_MAX_INT_CELLS 2
132 #define FDT_MAX_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \
133 1 + FDT_MAX_INT_CELLS)
134 #define FDT_PLIC_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \
135 1 + FDT_PLIC_INT_CELLS)
136 #define FDT_APLIC_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \
137 1 + FDT_APLIC_INT_CELLS)
138
139 bool virt_is_acpi_enabled(RISCVVirtState *s);
140 bool virt_is_iommu_sys_enabled(RISCVVirtState *s);
141 void virt_acpi_setup(RISCVVirtState *vms);
142
143 /*
144 * The virt machine physical address space used by some of the devices
145 * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets,
146 * number of CPUs, and number of IMSIC guest files.
147 *
148 * Various limits defined by VIRT_SOCKETS_MAX_BITS, VIRT_CPUS_MAX_BITS,
149 * and VIRT_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization
150 * of virt machine physical address space.
151 */
152
153 #define VIRT_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHIFT)
154 #if VIRT_IMSIC_GROUP_MAX_SIZE < \
155 IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS)
156 #error "Can't accommodate single IMSIC group in address space"
157 #endif
158
159 #define VIRT_IMSIC_MAX_SIZE (VIRT_SOCKETS_MAX * \
160 VIRT_IMSIC_GROUP_MAX_SIZE)
161 #if 0x4000000 < VIRT_IMSIC_MAX_SIZE
162 #error "Can't accommodate all IMSIC groups in address space"
163 #endif
164
165 #endif