| 1 | /* |
| 2 | * Allwinner (sun4i and above) SD Host Controller emulation |
| 3 | * |
| 4 | * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> |
| 5 | * |
| 6 | * This program is free software: you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation, either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #ifndef HW_SD_ALLWINNER_SDHOST_H |
| 21 | #define HW_SD_ALLWINNER_SDHOST_H |
| 22 | |
| 23 | #include "qom/object.h" |
| 24 | #include "hw/core/sysbus.h" |
| 25 | #include "hw/sd/sd.h" |
| 26 | |
| 27 | /** |
| 28 | * Object model types |
| 29 | * @{ |
| 30 | */ |
| 31 | |
| 32 | /** Generic Allwinner SD Host Controller (abstract) */ |
| 33 | #define TYPE_AW_SDHOST "allwinner-sdhost" |
| 34 | |
| 35 | /** Allwinner sun4i family (A10, A12) */ |
| 36 | #define TYPE_AW_SDHOST_SUN4I TYPE_AW_SDHOST "-sun4i" |
| 37 | |
| 38 | /** Allwinner sun5i family and newer (A13, H2+, H3, etc) */ |
| 39 | #define TYPE_AW_SDHOST_SUN5I TYPE_AW_SDHOST "-sun5i" |
| 40 | |
| 41 | /** Allwinner sun50i-a64 */ |
| 42 | #define TYPE_AW_SDHOST_SUN50I_A64 TYPE_AW_SDHOST "-sun50i-a64" |
| 43 | |
| 44 | /** Allwinner sun50i-a64 emmc */ |
| 45 | #define TYPE_AW_SDHOST_SUN50I_A64_EMMC TYPE_AW_SDHOST "-sun50i-a64-emmc" |
| 46 | |
| 47 | /** @} */ |
| 48 | |
| 49 | /** |
| 50 | * Object model macros |
| 51 | * @{ |
| 52 | */ |
| 53 | |
| 54 | OBJECT_DECLARE_TYPE(AwSdHostState, AwSdHostClass, AW_SDHOST) |
| 55 | |
| 56 | /** @} */ |
| 57 | |
| 58 | /** |
| 59 | * Allwinner SD Host Controller object instance state. |
| 60 | */ |
| 61 | struct AwSdHostState { |
| 62 | /*< private >*/ |
| 63 | SysBusDevice busdev; |
| 64 | /*< public >*/ |
| 65 | |
| 66 | /** Secure Digital (SD) bus, which connects to SD card (if present) */ |
| 67 | SDBus sdbus; |
| 68 | |
| 69 | /** Maps I/O registers in physical memory */ |
| 70 | MemoryRegion iomem; |
| 71 | |
| 72 | /** Interrupt output signal to notify CPU */ |
| 73 | qemu_irq irq; |
| 74 | |
| 75 | /** Memory region where DMA transfers are done */ |
| 76 | MemoryRegion *dma_mr; |
| 77 | |
| 78 | /** Address space used internally for DMA transfers */ |
| 79 | AddressSpace dma_as; |
| 80 | |
| 81 | /** Number of bytes left in current DMA transfer */ |
| 82 | uint32_t transfer_cnt; |
| 83 | |
| 84 | /** |
| 85 | * @name Hardware Registers |
| 86 | * @{ |
| 87 | */ |
| 88 | |
| 89 | uint32_t global_ctl; /**< Global Control */ |
| 90 | uint32_t clock_ctl; /**< Clock Control */ |
| 91 | uint32_t timeout; /**< Timeout */ |
| 92 | uint32_t bus_width; /**< Bus Width */ |
| 93 | uint32_t block_size; /**< Block Size */ |
| 94 | uint32_t byte_count; /**< Byte Count */ |
| 95 | |
| 96 | uint32_t command; /**< Command */ |
| 97 | uint32_t command_arg; /**< Command Argument */ |
| 98 | uint32_t response[4]; /**< Command Response */ |
| 99 | |
| 100 | uint32_t irq_mask; /**< Interrupt Mask */ |
| 101 | uint32_t irq_status; /**< Raw Interrupt Status */ |
| 102 | uint32_t status; /**< Status */ |
| 103 | |
| 104 | uint32_t fifo_wlevel; /**< FIFO Water Level */ |
| 105 | uint32_t fifo_func_sel; /**< FIFO Function Select */ |
| 106 | uint32_t debug_enable; /**< Debug Enable */ |
| 107 | uint32_t auto12_arg; /**< Auto Command 12 Argument */ |
| 108 | uint32_t newtiming_set; /**< SD New Timing Set */ |
| 109 | uint32_t newtiming_debug; /**< SD New Timing Debug */ |
| 110 | uint32_t hardware_rst; /**< Hardware Reset */ |
| 111 | uint32_t dmac; /**< Internal DMA Controller Control */ |
| 112 | uint32_t desc_base; /**< Descriptor List Base Address */ |
| 113 | uint32_t dmac_status; /**< Internal DMA Controller Status */ |
| 114 | uint32_t dmac_irq; /**< Internal DMA Controller IRQ Enable */ |
| 115 | uint32_t card_threshold; /**< Card Threshold Control */ |
| 116 | uint32_t startbit_detect; /**< eMMC DDR Start Bit Detection Control */ |
| 117 | uint32_t response_crc; /**< Response CRC */ |
| 118 | uint32_t data_crc[8]; /**< Data CRC */ |
| 119 | uint32_t sample_delay; /**< Sample delay control */ |
| 120 | uint32_t status_crc; /**< Status CRC */ |
| 121 | |
| 122 | /** @} */ |
| 123 | |
| 124 | }; |
| 125 | |
| 126 | /** |
| 127 | * Allwinner SD Host Controller class-level struct. |
| 128 | * |
| 129 | * This struct is filled by each sunxi device specific code |
| 130 | * such that the generic code can use this struct to support |
| 131 | * all devices. |
| 132 | */ |
| 133 | struct AwSdHostClass { |
| 134 | /*< private >*/ |
| 135 | SysBusDeviceClass parent_class; |
| 136 | /*< public >*/ |
| 137 | |
| 138 | /** Maximum buffer size in bytes per DMA descriptor */ |
| 139 | size_t max_desc_size; |
| 140 | bool is_sun4i; |
| 141 | |
| 142 | /** does the IP block support autocalibration? */ |
| 143 | bool can_calibrate; |
| 144 | }; |
| 145 | |
| 146 | #endif /* HW_SD_ALLWINNER_SDHOST_H */ |