| 1 | /* |
| 2 | * QEMU PIIX South Bridge Emulation |
| 3 | * |
| 4 | * Copyright (c) 2006 Fabrice Bellard |
| 5 | * Copyright (c) 2018 Hervé Poussineau |
| 6 | * |
| 7 | * This work is licensed under the terms of the GNU GPL, version 2 or later. |
| 8 | * See the COPYING file in the top-level directory. |
| 9 | * |
| 10 | */ |
| 11 | |
| 12 | #ifndef HW_SOUTHBRIDGE_PIIX_H |
| 13 | #define HW_SOUTHBRIDGE_PIIX_H |
| 14 | |
| 15 | #include "hw/pci/pci_device.h" |
| 16 | #include "hw/acpi/piix4.h" |
| 17 | #include "hw/ide/pci.h" |
| 18 | #include "hw/rtc/mc146818rtc.h" |
| 19 | #include "hw/usb/hcd-uhci.h" |
| 20 | #include "hw/core/irq.h" |
| 21 | |
| 22 | /* PIRQRC[A:D]: PIRQx Route Control Registers */ |
| 23 | #define PIIX_PIRQCA 0x60 |
| 24 | #define PIIX_PIRQCB 0x61 |
| 25 | #define PIIX_PIRQCC 0x62 |
| 26 | #define PIIX_PIRQCD 0x63 |
| 27 | |
| 28 | /* |
| 29 | * Reset Control Register: PCI-accessible ISA-Compatible Register at address |
| 30 | * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000). |
| 31 | */ |
| 32 | #define PIIX_RCR_IOPORT 0xcf9 |
| 33 | |
| 34 | #define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */ |
| 35 | |
| 36 | struct PIIXState { |
| 37 | PCIDevice dev; |
| 38 | |
| 39 | /* |
| 40 | * bitmap to track pic levels. |
| 41 | * The pic level is the logical OR of all the PCI irqs mapped to it |
| 42 | * So one PIC level is tracked by PIIX_NUM_PIRQS bits. |
| 43 | * |
| 44 | * PIRQ is mapped to PIC pins, we track it by |
| 45 | * PIIX_NUM_PIRQS * ISA_NUM_IRQS = 64 bits with |
| 46 | * pic_irq * PIIX_NUM_PIRQS + pirq |
| 47 | */ |
| 48 | #if ISA_NUM_IRQS * PIIX_NUM_PIRQS > 64 |
| 49 | #error "unable to encode pic state in 64bit in pic_levels." |
| 50 | #endif |
| 51 | uint64_t pic_levels; |
| 52 | |
| 53 | qemu_irq cpu_intr; |
| 54 | qemu_irq isa_irqs_in[ISA_NUM_IRQS]; |
| 55 | |
| 56 | IRQState i8259_irq; |
| 57 | |
| 58 | /* This member isn't used. Just for save/load compatibility */ |
| 59 | int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; |
| 60 | |
| 61 | MC146818RtcState rtc; |
| 62 | PCIIDEState ide; |
| 63 | UHCIState uhci; |
| 64 | PIIX4PMState pm; |
| 65 | |
| 66 | uint32_t smb_io_base; |
| 67 | |
| 68 | /* Reset Control Register contents */ |
| 69 | uint8_t rcr; |
| 70 | |
| 71 | /* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */ |
| 72 | MemoryRegion rcr_mem; |
| 73 | |
| 74 | bool has_acpi; |
| 75 | bool has_pic; |
| 76 | bool has_pit; |
| 77 | bool has_usb; |
| 78 | bool smm_enabled; |
| 79 | }; |
| 80 | |
| 81 | #define TYPE_PIIX_PCI_DEVICE "pci-piix" |
| 82 | OBJECT_DECLARE_SIMPLE_TYPE(PIIXState, PIIX_PCI_DEVICE) |
| 83 | |
| 84 | #define TYPE_PIIX3_DEVICE "PIIX3" |
| 85 | #define TYPE_PIIX4_PCI_DEVICE "piix4-isa" |
| 86 | |
| 87 | #endif |