| 1 | /* |
| 2 | * QEMU PowerPC SPI model |
| 3 | * |
| 4 | * Copyright (c) 2024, IBM Corporation. |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 7 | * |
| 8 | * This model Supports a connection to a single SPI responder. |
| 9 | * Introduced for P10 to provide access to SPI seeproms, TPM, flash device |
| 10 | * and an ADC controller. |
| 11 | * |
| 12 | * All SPI function control is mapped into the SPI register space to enable |
| 13 | * full control by firmware. |
| 14 | * |
| 15 | * SPI Controller has sequencer and shift engine. The SPI shift engine |
| 16 | * performs serialization and de-serialization according to the control by |
| 17 | * the sequencer and according to the setup defined in the configuration |
| 18 | * registers and the SPI sequencer implements the main control logic. |
| 19 | */ |
| 20 | |
| 21 | #ifndef PPC_PNV_SPI_H |
| 22 | #define PPC_PNV_SPI_H |
| 23 | |
| 24 | #include "hw/ssi/ssi.h" |
| 25 | #include "hw/core/sysbus.h" |
| 26 | #include "qemu/fifo8.h" |
| 27 | |
| 28 | #define TYPE_PNV_SPI "pnv-spi" |
| 29 | OBJECT_DECLARE_SIMPLE_TYPE(PnvSpi, PNV_SPI) |
| 30 | |
| 31 | #define PNV_SPI_REG_SIZE 8 |
| 32 | #define PNV_SPI_REGS 7 |
| 33 | |
| 34 | #define TYPE_PNV_SPI_BUS "spi" |
| 35 | typedef struct PnvSpi { |
| 36 | SysBusDevice parent_obj; |
| 37 | |
| 38 | SSIBus *ssi_bus; |
| 39 | qemu_irq *cs_line; |
| 40 | MemoryRegion xscom_spic_regs; |
| 41 | Fifo8 tx_fifo; |
| 42 | Fifo8 rx_fifo; |
| 43 | uint8_t fail_count; /* RDR Match failure counter */ |
| 44 | /* SPI object number */ |
| 45 | uint32_t spic_num; |
| 46 | uint32_t chip_id; |
| 47 | uint8_t transfer_len; |
| 48 | uint8_t responder_select; |
| 49 | /* To verify if shift_n1 happens prior to shift_n2 */ |
| 50 | bool shift_n1_done; |
| 51 | /* Loop counter for branch operation opcode Ex/Fx */ |
| 52 | uint8_t loop_counter_1; |
| 53 | uint8_t loop_counter_2; |
| 54 | /* N1/N2_bits specifies the size of the N1/N2 segment of a frame in bits.*/ |
| 55 | uint8_t N1_bits; |
| 56 | uint8_t N2_bits; |
| 57 | /* Number of bytes in a payload for the N1/N2 frame segment.*/ |
| 58 | uint8_t N1_bytes; |
| 59 | uint8_t N2_bytes; |
| 60 | /* Number of N1/N2 bytes marked for transmit */ |
| 61 | uint8_t N1_tx; |
| 62 | uint8_t N2_tx; |
| 63 | /* Number of N1/N2 bytes marked for receive */ |
| 64 | uint8_t N1_rx; |
| 65 | uint8_t N2_rx; |
| 66 | |
| 67 | /* SPI registers */ |
| 68 | uint64_t regs[PNV_SPI_REGS]; |
| 69 | uint8_t seq_op[PNV_SPI_REG_SIZE]; |
| 70 | uint64_t status; |
| 71 | } PnvSpi; |
| 72 | #endif /* PPC_PNV_SPI_H */ |