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1 /*
2 * K230 Watchdog Timer
3 *
4 * K230 Technical Reference Manual V0.3.1 (2024-11-18):
5 * https://github.com/revyos/external-docs/blob/master/K230/en-us/K230_Technical_Reference_Manual_V0.3.1_20241118.pdf
6 *
7 * Copyright (c) 2025 Mig Yang <temashking@foxmail.com>
8 * Copyright (c) 2025 Chao Liu <chao.liu.zevorn@gmail.com>
9 *
10 * SPDX-License-Identifier: GPL-2.0-or-later
11 */
12
13 #ifndef K230_WDT_H
14 #define K230_WDT_H
15
16 #include "qemu/bitops.h"
17 #include "hw/core/sysbus.h"
18 #include "hw/core/irq.h"
19 #include "hw/core/ptimer.h"
20 #include "qom/object.h"
21
22 #define TYPE_K230_WDT "riscv.k230.wdt"
23 OBJECT_DECLARE_SIMPLE_TYPE(K230WdtState, K230_WDT)
24
25 #define K230_WDT_DEFAULT_FREQ (32768)
26
27 /* K230 Watchdog Register Map */
28 enum K230WdtRegisters {
29 K230_WDT_CR = 0x00, /* Control Register */
30 K230_WDT_TORR = 0x04, /* Timeout Range Register */
31 K230_WDT_CCVR = 0x08, /* Current Counter Value Register */
32 K230_WDT_CRR = 0x0c, /* Counter Restart Register */
33 K230_WDT_STAT = 0x10, /* Interrupt Status Register */
34 K230_WDT_EOI = 0x14, /* Interrupt Clear Register */
35 K230_WDT_PROT_LEVEL = 0x1c, /* Protection Level Register */
36 K230_WDT_COMP_PARAM_5 = 0xe4, /* Component Parameters Register 5 */
37 K230_WDT_COMP_PARAM_4 = 0xe8, /* Component Parameters Register 4 */
38 K230_WDT_COMP_PARAM_3 = 0xec, /* Component Parameters Register 3 */
39 K230_WDT_COMP_PARAM_2 = 0xf0, /* Component Parameters Register 2 */
40 K230_WDT_COMP_PARAM_1 = 0xf4, /* Component Parameters Register 1 */
41 K230_WDT_COMP_VERSION = 0xf8, /* Component Version Register */
42 K230_WDT_COMP_TYPE = 0xfc, /* Component Type Register */
43 };
44
45 #define K230_WDT_MMIO_SIZE 0x100
46
47 /* Control Register (WDT_CR) definitions */
48 #define K230_WDT_CR_RPL_MASK 0x7 /* Reset Pulse Length */
49 #define K230_WDT_CR_RPL_SHIFT 2
50 #define K230_WDT_CR_RMOD BIT(1) /* Response Mode */
51 #define K230_WDT_CR_WDT_EN BIT(0) /* Watchdog Enable */
52
53 /* Reset Pulse Length values */
54 #define K230_WDT_RPL_2_CYCLES 0x0
55 #define K230_WDT_RPL_4_CYCLES 0x1
56 #define K230_WDT_RPL_8_CYCLES 0x2
57 #define K230_WDT_RPL_16_CYCLES 0x3
58 #define K230_WDT_RPL_32_CYCLES 0x4
59 #define K230_WDT_RPL_64_CYCLES 0x5
60 #define K230_WDT_RPL_128_CYCLES 0x6
61 #define K230_WDT_RPL_256_CYCLES 0x7
62
63 /* Timeout Range Register (WDT_TORR) definitions */
64 #define K230_WDT_TORR_TOP_MASK 0xf /* Timeout Period */
65
66 /* Interrupt Status Register (WDT_STAT) definitions */
67 #define K230_WDT_STAT_INT BIT(0) /* Interrupt Status */
68
69 /* Counter Restart Register (WDT_CRR) magic value */
70 #define K230_WDT_CRR_RESTART 0x76 /* Restart command */
71
72 /* Component Parameters Register 1 (WDT_COMP_PARAM_1) definitions */
73 #define K230_WDT_CNT_WIDTH_MASK 0x1f000000 /* Counter Width */
74 #define K230_WDT_CNT_WIDTH_SHIFT 24
75 #define K230_WDT_DFLT_TOP_INIT_MASK 0xf00000 /* Default Initial Timeout */
76 #define K230_WDT_DFLT_TOP_INIT_SHIFT 20
77 #define K230_WDT_DFLT_TOP_MASK 0xf0000 /* Default Timeout */
78 #define K230_WDT_DFLT_TOP_SHIFT 16
79 #define K230_WDT_DFLT_RPL_MASK 0x7 /* Default Reset Pulse Length */
80 #define K230_WDT_DFLT_RPL_SHIFT 10
81 #define K230_WDT_APB_DATA_WIDTH_MASK 0x3 /* APB Data Width */
82 #define K230_WDT_APB_DATA_WIDTH_SHIFT 8
83 #define K230_WDT_USE_FIX_TOP BIT(6) /* Use Fixed Timeout Values */
84 #define K230_WDT_HC_TOP BIT(5) /* Hard-coded Timeout */
85 #define K230_WDT_HC_RPL BIT(4) /* Hard-coded Reset Pulse Length */
86 #define K230_WDT_HC_RMOD BIT(3) /* Hard-coded Response Mode */
87 #define K230_WDT_DUAL_TOP BIT(2) /* Dual Timeout Period */
88 #define K230_WDT_DFLT_RMOD BIT(1) /* Default Response Mode */
89 #define K230_WDT_ALWAYS_EN BIT(0) /* Always Enabled */
90
91 /* Component Type Register value */
92 #define K230_WDT_COMP_TYPE_VAL 0x44570120
93
94 /* Component Version Register value */
95 #define K230_WDT_COMP_VERSION_VAL 0x3131302a /* "110*" */
96
97 struct K230WdtState {
98 /* <private> */
99 SysBusDevice parent_obj;
100
101 /*< public >*/
102 MemoryRegion mmio;
103 qemu_irq irq;
104
105 struct ptimer_state *timer;
106
107 /* Register state */
108 uint32_t cr; /* Control Register */
109 uint32_t torr; /* Timeout Range Register */
110 uint32_t ccvr; /* Current Counter Value Register */
111 uint32_t stat; /* Interrupt Status Register */
112 uint32_t prot_level; /* Protection Level Register */
113
114 /* Internal state */
115 bool interrupt_pending;
116 bool enabled;
117 uint32_t timeout_value;
118 uint32_t current_count;
119 };
120
121 #endif /* K230_WDT_H */