| 1 | /* |
| 2 | * Copyright (c) 2017, Impinj, Inc. |
| 3 | * |
| 4 | * i.MX2 Watchdog IP block |
| 5 | * |
| 6 | * Author: Andrey Smirnov <andrew.smirnov@gmail.com> |
| 7 | * |
| 8 | * This work is licensed under the terms of the GNU GPL, version 2 or later. |
| 9 | * See the COPYING file in the top-level directory. |
| 10 | */ |
| 11 | |
| 12 | #ifndef WDT_IMX2_H |
| 13 | #define WDT_IMX2_H |
| 14 | |
| 15 | #include "qemu/bitops.h" |
| 16 | #include "hw/core/sysbus.h" |
| 17 | #include "hw/core/irq.h" |
| 18 | #include "hw/core/ptimer.h" |
| 19 | #include "qom/object.h" |
| 20 | |
| 21 | #define TYPE_IMX2_WDT "imx2.wdt" |
| 22 | OBJECT_DECLARE_SIMPLE_TYPE(IMX2WdtState, IMX2_WDT) |
| 23 | |
| 24 | enum IMX2WdtRegisters { |
| 25 | IMX2_WDT_WCR = 0x0000, /* Control Register */ |
| 26 | IMX2_WDT_WSR = 0x0002, /* Service Register */ |
| 27 | IMX2_WDT_WRSR = 0x0004, /* Reset Status Register */ |
| 28 | IMX2_WDT_WICR = 0x0006, /* Interrupt Control Register */ |
| 29 | IMX2_WDT_WMCR = 0x0008, /* Misc Register */ |
| 30 | }; |
| 31 | |
| 32 | #define IMX2_WDT_MMIO_SIZE 0x000a |
| 33 | |
| 34 | /* Control Register definitions */ |
| 35 | #define IMX2_WDT_WCR_WT (0xFF << 8) /* Watchdog Timeout Field */ |
| 36 | #define IMX2_WDT_WCR_WDW BIT(7) /* WDOG Disable for Wait */ |
| 37 | #define IMX2_WDT_WCR_WDA BIT(5) /* WDOG Assertion */ |
| 38 | #define IMX2_WDT_WCR_SRS BIT(4) /* Software Reset Signal */ |
| 39 | #define IMX2_WDT_WCR_WDT BIT(3) /* WDOG Timeout Assertion */ |
| 40 | #define IMX2_WDT_WCR_WDE BIT(2) /* Watchdog Enable */ |
| 41 | #define IMX2_WDT_WCR_WDBG BIT(1) /* Watchdog Debug Enable */ |
| 42 | #define IMX2_WDT_WCR_WDZST BIT(0) /* Watchdog Timer Suspend */ |
| 43 | |
| 44 | #define IMX2_WDT_WCR_LOCK_MASK (IMX2_WDT_WCR_WDZST | IMX2_WDT_WCR_WDBG \ |
| 45 | | IMX2_WDT_WCR_WDW) |
| 46 | |
| 47 | /* Service Register definitions */ |
| 48 | #define IMX2_WDT_SEQ1 0x5555 /* service sequence 1 */ |
| 49 | #define IMX2_WDT_SEQ2 0xAAAA /* service sequence 2 */ |
| 50 | |
| 51 | /* Reset Status Register definitions */ |
| 52 | #define IMX2_WDT_WRSR_TOUT BIT(1) /* Reset due to Timeout */ |
| 53 | #define IMX2_WDT_WRSR_SFTW BIT(0) /* Reset due to software reset */ |
| 54 | |
| 55 | /* Interrupt Control Register definitions */ |
| 56 | #define IMX2_WDT_WICR_WIE BIT(15) /* Interrupt Enable */ |
| 57 | #define IMX2_WDT_WICR_WTIS BIT(14) /* Interrupt Status */ |
| 58 | #define IMX2_WDT_WICR_WICT 0xff /* Interrupt Timeout */ |
| 59 | #define IMX2_WDT_WICR_WICT_DEF 0x04 /* Default interrupt timeout (2s) */ |
| 60 | |
| 61 | #define IMX2_WDT_WICR_LOCK_MASK (IMX2_WDT_WICR_WIE | IMX2_WDT_WICR_WICT) |
| 62 | |
| 63 | /* Misc Control Register definitions */ |
| 64 | #define IMX2_WDT_WMCR_PDE BIT(0) /* Power-Down Enable */ |
| 65 | |
| 66 | struct IMX2WdtState { |
| 67 | /* <private> */ |
| 68 | SysBusDevice parent_obj; |
| 69 | |
| 70 | /*< public >*/ |
| 71 | MemoryRegion mmio; |
| 72 | qemu_irq irq; |
| 73 | |
| 74 | struct ptimer_state *timer; |
| 75 | struct ptimer_state *itimer; |
| 76 | |
| 77 | bool pretimeout_support; |
| 78 | bool wicr_locked; |
| 79 | |
| 80 | uint16_t wcr; |
| 81 | uint16_t wsr; |
| 82 | uint16_t wrsr; |
| 83 | uint16_t wicr; |
| 84 | uint16_t wmcr; |
| 85 | |
| 86 | bool wcr_locked; /* affects WDZST, WDBG, and WDW */ |
| 87 | bool wcr_wde_locked; /* affects WDE */ |
| 88 | bool wcr_wdt_locked; /* affects WDT (never cleared) */ |
| 89 | }; |
| 90 | |
| 91 | #endif /* WDT_IMX2_H */ |