| 1 | /* SPDX-License-Identifier: MIT */ |
| 2 | /****************************************************************************** |
| 3 | * xen.h |
| 4 | * |
| 5 | * Guest OS interface to Xen. |
| 6 | * |
| 7 | * Copyright (c) 2004, K A Fraser |
| 8 | */ |
| 9 | |
| 10 | #ifndef __XEN_PUBLIC_XEN_H__ |
| 11 | #define __XEN_PUBLIC_XEN_H__ |
| 12 | |
| 13 | #include "xen-compat.h" |
| 14 | |
| 15 | #if defined(__i386__) || defined(__x86_64__) |
| 16 | #include "arch-x86/xen.h" |
| 17 | #elif defined(__arm__) || defined (__aarch64__) |
| 18 | #include "arch-arm.h" |
| 19 | #else |
| 20 | #error "Unsupported architecture" |
| 21 | #endif |
| 22 | |
| 23 | #ifndef __ASSEMBLY__ |
| 24 | /* Guest handles for primitive C types. */ |
| 25 | DEFINE_XEN_GUEST_HANDLE(char); |
| 26 | __DEFINE_XEN_GUEST_HANDLE(uchar, unsigned char); |
| 27 | DEFINE_XEN_GUEST_HANDLE(int); |
| 28 | __DEFINE_XEN_GUEST_HANDLE(uint, unsigned int); |
| 29 | #if __XEN_INTERFACE_VERSION__ < 0x00040300 |
| 30 | DEFINE_XEN_GUEST_HANDLE(long); |
| 31 | __DEFINE_XEN_GUEST_HANDLE(ulong, unsigned long); |
| 32 | #endif |
| 33 | DEFINE_XEN_GUEST_HANDLE(void); |
| 34 | |
| 35 | DEFINE_XEN_GUEST_HANDLE(uint64_t); |
| 36 | DEFINE_XEN_GUEST_HANDLE(xen_pfn_t); |
| 37 | DEFINE_XEN_GUEST_HANDLE(xen_ulong_t); |
| 38 | |
| 39 | /* Turn a plain number into a C unsigned (long (long)) constant. */ |
| 40 | #define __xen_mk_uint(x) x ## U |
| 41 | #define __xen_mk_ulong(x) x ## UL |
| 42 | #ifndef __xen_mk_ullong |
| 43 | # define __xen_mk_ullong(x) x ## ULL |
| 44 | #endif |
| 45 | #define xen_mk_uint(x) __xen_mk_uint(x) |
| 46 | #define xen_mk_ulong(x) __xen_mk_ulong(x) |
| 47 | #define xen_mk_ullong(x) __xen_mk_ullong(x) |
| 48 | |
| 49 | #else |
| 50 | |
| 51 | /* In assembly code we cannot use C numeric constant suffixes. */ |
| 52 | #define xen_mk_uint(x) x |
| 53 | #define xen_mk_ulong(x) x |
| 54 | #define xen_mk_ullong(x) x |
| 55 | |
| 56 | #endif |
| 57 | |
| 58 | /* |
| 59 | * HYPERCALLS |
| 60 | */ |
| 61 | |
| 62 | /* `incontents 100 hcalls List of hypercalls |
| 63 | * ` enum hypercall_num { // __HYPERVISOR_* => HYPERVISOR_*() |
| 64 | */ |
| 65 | |
| 66 | #define __HYPERVISOR_set_trap_table 0 |
| 67 | #define __HYPERVISOR_mmu_update 1 |
| 68 | #define __HYPERVISOR_set_gdt 2 |
| 69 | #define __HYPERVISOR_stack_switch 3 |
| 70 | #define __HYPERVISOR_set_callbacks 4 |
| 71 | #define __HYPERVISOR_fpu_taskswitch 5 |
| 72 | #define __HYPERVISOR_sched_op_compat 6 /* compat since 0x00030101 */ |
| 73 | #define __HYPERVISOR_platform_op 7 |
| 74 | #define __HYPERVISOR_set_debugreg 8 |
| 75 | #define __HYPERVISOR_get_debugreg 9 |
| 76 | #define __HYPERVISOR_update_descriptor 10 |
| 77 | #define __HYPERVISOR_memory_op 12 |
| 78 | #define __HYPERVISOR_multicall 13 |
| 79 | #define __HYPERVISOR_update_va_mapping 14 |
| 80 | #define __HYPERVISOR_set_timer_op 15 |
| 81 | #define __HYPERVISOR_event_channel_op_compat 16 /* compat since 0x00030202 */ |
| 82 | #define __HYPERVISOR_xen_version 17 |
| 83 | #define __HYPERVISOR_console_io 18 |
| 84 | #define __HYPERVISOR_physdev_op_compat 19 /* compat since 0x00030202 */ |
| 85 | #define __HYPERVISOR_grant_table_op 20 |
| 86 | #define __HYPERVISOR_vm_assist 21 |
| 87 | #define __HYPERVISOR_update_va_mapping_otherdomain 22 |
| 88 | #define __HYPERVISOR_iret 23 /* x86 only */ |
| 89 | #define __HYPERVISOR_vcpu_op 24 |
| 90 | #define __HYPERVISOR_set_segment_base 25 /* x86/64 only */ |
| 91 | #define __HYPERVISOR_mmuext_op 26 |
| 92 | #define __HYPERVISOR_xsm_op 27 |
| 93 | #define __HYPERVISOR_nmi_op 28 |
| 94 | #define __HYPERVISOR_sched_op 29 |
| 95 | #define __HYPERVISOR_callback_op 30 |
| 96 | #define __HYPERVISOR_xenoprof_op 31 |
| 97 | #define __HYPERVISOR_event_channel_op 32 |
| 98 | #define __HYPERVISOR_physdev_op 33 |
| 99 | #define __HYPERVISOR_hvm_op 34 |
| 100 | #define __HYPERVISOR_sysctl 35 |
| 101 | #define __HYPERVISOR_domctl 36 |
| 102 | #define __HYPERVISOR_kexec_op 37 |
| 103 | #define __HYPERVISOR_tmem_op 38 |
| 104 | #define __HYPERVISOR_argo_op 39 |
| 105 | #define __HYPERVISOR_xenpmu_op 40 |
| 106 | #define __HYPERVISOR_dm_op 41 |
| 107 | #define __HYPERVISOR_hypfs_op 42 |
| 108 | |
| 109 | /* Architecture-specific hypercall definitions. */ |
| 110 | #define __HYPERVISOR_arch_0 48 |
| 111 | #define __HYPERVISOR_arch_1 49 |
| 112 | #define __HYPERVISOR_arch_2 50 |
| 113 | #define __HYPERVISOR_arch_3 51 |
| 114 | #define __HYPERVISOR_arch_4 52 |
| 115 | #define __HYPERVISOR_arch_5 53 |
| 116 | #define __HYPERVISOR_arch_6 54 |
| 117 | #define __HYPERVISOR_arch_7 55 |
| 118 | |
| 119 | /* ` } */ |
| 120 | |
| 121 | /* |
| 122 | * HYPERCALL COMPATIBILITY. |
| 123 | */ |
| 124 | |
| 125 | /* New sched_op hypercall introduced in 0x00030101. */ |
| 126 | #if __XEN_INTERFACE_VERSION__ < 0x00030101 |
| 127 | #undef __HYPERVISOR_sched_op |
| 128 | #define __HYPERVISOR_sched_op __HYPERVISOR_sched_op_compat |
| 129 | #endif |
| 130 | |
| 131 | /* New event-channel and physdev hypercalls introduced in 0x00030202. */ |
| 132 | #if __XEN_INTERFACE_VERSION__ < 0x00030202 |
| 133 | #undef __HYPERVISOR_event_channel_op |
| 134 | #define __HYPERVISOR_event_channel_op __HYPERVISOR_event_channel_op_compat |
| 135 | #undef __HYPERVISOR_physdev_op |
| 136 | #define __HYPERVISOR_physdev_op __HYPERVISOR_physdev_op_compat |
| 137 | #endif |
| 138 | |
| 139 | /* New platform_op hypercall introduced in 0x00030204. */ |
| 140 | #if __XEN_INTERFACE_VERSION__ < 0x00030204 |
| 141 | #define __HYPERVISOR_dom0_op __HYPERVISOR_platform_op |
| 142 | #endif |
| 143 | |
| 144 | /* |
| 145 | * VIRTUAL INTERRUPTS |
| 146 | * |
| 147 | * Virtual interrupts that a guest OS may receive from Xen. |
| 148 | * |
| 149 | * In the side comments, 'V.' denotes a per-VCPU VIRQ while 'G.' denotes a |
| 150 | * global VIRQ. The former can be bound once per VCPU and cannot be re-bound. |
| 151 | * The latter can be allocated only once per guest: they must initially be |
| 152 | * allocated to VCPU0 but can subsequently be re-bound. |
| 153 | */ |
| 154 | /* ` enum virq { */ |
| 155 | #define VIRQ_TIMER 0 /* V. Timebase update, and/or requested timeout. */ |
| 156 | #define VIRQ_DEBUG 1 /* V. Request guest to dump debug info. */ |
| 157 | #define VIRQ_CONSOLE 2 /* G. (DOM0) Bytes received on emergency console. */ |
| 158 | #define VIRQ_DOM_EXC 3 /* G. (DOM0) Exceptional event for some domain. */ |
| 159 | #define VIRQ_TBUF 4 /* G. (DOM0) Trace buffer has records available. */ |
| 160 | #define VIRQ_DEBUGGER 6 /* G. (DOM0) A domain has paused for debugging. */ |
| 161 | #define VIRQ_XENOPROF 7 /* V. XenOprofile interrupt: new sample available */ |
| 162 | #define VIRQ_CON_RING 8 /* G. (DOM0) Bytes received on console */ |
| 163 | #define VIRQ_PCPU_STATE 9 /* G. (DOM0) PCPU state changed */ |
| 164 | #define VIRQ_MEM_EVENT 10 /* G. (DOM0) A memory event has occurred */ |
| 165 | #define VIRQ_ARGO 11 /* G. Argo interdomain message notification */ |
| 166 | #define VIRQ_ENOMEM 12 /* G. (DOM0) Low on heap memory */ |
| 167 | #define VIRQ_XENPMU 13 /* V. PMC interrupt */ |
| 168 | |
| 169 | /* Architecture-specific VIRQ definitions. */ |
| 170 | #define VIRQ_ARCH_0 16 |
| 171 | #define VIRQ_ARCH_1 17 |
| 172 | #define VIRQ_ARCH_2 18 |
| 173 | #define VIRQ_ARCH_3 19 |
| 174 | #define VIRQ_ARCH_4 20 |
| 175 | #define VIRQ_ARCH_5 21 |
| 176 | #define VIRQ_ARCH_6 22 |
| 177 | #define VIRQ_ARCH_7 23 |
| 178 | /* ` } */ |
| 179 | |
| 180 | #define NR_VIRQS 24 |
| 181 | |
| 182 | /* |
| 183 | * ` enum neg_errnoval |
| 184 | * ` HYPERVISOR_mmu_update(const struct mmu_update reqs[], |
| 185 | * ` unsigned count, unsigned *done_out, |
| 186 | * ` unsigned foreigndom) |
| 187 | * ` |
| 188 | * @reqs is an array of mmu_update_t structures ((ptr, val) pairs). |
| 189 | * @count is the length of the above array. |
| 190 | * @pdone is an output parameter indicating number of completed operations |
| 191 | * @foreigndom[15:0]: FD, the expected owner of data pages referenced in this |
| 192 | * hypercall invocation. Can be DOMID_SELF. |
| 193 | * @foreigndom[31:16]: PFD, the expected owner of pagetable pages referenced |
| 194 | * in this hypercall invocation. The value of this field |
| 195 | * (x) encodes the PFD as follows: |
| 196 | * x == 0 => PFD == DOMID_SELF |
| 197 | * x != 0 => PFD == x - 1 |
| 198 | * |
| 199 | * Sub-commands: ptr[1:0] specifies the appropriate MMU_* command. |
| 200 | * ------------- |
| 201 | * ptr[1:0] == MMU_NORMAL_PT_UPDATE: |
| 202 | * Updates an entry in a page table belonging to PFD. If updating an L1 table, |
| 203 | * and the new table entry is valid/present, the mapped frame must belong to |
| 204 | * FD. If attempting to map an I/O page then the caller assumes the privilege |
| 205 | * of the FD. |
| 206 | * FD == DOMID_IO: Permit /only/ I/O mappings, at the priv level of the caller. |
| 207 | * FD == DOMID_XEN: Map restricted areas of Xen's heap space. |
| 208 | * ptr[:2] -- Machine address of the page-table entry to modify. |
| 209 | * val -- Value to write. |
| 210 | * |
| 211 | * There also certain implicit requirements when using this hypercall. The |
| 212 | * pages that make up a pagetable must be mapped read-only in the guest. |
| 213 | * This prevents uncontrolled guest updates to the pagetable. Xen strictly |
| 214 | * enforces this, and will disallow any pagetable update which will end up |
| 215 | * mapping pagetable page RW, and will disallow using any writable page as a |
| 216 | * pagetable. In practice it means that when constructing a page table for a |
| 217 | * process, thread, etc, we MUST be very dilligient in following these rules: |
| 218 | * 1). Start with top-level page (PGD or in Xen language: L4). Fill out |
| 219 | * the entries. |
| 220 | * 2). Keep on going, filling out the upper (PUD or L3), and middle (PMD |
| 221 | * or L2). |
| 222 | * 3). Start filling out the PTE table (L1) with the PTE entries. Once |
| 223 | * done, make sure to set each of those entries to RO (so writeable bit |
| 224 | * is unset). Once that has been completed, set the PMD (L2) for this |
| 225 | * PTE table as RO. |
| 226 | * 4). When completed with all of the PMD (L2) entries, and all of them have |
| 227 | * been set to RO, make sure to set RO the PUD (L3). Do the same |
| 228 | * operation on PGD (L4) pagetable entries that have a PUD (L3) entry. |
| 229 | * 5). Now before you can use those pages (so setting the cr3), you MUST also |
| 230 | * pin them so that the hypervisor can verify the entries. This is done |
| 231 | * via the HYPERVISOR_mmuext_op(MMUEXT_PIN_L4_TABLE, guest physical frame |
| 232 | * number of the PGD (L4)). And this point the HYPERVISOR_mmuext_op( |
| 233 | * MMUEXT_NEW_BASEPTR, guest physical frame number of the PGD (L4)) can be |
| 234 | * issued. |
| 235 | * For 32-bit guests, the L4 is not used (as there is less pagetables), so |
| 236 | * instead use L3. |
| 237 | * At this point the pagetables can be modified using the MMU_NORMAL_PT_UPDATE |
| 238 | * hypercall. Also if so desired the OS can also try to write to the PTE |
| 239 | * and be trapped by the hypervisor (as the PTE entry is RO). |
| 240 | * |
| 241 | * To deallocate the pages, the operations are the reverse of the steps |
| 242 | * mentioned above. The argument is MMUEXT_UNPIN_TABLE for all levels and the |
| 243 | * pagetable MUST not be in use (meaning that the cr3 is not set to it). |
| 244 | * |
| 245 | * ptr[1:0] == MMU_MACHPHYS_UPDATE: |
| 246 | * Updates an entry in the machine->pseudo-physical mapping table. |
| 247 | * ptr[:2] -- Machine address within the frame whose mapping to modify. |
| 248 | * The frame must belong to the FD, if one is specified. |
| 249 | * val -- Value to write into the mapping entry. |
| 250 | * |
| 251 | * ptr[1:0] == MMU_PT_UPDATE_PRESERVE_AD: |
| 252 | * As MMU_NORMAL_PT_UPDATE above, but A/D bits currently in the PTE are ORed |
| 253 | * with those in @val. |
| 254 | * |
| 255 | * ptr[1:0] == MMU_PT_UPDATE_NO_TRANSLATE: |
| 256 | * As MMU_NORMAL_PT_UPDATE above, but @val is not translated though FD |
| 257 | * page tables. |
| 258 | * |
| 259 | * @val is usually the machine frame number along with some attributes. |
| 260 | * The attributes by default follow the architecture defined bits. Meaning that |
| 261 | * if this is a X86_64 machine and four page table layout is used, the layout |
| 262 | * of val is: |
| 263 | * - 63 if set means No execute (NX) |
| 264 | * - 46-13 the machine frame number |
| 265 | * - 12 available for guest |
| 266 | * - 11 available for guest |
| 267 | * - 10 available for guest |
| 268 | * - 9 available for guest |
| 269 | * - 8 global |
| 270 | * - 7 PAT (PSE is disabled, must use hypercall to make 4MB or 2MB pages) |
| 271 | * - 6 dirty |
| 272 | * - 5 accessed |
| 273 | * - 4 page cached disabled |
| 274 | * - 3 page write through |
| 275 | * - 2 userspace accessible |
| 276 | * - 1 writeable |
| 277 | * - 0 present |
| 278 | * |
| 279 | * The one bits that does not fit with the default layout is the PAGE_PSE |
| 280 | * also called PAGE_PAT). The MMUEXT_[UN]MARK_SUPER arguments to the |
| 281 | * HYPERVISOR_mmuext_op serve as mechanism to set a pagetable to be 4MB |
| 282 | * (or 2MB) instead of using the PAGE_PSE bit. |
| 283 | * |
| 284 | * The reason that the PAGE_PSE (bit 7) is not being utilized is due to Xen |
| 285 | * using it as the Page Attribute Table (PAT) bit - for details on it please |
| 286 | * refer to Intel SDM 10.12. The PAT allows to set the caching attributes of |
| 287 | * pages instead of using MTRRs. |
| 288 | * |
| 289 | * The PAT MSR is as follows (it is a 64-bit value, each entry is 8 bits): |
| 290 | * PAT4 PAT0 |
| 291 | * +-----+-----+----+----+----+-----+----+----+ |
| 292 | * | UC | UC- | WC | WB | UC | UC- | WC | WB | <= Linux |
| 293 | * +-----+-----+----+----+----+-----+----+----+ |
| 294 | * | UC | UC- | WT | WB | UC | UC- | WT | WB | <= BIOS (default when machine boots) |
| 295 | * +-----+-----+----+----+----+-----+----+----+ |
| 296 | * | rsv | rsv | WP | WC | UC | UC- | WT | WB | <= Xen |
| 297 | * +-----+-----+----+----+----+-----+----+----+ |
| 298 | * |
| 299 | * The lookup of this index table translates to looking up |
| 300 | * Bit 7, Bit 4, and Bit 3 of val entry: |
| 301 | * |
| 302 | * PAT/PSE (bit 7) ... PCD (bit 4) .. PWT (bit 3). |
| 303 | * |
| 304 | * If all bits are off, then we are using PAT0. If bit 3 turned on, |
| 305 | * then we are using PAT1, if bit 3 and bit 4, then PAT2.. |
| 306 | * |
| 307 | * As you can see, the Linux PAT1 translates to PAT4 under Xen. Which means |
| 308 | * that if a guest that follows Linux's PAT setup and would like to set Write |
| 309 | * Combined on pages it MUST use PAT4 entry. Meaning that Bit 7 (PAGE_PAT) is |
| 310 | * set. For example, under Linux it only uses PAT0, PAT1, and PAT2 for the |
| 311 | * caching as: |
| 312 | * |
| 313 | * WB = none (so PAT0) |
| 314 | * WC = PWT (bit 3 on) |
| 315 | * UC = PWT | PCD (bit 3 and 4 are on). |
| 316 | * |
| 317 | * To make it work with Xen, it needs to translate the WC bit as so: |
| 318 | * |
| 319 | * PWT (so bit 3 on) --> PAT (so bit 7 is on) and clear bit 3 |
| 320 | * |
| 321 | * And to translate back it would: |
| 322 | * |
| 323 | * PAT (bit 7 on) --> PWT (bit 3 on) and clear bit 7. |
| 324 | */ |
| 325 | #define MMU_NORMAL_PT_UPDATE 0 /* checked '*ptr = val'. ptr is MA. */ |
| 326 | #define MMU_MACHPHYS_UPDATE 1 /* ptr = MA of frame to modify entry for */ |
| 327 | #define MMU_PT_UPDATE_PRESERVE_AD 2 /* atomically: *ptr = val | (*ptr&(A|D)) */ |
| 328 | #define MMU_PT_UPDATE_NO_TRANSLATE 3 /* checked '*ptr = val'. ptr is MA. */ |
| 329 | /* val never translated. */ |
| 330 | |
| 331 | /* |
| 332 | * MMU EXTENDED OPERATIONS |
| 333 | * |
| 334 | * ` enum neg_errnoval |
| 335 | * ` HYPERVISOR_mmuext_op(mmuext_op_t uops[], |
| 336 | * ` unsigned int count, |
| 337 | * ` unsigned int *pdone, |
| 338 | * ` unsigned int foreigndom) |
| 339 | */ |
| 340 | /* HYPERVISOR_mmuext_op() accepts a list of mmuext_op structures. |
| 341 | * A foreigndom (FD) can be specified (or DOMID_SELF for none). |
| 342 | * Where the FD has some effect, it is described below. |
| 343 | * |
| 344 | * cmd: MMUEXT_(UN)PIN_*_TABLE |
| 345 | * mfn: Machine frame number to be (un)pinned as a p.t. page. |
| 346 | * The frame must belong to the FD, if one is specified. |
| 347 | * |
| 348 | * cmd: MMUEXT_NEW_BASEPTR |
| 349 | * mfn: Machine frame number of new page-table base to install in MMU. |
| 350 | * |
| 351 | * cmd: MMUEXT_NEW_USER_BASEPTR [x86/64 only] |
| 352 | * mfn: Machine frame number of new page-table base to install in MMU |
| 353 | * when in user space. |
| 354 | * |
| 355 | * cmd: MMUEXT_TLB_FLUSH_LOCAL |
| 356 | * No additional arguments. Flushes local TLB. |
| 357 | * |
| 358 | * cmd: MMUEXT_INVLPG_LOCAL |
| 359 | * linear_addr: Linear address to be flushed from the local TLB. |
| 360 | * |
| 361 | * cmd: MMUEXT_TLB_FLUSH_MULTI |
| 362 | * vcpumask: Pointer to bitmap of VCPUs to be flushed. |
| 363 | * |
| 364 | * cmd: MMUEXT_INVLPG_MULTI |
| 365 | * linear_addr: Linear address to be flushed. |
| 366 | * vcpumask: Pointer to bitmap of VCPUs to be flushed. |
| 367 | * |
| 368 | * cmd: MMUEXT_TLB_FLUSH_ALL |
| 369 | * No additional arguments. Flushes all VCPUs' TLBs. |
| 370 | * |
| 371 | * cmd: MMUEXT_INVLPG_ALL |
| 372 | * linear_addr: Linear address to be flushed from all VCPUs' TLBs. |
| 373 | * |
| 374 | * cmd: MMUEXT_FLUSH_CACHE |
| 375 | * No additional arguments. Writes back and flushes cache contents. |
| 376 | * |
| 377 | * cmd: MMUEXT_FLUSH_CACHE_GLOBAL |
| 378 | * No additional arguments. Writes back and flushes cache contents |
| 379 | * on all CPUs in the system. |
| 380 | * |
| 381 | * cmd: MMUEXT_SET_LDT |
| 382 | * linear_addr: Linear address of LDT base (NB. must be page-aligned). |
| 383 | * nr_ents: Number of entries in LDT. |
| 384 | * |
| 385 | * cmd: MMUEXT_CLEAR_PAGE |
| 386 | * mfn: Machine frame number to be cleared. |
| 387 | * |
| 388 | * cmd: MMUEXT_COPY_PAGE |
| 389 | * mfn: Machine frame number of the destination page. |
| 390 | * src_mfn: Machine frame number of the source page. |
| 391 | * |
| 392 | * cmd: MMUEXT_[UN]MARK_SUPER |
| 393 | * mfn: Machine frame number of head of superpage to be [un]marked. |
| 394 | */ |
| 395 | /* ` enum mmuext_cmd { */ |
| 396 | #define MMUEXT_PIN_L1_TABLE 0 |
| 397 | #define MMUEXT_PIN_L2_TABLE 1 |
| 398 | #define MMUEXT_PIN_L3_TABLE 2 |
| 399 | #define MMUEXT_PIN_L4_TABLE 3 |
| 400 | #define MMUEXT_UNPIN_TABLE 4 |
| 401 | #define MMUEXT_NEW_BASEPTR 5 |
| 402 | #define MMUEXT_TLB_FLUSH_LOCAL 6 |
| 403 | #define MMUEXT_INVLPG_LOCAL 7 |
| 404 | #define MMUEXT_TLB_FLUSH_MULTI 8 |
| 405 | #define MMUEXT_INVLPG_MULTI 9 |
| 406 | #define MMUEXT_TLB_FLUSH_ALL 10 |
| 407 | #define MMUEXT_INVLPG_ALL 11 |
| 408 | #define MMUEXT_FLUSH_CACHE 12 |
| 409 | #define MMUEXT_SET_LDT 13 |
| 410 | #define MMUEXT_NEW_USER_BASEPTR 15 |
| 411 | #define MMUEXT_CLEAR_PAGE 16 |
| 412 | #define MMUEXT_COPY_PAGE 17 |
| 413 | #define MMUEXT_FLUSH_CACHE_GLOBAL 18 |
| 414 | #define MMUEXT_MARK_SUPER 19 |
| 415 | #define MMUEXT_UNMARK_SUPER 20 |
| 416 | /* ` } */ |
| 417 | |
| 418 | #ifndef __ASSEMBLY__ |
| 419 | struct mmuext_op { |
| 420 | unsigned int cmd; /* => enum mmuext_cmd */ |
| 421 | union { |
| 422 | /* [UN]PIN_TABLE, NEW_BASEPTR, NEW_USER_BASEPTR |
| 423 | * CLEAR_PAGE, COPY_PAGE, [UN]MARK_SUPER */ |
| 424 | xen_pfn_t mfn; |
| 425 | /* INVLPG_LOCAL, INVLPG_ALL, SET_LDT */ |
| 426 | unsigned long linear_addr; |
| 427 | } arg1; |
| 428 | union { |
| 429 | /* SET_LDT */ |
| 430 | unsigned int nr_ents; |
| 431 | /* TLB_FLUSH_MULTI, INVLPG_MULTI */ |
| 432 | #if __XEN_INTERFACE_VERSION__ >= 0x00030205 |
| 433 | XEN_GUEST_HANDLE(const_void) vcpumask; |
| 434 | #else |
| 435 | const void *vcpumask; |
| 436 | #endif |
| 437 | /* COPY_PAGE */ |
| 438 | xen_pfn_t src_mfn; |
| 439 | } arg2; |
| 440 | }; |
| 441 | typedef struct mmuext_op mmuext_op_t; |
| 442 | DEFINE_XEN_GUEST_HANDLE(mmuext_op_t); |
| 443 | #endif |
| 444 | |
| 445 | /* |
| 446 | * ` enum neg_errnoval |
| 447 | * ` HYPERVISOR_update_va_mapping(unsigned long va, u64 val, |
| 448 | * ` enum uvm_flags flags) |
| 449 | * ` |
| 450 | * ` enum neg_errnoval |
| 451 | * ` HYPERVISOR_update_va_mapping_otherdomain(unsigned long va, u64 val, |
| 452 | * ` enum uvm_flags flags, |
| 453 | * ` domid_t domid) |
| 454 | * ` |
| 455 | * ` @va: The virtual address whose mapping we want to change |
| 456 | * ` @val: The new page table entry, must contain a machine address |
| 457 | * ` @flags: Control TLB flushes |
| 458 | */ |
| 459 | /* These are passed as 'flags' to update_va_mapping. They can be ORed. */ |
| 460 | /* When specifying UVMF_MULTI, also OR in a pointer to a CPU bitmap. */ |
| 461 | /* UVMF_LOCAL is merely UVMF_MULTI with a NULL bitmap pointer. */ |
| 462 | /* ` enum uvm_flags { */ |
| 463 | #define UVMF_NONE (xen_mk_ulong(0)<<0) /* No flushing at all. */ |
| 464 | #define UVMF_TLB_FLUSH (xen_mk_ulong(1)<<0) /* Flush entire TLB(s). */ |
| 465 | #define UVMF_INVLPG (xen_mk_ulong(2)<<0) /* Flush only one entry. */ |
| 466 | #define UVMF_FLUSHTYPE_MASK (xen_mk_ulong(3)<<0) |
| 467 | #define UVMF_MULTI (xen_mk_ulong(0)<<2) /* Flush subset of TLBs. */ |
| 468 | #define UVMF_LOCAL (xen_mk_ulong(0)<<2) /* Flush local TLB. */ |
| 469 | #define UVMF_ALL (xen_mk_ulong(1)<<2) /* Flush all TLBs. */ |
| 470 | /* ` } */ |
| 471 | |
| 472 | /* |
| 473 | * ` int |
| 474 | * ` HYPERVISOR_console_io(unsigned int cmd, |
| 475 | * ` unsigned int count, |
| 476 | * ` char buffer[]); |
| 477 | * |
| 478 | * @cmd: Command (see below) |
| 479 | * @count: Size of the buffer to read/write |
| 480 | * @buffer: Pointer in the guest memory |
| 481 | * |
| 482 | * List of commands: |
| 483 | * |
| 484 | * * CONSOLEIO_write: Write the buffer to Xen console. |
| 485 | * For the hardware domain, all the characters in the buffer will |
| 486 | * be written. Characters will be printed directly to the console. |
| 487 | * For all the other domains, only the printable characters will be |
| 488 | * written. Characters may be buffered until a newline (i.e '\n') is |
| 489 | * found. |
| 490 | * @return 0 on success, otherwise return an error code. |
| 491 | * * CONSOLEIO_read: Attempts to read up to @count characters from Xen |
| 492 | * console. The maximum buffer size (i.e. @count) supported is 2GB. |
| 493 | * @return the number of characters read on success, otherwise return |
| 494 | * an error code. |
| 495 | */ |
| 496 | #define CONSOLEIO_write 0 |
| 497 | #define CONSOLEIO_read 1 |
| 498 | |
| 499 | /* |
| 500 | * Commands to HYPERVISOR_vm_assist(). |
| 501 | */ |
| 502 | #define VMASST_CMD_enable 0 |
| 503 | #define VMASST_CMD_disable 1 |
| 504 | |
| 505 | /* x86/32 guests: simulate full 4GB segment limits. */ |
| 506 | #define VMASST_TYPE_4gb_segments 0 |
| 507 | |
| 508 | /* x86/32 guests: trap (vector 15) whenever above vmassist is used. */ |
| 509 | #define VMASST_TYPE_4gb_segments_notify 1 |
| 510 | |
| 511 | /* |
| 512 | * x86 guests: support writes to bottom-level PTEs. |
| 513 | * NB1. Page-directory entries cannot be written. |
| 514 | * NB2. Guest must continue to remove all writable mappings of PTEs. |
| 515 | */ |
| 516 | #define VMASST_TYPE_writable_pagetables 2 |
| 517 | |
| 518 | /* x86/PAE guests: support PDPTs above 4GB. */ |
| 519 | #define VMASST_TYPE_pae_extended_cr3 3 |
| 520 | |
| 521 | /* |
| 522 | * x86 guests: Sane behaviour for virtual iopl |
| 523 | * - virtual iopl updated from do_iret() hypercalls. |
| 524 | * - virtual iopl reported in bounce frames. |
| 525 | * - guest kernels assumed to be level 0 for the purpose of iopl checks. |
| 526 | */ |
| 527 | #define VMASST_TYPE_architectural_iopl 4 |
| 528 | |
| 529 | /* |
| 530 | * All guests: activate update indicator in vcpu_runstate_info |
| 531 | * Enable setting the XEN_RUNSTATE_UPDATE flag in guest memory mapped |
| 532 | * vcpu_runstate_info during updates of the runstate information. |
| 533 | */ |
| 534 | #define VMASST_TYPE_runstate_update_flag 5 |
| 535 | |
| 536 | /* |
| 537 | * x86/64 guests: strictly hide M2P from user mode. |
| 538 | * This allows the guest to control respective hypervisor behavior: |
| 539 | * - when not set, L4 tables get created with the respective slot blank, |
| 540 | * and whenever the L4 table gets used as a kernel one the missing |
| 541 | * mapping gets inserted, |
| 542 | * - when set, L4 tables get created with the respective slot initialized |
| 543 | * as before, and whenever the L4 table gets used as a user one the |
| 544 | * mapping gets zapped. |
| 545 | */ |
| 546 | #define VMASST_TYPE_m2p_strict 32 |
| 547 | |
| 548 | #if __XEN_INTERFACE_VERSION__ < 0x00040600 |
| 549 | #define MAX_VMASST_TYPE 3 |
| 550 | #endif |
| 551 | |
| 552 | /* Domain ids >= DOMID_FIRST_RESERVED cannot be used for ordinary domains. */ |
| 553 | #define DOMID_FIRST_RESERVED xen_mk_uint(0x7FF0) |
| 554 | |
| 555 | /* DOMID_SELF is used in certain contexts to refer to oneself. */ |
| 556 | #define DOMID_SELF xen_mk_uint(0x7FF0) |
| 557 | |
| 558 | /* |
| 559 | * DOMID_IO is used to restrict page-table updates to mapping I/O memory. |
| 560 | * Although no Foreign Domain need be specified to map I/O pages, DOMID_IO |
| 561 | * is useful to ensure that no mappings to the OS's own heap are accidentally |
| 562 | * installed. (e.g., in Linux this could cause havoc as reference counts |
| 563 | * aren't adjusted on the I/O-mapping code path). |
| 564 | * This only makes sense as HYPERVISOR_mmu_update()'s and |
| 565 | * HYPERVISOR_update_va_mapping_otherdomain()'s "foreigndom" argument. For |
| 566 | * HYPERVISOR_mmu_update() context it can be specified by any calling domain, |
| 567 | * otherwise it's only permitted if the caller is privileged. |
| 568 | */ |
| 569 | #define DOMID_IO xen_mk_uint(0x7FF1) |
| 570 | |
| 571 | /* |
| 572 | * DOMID_XEN is used to allow privileged domains to map restricted parts of |
| 573 | * Xen's heap space (e.g., the machine_to_phys table). |
| 574 | * This only makes sense as |
| 575 | * - HYPERVISOR_mmu_update()'s, HYPERVISOR_mmuext_op()'s, or |
| 576 | * HYPERVISOR_update_va_mapping_otherdomain()'s "foreigndom" argument, |
| 577 | * - with XENMAPSPACE_gmfn_foreign, |
| 578 | * and is only permitted if the caller is privileged. |
| 579 | */ |
| 580 | #define DOMID_XEN xen_mk_uint(0x7FF2) |
| 581 | |
| 582 | /* |
| 583 | * DOMID_COW is used as the owner of sharable pages */ |
| 584 | #define DOMID_COW xen_mk_uint(0x7FF3) |
| 585 | |
| 586 | /* DOMID_INVALID is used to identify pages with unknown owner. */ |
| 587 | #define DOMID_INVALID xen_mk_uint(0x7FF4) |
| 588 | |
| 589 | /* Idle domain. */ |
| 590 | #define DOMID_IDLE xen_mk_uint(0x7FFF) |
| 591 | |
| 592 | /* Mask for valid domain id values */ |
| 593 | #define DOMID_MASK xen_mk_uint(0x7FFF) |
| 594 | |
| 595 | #ifndef __ASSEMBLY__ |
| 596 | |
| 597 | typedef uint16_t domid_t; |
| 598 | |
| 599 | /* |
| 600 | * Send an array of these to HYPERVISOR_mmu_update(). |
| 601 | * NB. The fields are natural pointer/address size for this architecture. |
| 602 | */ |
| 603 | struct mmu_update { |
| 604 | uint64_t ptr; /* Machine address of PTE. */ |
| 605 | uint64_t val; /* New contents of PTE. */ |
| 606 | }; |
| 607 | typedef struct mmu_update mmu_update_t; |
| 608 | DEFINE_XEN_GUEST_HANDLE(mmu_update_t); |
| 609 | |
| 610 | /* |
| 611 | * ` enum neg_errnoval |
| 612 | * ` HYPERVISOR_multicall(multicall_entry_t call_list[], |
| 613 | * ` uint32_t nr_calls); |
| 614 | * |
| 615 | * NB. The fields are logically the natural register size for this |
| 616 | * architecture. In cases where xen_ulong_t is larger than this then |
| 617 | * any unused bits in the upper portion must be zero. |
| 618 | */ |
| 619 | struct multicall_entry { |
| 620 | xen_ulong_t op, result; |
| 621 | xen_ulong_t args[6]; |
| 622 | }; |
| 623 | typedef struct multicall_entry multicall_entry_t; |
| 624 | DEFINE_XEN_GUEST_HANDLE(multicall_entry_t); |
| 625 | |
| 626 | #if __XEN_INTERFACE_VERSION__ < 0x00040400 |
| 627 | /* |
| 628 | * Event channel endpoints per domain (when using the 2-level ABI): |
| 629 | * 1024 if a long is 32 bits; 4096 if a long is 64 bits. |
| 630 | */ |
| 631 | #define NR_EVENT_CHANNELS EVTCHN_2L_NR_CHANNELS |
| 632 | #endif |
| 633 | |
| 634 | struct vcpu_time_info { |
| 635 | /* |
| 636 | * Updates to the following values are preceded and followed by an |
| 637 | * increment of 'version'. The guest can therefore detect updates by |
| 638 | * looking for changes to 'version'. If the least-significant bit of |
| 639 | * the version number is set then an update is in progress and the guest |
| 640 | * must wait to read a consistent set of values. |
| 641 | * The correct way to interact with the version number is similar to |
| 642 | * Linux's seqlock: see the implementations of read_seqbegin/read_seqretry. |
| 643 | */ |
| 644 | uint32_t version; |
| 645 | uint32_t pad0; |
| 646 | uint64_t tsc_timestamp; /* TSC at last update of time vals. */ |
| 647 | uint64_t system_time; /* Time, in nanosecs, since boot. */ |
| 648 | /* |
| 649 | * Current system time: |
| 650 | * system_time + |
| 651 | * ((((tsc - tsc_timestamp) << tsc_shift) * tsc_to_system_mul) >> 32) |
| 652 | * CPU frequency (Hz): |
| 653 | * ((10^9 << 32) / tsc_to_system_mul) >> tsc_shift |
| 654 | */ |
| 655 | uint32_t tsc_to_system_mul; |
| 656 | int8_t tsc_shift; |
| 657 | #if __XEN_INTERFACE_VERSION__ > 0x040600 |
| 658 | uint8_t flags; |
| 659 | uint8_t pad1[2]; |
| 660 | #else |
| 661 | int8_t pad1[3]; |
| 662 | #endif |
| 663 | }; /* 32 bytes */ |
| 664 | typedef struct vcpu_time_info vcpu_time_info_t; |
| 665 | |
| 666 | #define XEN_PVCLOCK_TSC_STABLE_BIT (1 << 0) |
| 667 | #define XEN_PVCLOCK_GUEST_STOPPED (1 << 1) |
| 668 | |
| 669 | struct vcpu_info { |
| 670 | /* |
| 671 | * 'evtchn_upcall_pending' is written non-zero by Xen to indicate |
| 672 | * a pending notification for a particular VCPU. It is then cleared |
| 673 | * by the guest OS /before/ checking for pending work, thus avoiding |
| 674 | * a set-and-check race. Note that the mask is only accessed by Xen |
| 675 | * on the CPU that is currently hosting the VCPU. This means that the |
| 676 | * pending and mask flags can be updated by the guest without special |
| 677 | * synchronisation (i.e., no need for the x86 LOCK prefix). |
| 678 | * This may seem suboptimal because if the pending flag is set by |
| 679 | * a different CPU then an IPI may be scheduled even when the mask |
| 680 | * is set. However, note: |
| 681 | * 1. The task of 'interrupt holdoff' is covered by the per-event- |
| 682 | * channel mask bits. A 'noisy' event that is continually being |
| 683 | * triggered can be masked at source at this very precise |
| 684 | * granularity. |
| 685 | * 2. The main purpose of the per-VCPU mask is therefore to restrict |
| 686 | * reentrant execution: whether for concurrency control, or to |
| 687 | * prevent unbounded stack usage. Whatever the purpose, we expect |
| 688 | * that the mask will be asserted only for short periods at a time, |
| 689 | * and so the likelihood of a 'spurious' IPI is suitably small. |
| 690 | * The mask is read before making an event upcall to the guest: a |
| 691 | * non-zero mask therefore guarantees that the VCPU will not receive |
| 692 | * an upcall activation. The mask is cleared when the VCPU requests |
| 693 | * to block: this avoids wakeup-waiting races. |
| 694 | */ |
| 695 | uint8_t evtchn_upcall_pending; |
| 696 | #ifdef XEN_HAVE_PV_UPCALL_MASK |
| 697 | uint8_t evtchn_upcall_mask; |
| 698 | #else /* XEN_HAVE_PV_UPCALL_MASK */ |
| 699 | uint8_t pad0; |
| 700 | #endif /* XEN_HAVE_PV_UPCALL_MASK */ |
| 701 | xen_ulong_t evtchn_pending_sel; |
| 702 | struct arch_vcpu_info arch; |
| 703 | vcpu_time_info_t time; |
| 704 | }; /* 64 bytes (x86) */ |
| 705 | #ifndef __XEN__ |
| 706 | typedef struct vcpu_info vcpu_info_t; |
| 707 | #endif |
| 708 | |
| 709 | /* |
| 710 | * `incontents 200 startofday_shared Start-of-day shared data structure |
| 711 | * Xen/kernel shared data -- pointer provided in start_info. |
| 712 | * |
| 713 | * This structure is defined to be both smaller than a page, and the |
| 714 | * only data on the shared page, but may vary in actual size even within |
| 715 | * compatible Xen versions; guests should not rely on the size |
| 716 | * of this structure remaining constant. |
| 717 | */ |
| 718 | struct shared_info { |
| 719 | struct vcpu_info vcpu_info[XEN_LEGACY_MAX_VCPUS]; |
| 720 | |
| 721 | /* |
| 722 | * A domain can create "event channels" on which it can send and receive |
| 723 | * asynchronous event notifications. There are three classes of event that |
| 724 | * are delivered by this mechanism: |
| 725 | * 1. Bi-directional inter- and intra-domain connections. Domains must |
| 726 | * arrange out-of-band to set up a connection (usually by allocating |
| 727 | * an unbound 'listener' port and avertising that via a storage service |
| 728 | * such as xenstore). |
| 729 | * 2. Physical interrupts. A domain with suitable hardware-access |
| 730 | * privileges can bind an event-channel port to a physical interrupt |
| 731 | * source. |
| 732 | * 3. Virtual interrupts ('events'). A domain can bind an event-channel |
| 733 | * port to a virtual interrupt source, such as the virtual-timer |
| 734 | * device or the emergency console. |
| 735 | * |
| 736 | * Event channels are addressed by a "port index". Each channel is |
| 737 | * associated with two bits of information: |
| 738 | * 1. PENDING -- notifies the domain that there is a pending notification |
| 739 | * to be processed. This bit is cleared by the guest. |
| 740 | * 2. MASK -- if this bit is clear then a 0->1 transition of PENDING |
| 741 | * will cause an asynchronous upcall to be scheduled. This bit is only |
| 742 | * updated by the guest. It is read-only within Xen. If a channel |
| 743 | * becomes pending while the channel is masked then the 'edge' is lost |
| 744 | * (i.e., when the channel is unmasked, the guest must manually handle |
| 745 | * pending notifications as no upcall will be scheduled by Xen). |
| 746 | * |
| 747 | * To expedite scanning of pending notifications, any 0->1 pending |
| 748 | * transition on an unmasked channel causes a corresponding bit in a |
| 749 | * per-vcpu selector word to be set. Each bit in the selector covers a |
| 750 | * 'C long' in the PENDING bitfield array. |
| 751 | */ |
| 752 | xen_ulong_t evtchn_pending[sizeof(xen_ulong_t) * 8]; |
| 753 | xen_ulong_t evtchn_mask[sizeof(xen_ulong_t) * 8]; |
| 754 | |
| 755 | /* |
| 756 | * Wallclock time: updated by control software or RTC emulation. |
| 757 | * Guests should base their gettimeofday() syscall on this |
| 758 | * wallclock-base value. |
| 759 | * The values of wc_sec and wc_nsec are offsets from the Unix epoch |
| 760 | * adjusted by the domain's 'time offset' (in seconds) as set either |
| 761 | * by XEN_DOMCTL_settimeoffset, or adjusted via a guest write to the |
| 762 | * emulated RTC. |
| 763 | */ |
| 764 | uint32_t wc_version; /* Version counter: see vcpu_time_info_t. */ |
| 765 | uint32_t wc_sec; |
| 766 | uint32_t wc_nsec; |
| 767 | #if !defined(__i386__) |
| 768 | uint32_t wc_sec_hi; |
| 769 | # define xen_wc_sec_hi wc_sec_hi |
| 770 | #elif !defined(__XEN__) && !defined(__XEN_TOOLS__) |
| 771 | # define xen_wc_sec_hi arch.wc_sec_hi |
| 772 | #endif |
| 773 | |
| 774 | struct arch_shared_info arch; |
| 775 | |
| 776 | }; |
| 777 | #ifndef __XEN__ |
| 778 | typedef struct shared_info shared_info_t; |
| 779 | #endif |
| 780 | |
| 781 | /* |
| 782 | * `incontents 200 startofday Start-of-day memory layout |
| 783 | * |
| 784 | * 1. The domain is started within contiguous virtual-memory region. |
| 785 | * 2. The contiguous region ends on an aligned 4MB boundary. |
| 786 | * 3. This the order of bootstrap elements in the initial virtual region: |
| 787 | * a. relocated kernel image |
| 788 | * b. initial ram disk [mod_start, mod_len] |
| 789 | * (may be omitted) |
| 790 | * c. list of allocated page frames [mfn_list, nr_pages] |
| 791 | * (unless relocated due to XEN_ELFNOTE_INIT_P2M) |
| 792 | * d. start_info_t structure [register rSI (x86)] |
| 793 | * in case of dom0 this page contains the console info, too |
| 794 | * e. unless dom0: xenstore ring page |
| 795 | * f. unless dom0: console ring page |
| 796 | * g. bootstrap page tables [pt_base and CR3 (x86)] |
| 797 | * h. bootstrap stack [register ESP (x86)] |
| 798 | * 4. Bootstrap elements are packed together, but each is 4kB-aligned. |
| 799 | * 5. The list of page frames forms a contiguous 'pseudo-physical' memory |
| 800 | * layout for the domain. In particular, the bootstrap virtual-memory |
| 801 | * region is a 1:1 mapping to the first section of the pseudo-physical map. |
| 802 | * 6. All bootstrap elements are mapped read-writable for the guest OS. The |
| 803 | * only exception is the bootstrap page table, which is mapped read-only. |
| 804 | * 7. There is guaranteed to be at least 512kB padding after the final |
| 805 | * bootstrap element. If necessary, the bootstrap virtual region is |
| 806 | * extended by an extra 4MB to ensure this. |
| 807 | * |
| 808 | * Note: Prior to 25833:bb85bbccb1c9. ("x86/32-on-64 adjust Dom0 initial page |
| 809 | * table layout") a bug caused the pt_base (3.g above) and cr3 to not point |
| 810 | * to the start of the guest page tables (it was offset by two pages). |
| 811 | * This only manifested itself on 32-on-64 dom0 kernels and not 32-on-64 domU |
| 812 | * or 64-bit kernels of any colour. The page tables for a 32-on-64 dom0 got |
| 813 | * allocated in the order: 'first L1','first L2', 'first L3', so the offset |
| 814 | * to the page table base is by two pages back. The initial domain if it is |
| 815 | * 32-bit and runs under a 64-bit hypervisor should _NOT_ use two of the |
| 816 | * pages preceding pt_base and mark them as reserved/unused. |
| 817 | */ |
| 818 | #ifdef XEN_HAVE_PV_GUEST_ENTRY |
| 819 | struct start_info { |
| 820 | /* THE FOLLOWING ARE FILLED IN BOTH ON INITIAL BOOT AND ON RESUME. */ |
| 821 | char magic[32]; /* "xen-<version>-<platform>". */ |
| 822 | unsigned long nr_pages; /* Total pages allocated to this domain. */ |
| 823 | unsigned long shared_info; /* MACHINE address of shared info struct. */ |
| 824 | uint32_t flags; /* SIF_xxx flags. */ |
| 825 | xen_pfn_t store_mfn; /* MACHINE page number of shared page. */ |
| 826 | uint32_t store_evtchn; /* Event channel for store communication. */ |
| 827 | union { |
| 828 | struct { |
| 829 | xen_pfn_t mfn; /* MACHINE page number of console page. */ |
| 830 | uint32_t evtchn; /* Event channel for console page. */ |
| 831 | } domU; |
| 832 | struct { |
| 833 | uint32_t info_off; /* Offset of console_info struct. */ |
| 834 | uint32_t info_size; /* Size of console_info struct from start.*/ |
| 835 | } dom0; |
| 836 | } console; |
| 837 | /* THE FOLLOWING ARE ONLY FILLED IN ON INITIAL BOOT (NOT RESUME). */ |
| 838 | unsigned long pt_base; /* VIRTUAL address of page directory. */ |
| 839 | unsigned long nr_pt_frames; /* Number of bootstrap p.t. frames. */ |
| 840 | unsigned long mfn_list; /* VIRTUAL address of page-frame list. */ |
| 841 | unsigned long mod_start; /* VIRTUAL address of pre-loaded module */ |
| 842 | /* (PFN of pre-loaded module if */ |
| 843 | /* SIF_MOD_START_PFN set in flags). */ |
| 844 | unsigned long mod_len; /* Size (bytes) of pre-loaded module. */ |
| 845 | #define MAX_GUEST_CMDLINE 1024 |
| 846 | int8_t cmd_line[MAX_GUEST_CMDLINE]; |
| 847 | /* The pfn range here covers both page table and p->m table frames. */ |
| 848 | unsigned long first_p2m_pfn;/* 1st pfn forming initial P->M table. */ |
| 849 | unsigned long nr_p2m_frames;/* # of pfns forming initial P->M table. */ |
| 850 | }; |
| 851 | typedef struct start_info start_info_t; |
| 852 | |
| 853 | /* New console union for dom0 introduced in 0x00030203. */ |
| 854 | #if __XEN_INTERFACE_VERSION__ < 0x00030203 |
| 855 | #define console_mfn console.domU.mfn |
| 856 | #define console_evtchn console.domU.evtchn |
| 857 | #endif |
| 858 | #endif /* XEN_HAVE_PV_GUEST_ENTRY */ |
| 859 | |
| 860 | /* These flags are passed in the 'flags' field of start_info_t. */ |
| 861 | #define SIF_PRIVILEGED (1<<0) /* Is the domain privileged? */ |
| 862 | #define SIF_INITDOMAIN (1<<1) /* Is this the initial control domain? */ |
| 863 | #define SIF_MULTIBOOT_MOD (1<<2) /* Is mod_start a multiboot module? */ |
| 864 | #define SIF_MOD_START_PFN (1<<3) /* Is mod_start a PFN? */ |
| 865 | #define SIF_VIRT_P2M_4TOOLS (1<<4) /* Do Xen tools understand a virt. mapped */ |
| 866 | /* P->M making the 3 level tree obsolete? */ |
| 867 | #define SIF_PM_MASK (0xFF<<8) /* reserve 1 byte for xen-pm options */ |
| 868 | |
| 869 | /* |
| 870 | * A multiboot module is a package containing modules very similar to a |
| 871 | * multiboot module array. The only differences are: |
| 872 | * - the array of module descriptors is by convention simply at the beginning |
| 873 | * of the multiboot module, |
| 874 | * - addresses in the module descriptors are based on the beginning of the |
| 875 | * multiboot module, |
| 876 | * - the number of modules is determined by a termination descriptor that has |
| 877 | * mod_start == 0. |
| 878 | * |
| 879 | * This permits to both build it statically and reference it in a configuration |
| 880 | * file, and let the PV guest easily rebase the addresses to virtual addresses |
| 881 | * and at the same time count the number of modules. |
| 882 | */ |
| 883 | struct xen_multiboot_mod_list |
| 884 | { |
| 885 | /* Address of first byte of the module */ |
| 886 | uint32_t mod_start; |
| 887 | /* Address of last byte of the module (inclusive) */ |
| 888 | uint32_t mod_end; |
| 889 | /* Address of zero-terminated command line */ |
| 890 | uint32_t cmdline; |
| 891 | /* Unused, must be zero */ |
| 892 | uint32_t pad; |
| 893 | }; |
| 894 | /* |
| 895 | * `incontents 200 startofday_dom0_console Dom0_console |
| 896 | * |
| 897 | * The console structure in start_info.console.dom0 |
| 898 | * |
| 899 | * This structure includes a variety of information required to |
| 900 | * have a working VGA/VESA console. |
| 901 | */ |
| 902 | typedef struct dom0_vga_console_info { |
| 903 | uint8_t video_type; /* DOM0_VGA_CONSOLE_??? */ |
| 904 | #define XEN_VGATYPE_TEXT_MODE_3 0x03 |
| 905 | #define XEN_VGATYPE_VESA_LFB 0x23 |
| 906 | #define XEN_VGATYPE_EFI_LFB 0x70 |
| 907 | |
| 908 | union { |
| 909 | struct { |
| 910 | /* Font height, in pixels. */ |
| 911 | uint16_t font_height; |
| 912 | /* Cursor location (column, row). */ |
| 913 | uint16_t cursor_x, cursor_y; |
| 914 | /* Number of rows and columns (dimensions in characters). */ |
| 915 | uint16_t rows, columns; |
| 916 | } text_mode_3; |
| 917 | |
| 918 | struct { |
| 919 | /* Width and height, in pixels. */ |
| 920 | uint16_t width, height; |
| 921 | /* Bytes per scan line. */ |
| 922 | uint16_t bytes_per_line; |
| 923 | /* Bits per pixel. */ |
| 924 | uint16_t bits_per_pixel; |
| 925 | /* LFB physical address, and size (in units of 64kB). */ |
| 926 | uint32_t lfb_base; |
| 927 | uint32_t lfb_size; |
| 928 | /* RGB mask offsets and sizes, as defined by VBE 1.2+ */ |
| 929 | uint8_t red_pos, red_size; |
| 930 | uint8_t green_pos, green_size; |
| 931 | uint8_t blue_pos, blue_size; |
| 932 | uint8_t rsvd_pos, rsvd_size; |
| 933 | #if __XEN_INTERFACE_VERSION__ >= 0x00030206 |
| 934 | /* VESA capabilities (offset 0xa, VESA command 0x4f00). */ |
| 935 | uint32_t gbl_caps; |
| 936 | /* Mode attributes (offset 0x0, VESA command 0x4f01). */ |
| 937 | uint16_t mode_attrs; |
| 938 | uint16_t pad; |
| 939 | #endif |
| 940 | #if __XEN_INTERFACE_VERSION__ >= 0x00040d00 |
| 941 | /* high 32 bits of lfb_base */ |
| 942 | uint32_t ext_lfb_base; |
| 943 | #endif |
| 944 | } vesa_lfb; |
| 945 | } u; |
| 946 | } dom0_vga_console_info_t; |
| 947 | #define xen_vga_console_info dom0_vga_console_info |
| 948 | #define xen_vga_console_info_t dom0_vga_console_info_t |
| 949 | |
| 950 | typedef uint8_t xen_domain_handle_t[16]; |
| 951 | |
| 952 | __DEFINE_XEN_GUEST_HANDLE(uint8, uint8_t); |
| 953 | __DEFINE_XEN_GUEST_HANDLE(uint16, uint16_t); |
| 954 | __DEFINE_XEN_GUEST_HANDLE(uint32, uint32_t); |
| 955 | __DEFINE_XEN_GUEST_HANDLE(uint64, uint64_t); |
| 956 | |
| 957 | typedef struct { |
| 958 | uint8_t a[16]; |
| 959 | } xen_uuid_t; |
| 960 | |
| 961 | /* |
| 962 | * XEN_DEFINE_UUID(0x00112233, 0x4455, 0x6677, 0x8899, |
| 963 | * 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff) |
| 964 | * will construct UUID 00112233-4455-6677-8899-aabbccddeeff presented as |
| 965 | * {0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88, |
| 966 | * 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff}; |
| 967 | * |
| 968 | * NB: This is compatible with Linux kernel and with libuuid, but it is not |
| 969 | * compatible with Microsoft, as they use mixed-endian encoding (some |
| 970 | * components are little-endian, some are big-endian). |
| 971 | */ |
| 972 | #define XEN_DEFINE_UUID_(a, b, c, d, e1, e2, e3, e4, e5, e6) \ |
| 973 | {{((a) >> 24) & 0xFF, ((a) >> 16) & 0xFF, \ |
| 974 | ((a) >> 8) & 0xFF, ((a) >> 0) & 0xFF, \ |
| 975 | ((b) >> 8) & 0xFF, ((b) >> 0) & 0xFF, \ |
| 976 | ((c) >> 8) & 0xFF, ((c) >> 0) & 0xFF, \ |
| 977 | ((d) >> 8) & 0xFF, ((d) >> 0) & 0xFF, \ |
| 978 | e1, e2, e3, e4, e5, e6}} |
| 979 | |
| 980 | #define XEN_DEFINE_UUID(a, b, c, d, e1, e2, e3, e4, e5, e6) \ |
| 981 | ((xen_uuid_t)XEN_DEFINE_UUID_(a, b, c, d, e1, e2, e3, e4, e5, e6)) |
| 982 | |
| 983 | #endif /* !__ASSEMBLY__ */ |
| 984 | |
| 985 | /* Default definitions for macros used by domctl/sysctl. */ |
| 986 | #if defined(__XEN__) || defined(__XEN_TOOLS__) |
| 987 | |
| 988 | #ifndef int64_aligned_t |
| 989 | #define int64_aligned_t int64_t |
| 990 | #endif |
| 991 | #ifndef uint64_aligned_t |
| 992 | #define uint64_aligned_t uint64_t |
| 993 | #endif |
| 994 | #ifndef XEN_GUEST_HANDLE_64 |
| 995 | #define XEN_GUEST_HANDLE_64(name) XEN_GUEST_HANDLE(name) |
| 996 | #endif |
| 997 | |
| 998 | #ifndef __ASSEMBLY__ |
| 999 | struct xenctl_bitmap { |
| 1000 | XEN_GUEST_HANDLE_64(uint8) bitmap; |
| 1001 | uint32_t nr_bits; |
| 1002 | }; |
| 1003 | typedef struct xenctl_bitmap xenctl_bitmap_t; |
| 1004 | #endif |
| 1005 | |
| 1006 | #endif /* defined(__XEN__) || defined(__XEN_TOOLS__) */ |
| 1007 | |
| 1008 | #endif /* __XEN_PUBLIC_XEN_H__ */ |
| 1009 | |
| 1010 | /* |
| 1011 | * Local variables: |
| 1012 | * mode: C |
| 1013 | * c-file-style: "BSD" |
| 1014 | * c-basic-offset: 4 |
| 1015 | * tab-width: 4 |
| 1016 | * indent-tabs-mode: nil |
| 1017 | * End: |
| 1018 | */ |