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h 55 lines 2.2 KB
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1 /*
2 * QEMU base architecture bit definitions
3 *
4 * SPDX-License-Identifier: GPL-2.0-or-later
5 */
6
7 #ifndef QEMU_BASE_ARCH_DEFS_H
8 #define QEMU_BASE_ARCH_DEFS_H
9
10 #include "qapi/qapi-types-machine.h"
11
12 enum {
13 QEMU_ARCH_ALPHA = (1UL << SYS_EMU_TARGET_ALPHA),
14 QEMU_ARCH_ARM = (1UL << SYS_EMU_TARGET_ARM) |
15 (1UL << SYS_EMU_TARGET_AARCH64),
16 QEMU_ARCH_I386 = (1UL << SYS_EMU_TARGET_I386) |
17 (1UL << SYS_EMU_TARGET_X86_64),
18 QEMU_ARCH_M68K = (1UL << SYS_EMU_TARGET_M68K),
19 QEMU_ARCH_MICROBLAZE = (1UL << SYS_EMU_TARGET_MICROBLAZE),
20 QEMU_ARCH_MIPS = (1UL << SYS_EMU_TARGET_MIPS) |
21 (1UL << SYS_EMU_TARGET_MIPSEL) |
22 (1UL << SYS_EMU_TARGET_MIPS64) |
23 (1UL << SYS_EMU_TARGET_MIPS64EL),
24 QEMU_ARCH_PPC = (1UL << SYS_EMU_TARGET_PPC) |
25 (1UL << SYS_EMU_TARGET_PPC64),
26 QEMU_ARCH_S390X = (1UL << SYS_EMU_TARGET_S390X),
27 QEMU_ARCH_SH4 = (1UL << SYS_EMU_TARGET_SH4) |
28 (1UL << SYS_EMU_TARGET_SH4EB),
29 QEMU_ARCH_SPARC = (1UL << SYS_EMU_TARGET_SPARC) |
30 (1UL << SYS_EMU_TARGET_SPARC64),
31 QEMU_ARCH_XTENSA = (1UL << SYS_EMU_TARGET_XTENSA) |
32 (1UL << SYS_EMU_TARGET_XTENSAEB),
33 QEMU_ARCH_OR1K = (1UL << SYS_EMU_TARGET_OR1K),
34 QEMU_ARCH_TRICORE = (1UL << SYS_EMU_TARGET_TRICORE),
35 QEMU_ARCH_HPPA = (1UL << SYS_EMU_TARGET_HPPA),
36 QEMU_ARCH_RISCV = (1UL << SYS_EMU_TARGET_RISCV32) |
37 (1UL << SYS_EMU_TARGET_RISCV64),
38 QEMU_ARCH_RX = (1UL << SYS_EMU_TARGET_RX),
39 QEMU_ARCH_AVR = (1UL << SYS_EMU_TARGET_AVR),
40 QEMU_ARCH_HEXAGON = (1UL << SYS_EMU_TARGET_HEXAGON),
41 QEMU_ARCH_LOONGARCH = (1UL << SYS_EMU_TARGET_LOONGARCH64),
42 QEMU_ARCH_ALL = UINT32_MAX,
43 };
44
45 QEMU_BUILD_BUG_ON(SYS_EMU_TARGET__MAX > 32);
46
47 /**
48 * qemu_arch_available:
49 * @arch_bitmask: bitmask of QEMU_ARCH_* constants
50 *
51 * Return whether the current target architecture is contained in @arch_bitmask
52 */
53 bool qemu_arch_available(uint32_t arch_bitmask);
54
55 #endif