drm_fourcc.h · samitouri/QOSamiQemu

Code Commits Issues Pulls Sessions CI/CD

master

h 1,787 lines 76.6 KB

Raw

1	/* SPDX-License-Identifier: MIT */
2	/*
3	* Copyright 2011 Intel Corporation
4	*/
5
6	#ifndef DRM_FOURCC_H
7	#define DRM_FOURCC_H
8
9
10	#if defined(__cplusplus)
11	extern "C" {
12	#endif
13
14	/**
15	* DOC: overview
16	*
17	* In the DRM subsystem, framebuffer pixel formats are described using the
18	* fourcc codes defined in `include/uapi/drm/drm_fourcc.h`. In addition to the
19	* fourcc code, a Format Modifier may optionally be provided, in order to
20	* further describe the buffer's format - for example tiling or compression.
21	*
22	* Format Modifiers
23	* ----------------
24	*
25	* Format modifiers are used in conjunction with a fourcc code, forming a
26	* unique fourcc:modifier pair. This format:modifier pair must fully define the
27	* format and data layout of the buffer, and should be the only way to describe
28	* that particular buffer.
29	*
30	* Having multiple fourcc:modifier pairs which describe the same layout should
31	* be avoided, as such aliases run the risk of different drivers exposing
32	* different names for the same data format, forcing userspace to understand
33	* that they are aliases.
34	*
35	* Format modifiers may change any property of the buffer, including the number
36	* of planes and/or the required allocation size. Format modifiers are
37	* vendor-namespaced, and as such the relationship between a fourcc code and a
38	* modifier is specific to the modifier being used. For example, some modifiers
39	* may preserve meaning - such as number of planes - from the fourcc code,
40	* whereas others may not.
41	*
42	* Modifiers must uniquely encode buffer layout. In other words, a buffer must
43	* match only a single modifier. A modifier must not be a subset of layouts of
44	* another modifier. For instance, it's incorrect to encode pitch alignment in
45	* a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
46	* aligned modifier. That said, modifiers can have implicit minimal
47	* requirements.
48	*
49	* For modifiers where the combination of fourcc code and modifier can alias,
50	* a canonical pair needs to be defined and used by all drivers. Preferred
51	* combinations are also encouraged where all combinations might lead to
52	* confusion and unnecessarily reduced interoperability. An example for the
53	* latter is AFBC, where the ABGR layouts are preferred over ARGB layouts.
54	*
55	* There are two kinds of modifier users:
56	*
57	* - Kernel and user-space drivers: for drivers it's important that modifiers
58	* don't alias, otherwise two drivers might support the same format but use
59	* different aliases, preventing them from sharing buffers in an efficient
60	* format.
61	* - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users
62	* see modifiers as opaque tokens they can check for equality and intersect.
63	* These users mustn't need to know to reason about the modifier value
64	* (i.e. they are not expected to extract information out of the modifier).
65	*
66	* Vendors should document their modifier usage in as much detail as
67	* possible, to ensure maximum compatibility across devices, drivers and
68	* applications.
69	*
70	* The authoritative list of format modifier codes is found in
71	* `include/uapi/drm/drm_fourcc.h`
72	*
73	* Open Source User Waiver
74	* -----------------------
75	*
76	* Because this is the authoritative source for pixel formats and modifiers
77	* referenced by GL, Vulkan extensions and other standards and hence used both
78	* by open source and closed source driver stacks, the usual requirement for an
79	* upstream in-kernel or open source userspace user does not apply.
80	*
81	* To ensure, as much as feasible, compatibility across stacks and avoid
82	* confusion with incompatible enumerations stakeholders for all relevant driver
83	* stacks should approve additions.
84	*/
85
86	#define fourcc_code(a, b, c, d) ((uint32_t)(a) \| ((uint32_t)(b) << 8) \| \
87	((uint32_t)(c) << 16) \| ((uint32_t)(d) << 24))
88
89	#define DRM_FORMAT_BIG_ENDIAN (1U<<31) /* format is big endian instead of little endian */
90
91	/* Reserve 0 for the invalid format specifier */
92	#define DRM_FORMAT_INVALID 0
93
94	/* color index */
95	#define DRM_FORMAT_C1 fourcc_code('C', '1', ' ', ' ') /* [7:0] C0:C1:C2:C3:C4:C5:C6:C7 1:1:1:1:1:1:1:1 eight pixels/byte */
96	#define DRM_FORMAT_C2 fourcc_code('C', '2', ' ', ' ') /* [7:0] C0:C1:C2:C3 2:2:2:2 four pixels/byte */
97	#define DRM_FORMAT_C4 fourcc_code('C', '4', ' ', ' ') /* [7:0] C0:C1 4:4 two pixels/byte */
98	#define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
99
100	/* 1 bpp Darkness (inverse relationship between channel value and brightness) */
101	#define DRM_FORMAT_D1 fourcc_code('D', '1', ' ', ' ') /* [7:0] D0:D1:D2:D3:D4:D5:D6:D7 1:1:1:1:1:1:1:1 eight pixels/byte */
102
103	/* 2 bpp Darkness (inverse relationship between channel value and brightness) */
104	#define DRM_FORMAT_D2 fourcc_code('D', '2', ' ', ' ') /* [7:0] D0:D1:D2:D3 2:2:2:2 four pixels/byte */
105
106	/* 4 bpp Darkness (inverse relationship between channel value and brightness) */
107	#define DRM_FORMAT_D4 fourcc_code('D', '4', ' ', ' ') /* [7:0] D0:D1 4:4 two pixels/byte */
108
109	/* 8 bpp Darkness (inverse relationship between channel value and brightness) */
110	#define DRM_FORMAT_D8 fourcc_code('D', '8', ' ', ' ') /* [7:0] D */
111
112	/* 1 bpp Red (direct relationship between channel value and brightness) */
113	#define DRM_FORMAT_R1 fourcc_code('R', '1', ' ', ' ') /* [7:0] R0:R1:R2:R3:R4:R5:R6:R7 1:1:1:1:1:1:1:1 eight pixels/byte */
114
115	/* 2 bpp Red (direct relationship between channel value and brightness) */
116	#define DRM_FORMAT_R2 fourcc_code('R', '2', ' ', ' ') /* [7:0] R0:R1:R2:R3 2:2:2:2 four pixels/byte */
117
118	/* 4 bpp Red (direct relationship between channel value and brightness) */
119	#define DRM_FORMAT_R4 fourcc_code('R', '4', ' ', ' ') /* [7:0] R0:R1 4:4 two pixels/byte */
120
121	/* 8 bpp Red (direct relationship between channel value and brightness) */
122	#define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
123
124	/* 10 bpp Red (direct relationship between channel value and brightness) */
125	#define DRM_FORMAT_R10 fourcc_code('R', '1', '0', ' ') /* [15:0] x:R 6:10 little endian */
126
127	/* 12 bpp Red (direct relationship between channel value and brightness) */
128	#define DRM_FORMAT_R12 fourcc_code('R', '1', '2', ' ') /* [15:0] x:R 4:12 little endian */
129
130	/* 16 bpp Red (direct relationship between channel value and brightness) */
131	#define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */
132
133	/* 16 bpp RG */
134	#define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */
135	#define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */
136
137	/* 32 bpp RG */
138	#define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */
139	#define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */
140
141	/* 8 bpp RGB */
142	#define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */
143	#define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */
144
145	/* 16 bpp RGB */
146	#define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */
147	#define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */
148	#define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */
149	#define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */
150
151	#define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */
152	#define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */
153	#define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */
154	#define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */
155
156	#define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */
157	#define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */
158	#define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */
159	#define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */
160
161	#define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */
162	#define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */
163	#define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */
164	#define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */
165
166	#define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */
167	#define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */
168
169	/* 24 bpp RGB */
170	#define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */
171	#define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */
172
173	/* 32 bpp RGB */
174	#define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */
175	#define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */
176	#define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */
177	#define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */
178
179	#define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */
180	#define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */
181	#define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */
182	#define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */
183
184	#define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */
185	#define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */
186	#define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */
187	#define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */
188
189	#define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */
190	#define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */
191	#define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */
192	#define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */
193
194	/* 48 bpp RGB */
195	#define DRM_FORMAT_RGB161616 fourcc_code('R', 'G', '4', '8') /* [47:0] R:G:B 16:16:16 little endian */
196	#define DRM_FORMAT_BGR161616 fourcc_code('B', 'G', '4', '8') /* [47:0] B:G:R 16:16:16 little endian */
197
198	/* 64 bpp RGB */
199	#define DRM_FORMAT_XRGB16161616 fourcc_code('X', 'R', '4', '8') /* [63:0] x:R:G:B 16:16:16:16 little endian */
200	#define DRM_FORMAT_XBGR16161616 fourcc_code('X', 'B', '4', '8') /* [63:0] x:B:G:R 16:16:16:16 little endian */
201
202	#define DRM_FORMAT_ARGB16161616 fourcc_code('A', 'R', '4', '8') /* [63:0] A:R:G:B 16:16:16:16 little endian */
203	#define DRM_FORMAT_ABGR16161616 fourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 little endian */
204
205	/*
206	* Half-Floating point - 16b/component
207	* IEEE 754-2008 binary16 half-precision float
208	* [15:0] sign:exponent:mantissa 1:5:10
209	*/
210	#define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */
211	#define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */
212
213	#define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */
214	#define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */
215
216	#define DRM_FORMAT_R16F fourcc_code('R', ' ', ' ', 'H') /* [15:0] R 16 little endian */
217	#define DRM_FORMAT_GR1616F fourcc_code('G', 'R', ' ', 'H') /* [31:0] G:R 16:16 little endian */
218	#define DRM_FORMAT_BGR161616F fourcc_code('B', 'G', 'R', 'H') /* [47:0] B:G:R 16:16:16 little endian */
219
220	/*
221	* Floating point - 32b/component
222	* IEEE 754-2008 binary32 float
223	* [31:0] sign:exponent:mantissa 1:8:23
224	*/
225	#define DRM_FORMAT_R32F fourcc_code('R', ' ', ' ', 'F') /* [31:0] R 32 little endian */
226	#define DRM_FORMAT_GR3232F fourcc_code('G', 'R', ' ', 'F') /* [63:0] G:R 32:32 little endian */
227	#define DRM_FORMAT_BGR323232F fourcc_code('B', 'G', 'R', 'F') /* [95:0] B:G:R 32:32:32 little endian */
228	#define DRM_FORMAT_ABGR32323232F fourcc_code('A', 'B', '8', 'F') /* [127:0] A:B:G:R 32:32:32:32 little endian */
229
230	/*
231	* RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits
232	* of unused padding per component:
233	*/
234	#define DRM_FORMAT_AXBXGXRX106106106106 fourcc_code('A', 'B', '1', '0') /* [63:0] A:x:B:x:G:x:R:x 10:6:10:6:10:6:10:6 little endian */
235
236	/* packed YCbCr */
237	#define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
238	#define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
239	#define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */
240	#define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
241
242	#define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
243	#define DRM_FORMAT_AVUY8888 fourcc_code('A', 'V', 'U', 'Y') /* [31:0] A:Cr:Cb:Y 8:8:8:8 little endian */
244	#define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
245	#define DRM_FORMAT_XVUY8888 fourcc_code('X', 'V', 'U', 'Y') /* [31:0] X:Cr:Cb:Y 8:8:8:8 little endian */
246	#define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */
247	#define DRM_FORMAT_VUY101010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */
248	#define DRM_FORMAT_XVUY2101010 fourcc_code('X', 'Y', '3', '0') /* [31:0] x:Cr:Cb:Y 2:10:10:10 little endian */
249
250	/*
251	* packed Y2xx indicate for each component, xx valid data occupy msb
252	* 16-xx padding occupy lsb
253	*/
254	#define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 10:6:10:6:10:6:10:6 little endian per 2 Y pixels */
255	#define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 12:4:12:4:12:4:12:4 little endian per 2 Y pixels */
256	#define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0] Cr0:Y1:Cb0:Y0 16:16:16:16 little endian per 2 Y pixels */
257
258	/*
259	* packed Y4xx indicate for each component, xx valid data occupy msb
260	* 16-xx padding occupy lsb except Y410
261	*/
262	#define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 little endian */
263	#define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */
264	#define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 little endian */
265
266	#define DRM_FORMAT_XVYU2101010 fourcc_code('X', 'V', '3', '0') /* [31:0] X:Cr:Y:Cb 2:10:10:10 little endian */
267	#define DRM_FORMAT_XVYU12_16161616 fourcc_code('X', 'V', '3', '6') /* [63:0] X:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */
268	#define DRM_FORMAT_XVYU16161616 fourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 little endian */
269
270	/*
271	* packed YCbCr420 2x2 tiled formats
272	* first 64 bits will contain Y,Cb,Cr components for a 2x2 tile
273	*/
274	/* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
275	#define DRM_FORMAT_Y0L0 fourcc_code('Y', '0', 'L', '0')
276	/* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
277	#define DRM_FORMAT_X0L0 fourcc_code('X', '0', 'L', '0')
278
279	/* [63:0] A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
280	#define DRM_FORMAT_Y0L2 fourcc_code('Y', '0', 'L', '2')
281	/* [63:0] X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
282	#define DRM_FORMAT_X0L2 fourcc_code('X', '0', 'L', '2')
283
284	/*
285	* 1-plane YUV 4:2:0
286	* In these formats, the component ordering is specified (Y, followed by U
287	* then V), but the exact Linear layout is undefined.
288	* These formats can only be used with a non-Linear modifier.
289	*/
290	#define DRM_FORMAT_YUV420_8BIT fourcc_code('Y', 'U', '0', '8')
291	#define DRM_FORMAT_YUV420_10BIT fourcc_code('Y', 'U', '1', '0')
292
293	/*
294	* 2 plane RGB + A
295	* index 0 = RGB plane, same format as the corresponding non _A8 format has
296	* index 1 = A plane, [7:0] A
297	*/
298	#define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8')
299	#define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8')
300	#define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8')
301	#define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8')
302	#define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8')
303	#define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8')
304	#define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8')
305	#define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8')
306
307	/*
308	* 2 plane YCbCr
309	* index 0 = Y plane, [7:0] Y
310	* index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian
311	* or
312	* index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian
313	*/
314	#define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */
315	#define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */
316	#define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */
317	#define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
318	#define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
319	#define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
320	/*
321	* 2 plane YCbCr
322	* index 0 = Y plane, [39:0] Y3:Y2:Y1:Y0 little endian
323	* index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian
324	*/
325	#define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */
326	#define DRM_FORMAT_NV20 fourcc_code('N', 'V', '2', '0') /* 2x1 subsampled Cr:Cb plane */
327	#define DRM_FORMAT_NV30 fourcc_code('N', 'V', '3', '0') /* non-subsampled Cr:Cb plane */
328
329	/*
330	* 2 plane YCbCr MSB aligned
331	* index 0 = Y plane, [15:0] Y:x [10:6] little endian
332	* index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
333	*/
334	#define DRM_FORMAT_P210 fourcc_code('P', '2', '1', '0') /* 2x1 subsampled Cr:Cb plane, 10 bit per channel */
335
336	/*
337	* 2 plane YCbCr MSB aligned
338	* index 0 = Y plane, [15:0] Y:x [10:6] little endian
339	* index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
340	*/
341	#define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */
342
343	/*
344	* 2 plane YCbCr MSB aligned
345	* index 0 = Y plane, [15:0] Y:x [12:4] little endian
346	* index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian
347	*/
348	#define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */
349
350	/*
351	* 2 plane YCbCr MSB aligned
352	* index 0 = Y plane, [15:0] Y little endian
353	* index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian
354	*/
355	#define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */
356
357	/* 2 plane YCbCr420.
358	* 3 10 bit components and 2 padding bits packed into 4 bytes.
359	* index 0 = Y plane, [31:0] x:Y2:Y1:Y0 2:10:10:10 little endian
360	* index 1 = Cr:Cb plane, [63:0] x:Cr2:Cb2:Cr1:x:Cb1:Cr0:Cb0 [2:10:10:10:2:10:10:10] little endian
361	*/
362	#define DRM_FORMAT_P030 fourcc_code('P', '0', '3', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel packed */
363
364	/*
365	* 2 plane YCbCr422.
366	* 3 10 bit components and 2 padding bits packed into 4 bytes.
367	* index 0 = Y plane, [31:0] x:Y2:Y1:Y0 2:10:10:10 little endian
368	* index 1 = Cr:Cb plane, [63:0] x:Cr2:Cb2:Cr1:x:Cb1:Cr0:Cb0 [2:10:10:10:2:10:10:10] little endian
369	*/
370	#define DRM_FORMAT_P230 fourcc_code('P', '2', '3', '0') /* 2x1 subsampled Cr:Cb plane 10 bits per channel packed */
371
372	/* 3 plane non-subsampled (444) YCbCr
373	* 16 bits per component, but only 10 bits are used and 6 bits are padded
374	* index 0: Y plane, [15:0] Y:x [10:6] little endian
375	* index 1: Cb plane, [15:0] Cb:x [10:6] little endian
376	* index 2: Cr plane, [15:0] Cr:x [10:6] little endian
377	*/
378	#define DRM_FORMAT_Q410 fourcc_code('Q', '4', '1', '0')
379
380	/* 3 plane non-subsampled (444) YCrCb
381	* 16 bits per component, but only 10 bits are used and 6 bits are padded
382	* index 0: Y plane, [15:0] Y:x [10:6] little endian
383	* index 1: Cr plane, [15:0] Cr:x [10:6] little endian
384	* index 2: Cb plane, [15:0] Cb:x [10:6] little endian
385	*/
386	#define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1')
387
388	/*
389	* 3 plane non-subsampled (444) YCbCr LSB aligned
390	* 10 bpc, 30 bits per sample image data in a single contiguous buffer.
391	* index 0: Y plane, [31:0] x:Y2:Y1:Y0 [2:10:10:10] little endian
392	* index 1: Cb plane, [31:0] x:Cb2:Cb1:Cb0 [2:10:10:10] little endian
393	* index 2: Cr plane, [31:0] x:Cr2:Cr1:Cr0 [2:10:10:10] little endian
394	*/
395	#define DRM_FORMAT_T430 fourcc_code('T', '4', '3', '0')
396
397	/*
398	* 3 plane YCbCr LSB aligned
399	* In order to use these formats in a similar fashion to MSB aligned ones
400	* implementation can multiply the values by 2^6=64. For that reason the padding
401	* must only contain zeros.
402	* index 0 = Y plane, [15:0] z:Y [6:10] little endian
403	* index 1 = Cb plane, [15:0] z:Cb [6:10] little endian
404	* index 2 = Cr plane, [15:0] z:Cr [6:10] little endian
405	*/
406	#define DRM_FORMAT_S010 fourcc_code('S', '0', '1', '0') /* 2x2 subsampled Cb (1) and Cr (2) planes 10 bits per channel */
407	#define DRM_FORMAT_S210 fourcc_code('S', '2', '1', '0') /* 2x1 subsampled Cb (1) and Cr (2) planes 10 bits per channel */
408	#define DRM_FORMAT_S410 fourcc_code('S', '4', '1', '0') /* non-subsampled Cb (1) and Cr (2) planes 10 bits per channel */
409
410	/*
411	* 3 plane YCbCr LSB aligned
412	* In order to use these formats in a similar fashion to MSB aligned ones
413	* implementation can multiply the values by 2^4=16. For that reason the padding
414	* must only contain zeros.
415	* index 0 = Y plane, [15:0] z:Y [4:12] little endian
416	* index 1 = Cb plane, [15:0] z:Cb [4:12] little endian
417	* index 2 = Cr plane, [15:0] z:Cr [4:12] little endian
418	*/
419	#define DRM_FORMAT_S012 fourcc_code('S', '0', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes 12 bits per channel */
420	#define DRM_FORMAT_S212 fourcc_code('S', '2', '1', '2') /* 2x1 subsampled Cb (1) and Cr (2) planes 12 bits per channel */
421	#define DRM_FORMAT_S412 fourcc_code('S', '4', '1', '2') /* non-subsampled Cb (1) and Cr (2) planes 12 bits per channel */
422
423	/*
424	* 3 plane YCbCr
425	* index 0 = Y plane, [15:0] Y little endian
426	* index 1 = Cb plane, [15:0] Cb little endian
427	* index 2 = Cr plane, [15:0] Cr little endian
428	*/
429	#define DRM_FORMAT_S016 fourcc_code('S', '0', '1', '6') /* 2x2 subsampled Cb (1) and Cr (2) planes 16 bits per channel */
430	#define DRM_FORMAT_S216 fourcc_code('S', '2', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes 16 bits per channel */
431	#define DRM_FORMAT_S416 fourcc_code('S', '4', '1', '6') /* non-subsampled Cb (1) and Cr (2) planes 16 bits per channel */
432
433	/*
434	* 3 plane YCbCr
435	* index 0: Y plane, [7:0] Y
436	* index 1: Cb plane, [7:0] Cb
437	* index 2: Cr plane, [7:0] Cr
438	* or
439	* index 1: Cr plane, [7:0] Cr
440	* index 2: Cb plane, [7:0] Cb
441	*/
442	#define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */
443	#define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */
444	#define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */
445	#define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */
446	#define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */
447	#define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */
448	#define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */
449	#define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */
450	#define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */
451	#define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */
452
453	/*
454	* Y-only (greyscale) formats
455	*
456	* The Y-only formats are handled similarly to the YCbCr formats in the display
457	* pipeline, with the Cb and Cr implicitly neutral (0.0 in nominal values). This
458	* also means that COLOR_RANGE property applies to the Y-only formats.
459	*/
460
461	#define DRM_FORMAT_Y8 fourcc_code('G', 'R', 'E', 'Y') /* 8-bit Y-only */
462	#define DRM_FORMAT_XYYY2101010 fourcc_code('Y', 'P', 'A', '4') /* [31:0] x:Y2:Y1:Y0 2:10:10:10 little endian */
463
464	/*
465	* Format Modifiers:
466	*
467	* Format modifiers describe, typically, a re-ordering or modification
468	* of the data in a plane of an FB. This can be used to express tiled/
469	* swizzled formats, or compression, or a combination of the two.
470	*
471	* The upper 8 bits of the format modifier are a vendor-id as assigned
472	* below. The lower 56 bits are assigned as vendor sees fit.
473	*/
474
475	/* Vendor Ids: */
476	#define DRM_FORMAT_MOD_VENDOR_NONE 0
477	#define DRM_FORMAT_MOD_VENDOR_INTEL 0x01
478	#define DRM_FORMAT_MOD_VENDOR_AMD 0x02
479	#define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03
480	#define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
481	#define DRM_FORMAT_MOD_VENDOR_QCOM 0x05
482	#define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
483	#define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07
484	#define DRM_FORMAT_MOD_VENDOR_ARM 0x08
485	#define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09
486	#define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a
487	#define DRM_FORMAT_MOD_VENDOR_MTK 0x0b
488	#define DRM_FORMAT_MOD_VENDOR_APPLE 0x0c
489
490	/* add more to the end as needed */
491
492	#define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
493
494	#define fourcc_mod_get_vendor(modifier) \
495	(((modifier) >> 56) & 0xff)
496
497	#define fourcc_mod_is_vendor(modifier, vendor) \
498	(fourcc_mod_get_vendor(modifier) == DRM_FORMAT_MOD_VENDOR_## vendor)
499
500	#define fourcc_mod_code(vendor, val) \
501	((((uint64_t)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) \| ((val) & 0x00ffffffffffffffULL))
502
503	/*
504	* Format Modifier tokens:
505	*
506	* When adding a new token please document the layout with a code comment,
507	* similar to the fourcc codes above. drm_fourcc.h is considered the
508	* authoritative source for all of these.
509	*
510	* Generic modifier names:
511	*
512	* DRM_FORMAT_MOD_GENERIC_* definitions are used to provide vendor-neutral names
513	* for layouts which are common across multiple vendors. To preserve
514	* compatibility, in cases where a vendor-specific definition already exists and
515	* a generic name for it is desired, the common name is a purely symbolic alias
516	* and must use the same numerical value as the original definition.
517	*
518	* Note that generic names should only be used for modifiers which describe
519	* generic layouts (such as pixel re-ordering), which may have
520	* independently-developed support across multiple vendors.
521	*
522	* In future cases where a generic layout is identified before merging with a
523	* vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor
524	* 'NONE' could be considered. This should only be for obvious, exceptional
525	* cases to avoid polluting the 'GENERIC' namespace with modifiers which only
526	* apply to a single vendor.
527	*
528	* Generic names should not be used for cases where multiple hardware vendors
529	* have implementations of the same standardised compression scheme (such as
530	* AFBC). In those cases, all implementations should use the same format
531	* modifier(s), reflecting the vendor of the standard.
532	*/
533
534	#define DRM_FORMAT_MOD_GENERIC_16_16_TILE DRM_FORMAT_MOD_SAMSUNG_16_16_TILE
535
536	/*
537	* Invalid Modifier
538	*
539	* This modifier can be used as a sentinel to terminate the format modifiers
540	* list, or to initialize a variable with an invalid modifier. It might also be
541	* used to report an error back to userspace for certain APIs.
542	*/
543	#define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED)
544
545	/*
546	* Linear Layout
547	*
548	* Just plain linear layout. Note that this is different from no specifying any
549	* modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl),
550	* which tells the driver to also take driver-internal information into account
551	* and so might actually result in a tiled framebuffer.
552	*/
553	#define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0)
554
555	/*
556	* Deprecated: use DRM_FORMAT_MOD_LINEAR instead
557	*
558	* The "none" format modifier doesn't actually mean that the modifier is
559	* implicit, instead it means that the layout is linear. Whether modifiers are
560	* used is out-of-band information carried in an API-specific way (e.g. in a
561	* flag for drm_mode_fb_cmd2).
562	*/
563	#define DRM_FORMAT_MOD_NONE 0
564
565	/* Intel framebuffer modifiers */
566
567	/*
568	* Intel X-tiling layout
569	*
570	* This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
571	* in row-major layout. Within the tile bytes are laid out row-major, with
572	* a platform-dependent stride. On top of that the memory can apply
573	* platform-depending swizzling of some higher address bits into bit6.
574	*
575	* Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
576	* On earlier platforms the is highly platforms specific and not useful for
577	* cross-driver sharing. It exists since on a given platform it does uniquely
578	* identify the layout in a simple way for i915-specific userspace, which
579	* facilitated conversion of userspace to modifiers. Additionally the exact
580	* format on some really old platforms is not known.
581	*/
582	#define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1)
583
584	/*
585	* Intel Y-tiling layout
586	*
587	* This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
588	* in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
589	* chunks column-major, with a platform-dependent height. On top of that the
590	* memory can apply platform-depending swizzling of some higher address bits
591	* into bit6.
592	*
593	* Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
594	* On earlier platforms the is highly platforms specific and not useful for
595	* cross-driver sharing. It exists since on a given platform it does uniquely
596	* identify the layout in a simple way for i915-specific userspace, which
597	* facilitated conversion of userspace to modifiers. Additionally the exact
598	* format on some really old platforms is not known.
599	*/
600	#define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2)
601
602	/*
603	* Intel Yf-tiling layout
604	*
605	* This is a tiled layout using 4Kb tiles in row-major layout.
606	* Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
607	* are arranged in four groups (two wide, two high) with column-major layout.
608	* Each group therefore consists out of four 256 byte units, which are also laid
609	* out as 2x2 column-major.
610	* 256 byte units are made out of four 64 byte blocks of pixels, producing
611	* either a square block or a 2:1 unit.
612	* 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width
613	* in pixel depends on the pixel depth.
614	*/
615	#define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)
616
617	/*
618	* Intel color control surface (CCS) for render compression
619	*
620	* The framebuffer format must be one of the 8:8:8:8 RGB formats.
621	* The main surface will be plane index 0 and must be Y/Yf-tiled,
622	* the CCS will be plane index 1.
623	*
624	* Each CCS tile matches a 1024x512 pixel area of the main surface.
625	* To match certain aspects of the 3D hardware the CCS is
626	* considered to be made up of normal 128Bx32 Y tiles, Thus
627	* the CCS pitch must be specified in multiples of 128 bytes.
628	*
629	* In reality the CCS tile appears to be a 64Bx64 Y tile, composed
630	* of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks.
631	* But that fact is not relevant unless the memory is accessed
632	* directly.
633	*/
634	#define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4)
635	#define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5)
636
637	/*
638	* Intel color control surfaces (CCS) for Gen-12 render compression.
639	*
640	* The main surface is Y-tiled and at plane index 0, the CCS is linear and
641	* at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
642	* main surface. In other words, 4 bits in CCS map to a main surface cache
643	* line pair. The main surface pitch is required to be a multiple of four
644	* Y-tile widths.
645	*/
646	#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
647
648	/*
649	* Intel color control surfaces (CCS) for Gen-12 media compression
650	*
651	* The main surface is Y-tiled and at plane index 0, the CCS is linear and
652	* at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
653	* main surface. In other words, 4 bits in CCS map to a main surface cache
654	* line pair. The main surface pitch is required to be a multiple of four
655	* Y-tile widths. For semi-planar formats like NV12, CCS planes follow the
656	* Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,
657	* planes 2 and 3 for the respective CCS.
658	*/
659	#define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
660
661	/*
662	* Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
663	* compression.
664	*
665	* The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
666	* and at index 1. The clear color is stored at index 2, and the pitch should
667	* be 64 bytes aligned. The clear color structure is 256 bits. The first 128 bits
668	* represents Raw Clear Color Red, Green, Blue and Alpha color each represented
669	* by 32 bits. The raw clear color is consumed by the 3d engine and generates
670	* the converted clear color of size 64 bits. The first 32 bits store the Lower
671	* Converted Clear Color value and the next 32 bits store the Higher Converted
672	* Clear Color value when applicable. The Converted Clear Color values are
673	* consumed by the DE. The last 64 bits are used to store Color Discard Enable
674	* and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
675	* corresponds to an area of 4x1 tiles in the main surface. The main surface
676	* pitch is required to be a multiple of 4 tile widths.
677	*/
678	#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
679
680	/*
681	* Intel Tile 4 layout
682	*
683	* This is a tiled layout using 4KB tiles in a row-major layout. It has the same
684	* shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It
685	* only differs from Tile Y at the 256B granularity in between. At this
686	* granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape
687	* of 64B x 8 rows.
688	*/
689	#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9)
690
691	/*
692	* Intel color control surfaces (CCS) for DG2 render compression.
693	*
694	* The main surface is Tile 4 and at plane index 0. The CCS data is stored
695	* outside of the GEM object in a reserved memory area dedicated for the
696	* storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
697	* main surface pitch is required to be a multiple of four Tile 4 widths.
698	*/
699	#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS fourcc_mod_code(INTEL, 10)
700
701	/*
702	* Intel color control surfaces (CCS) for DG2 media compression.
703	*
704	* The main surface is Tile 4 and at plane index 0. For semi-planar formats
705	* like NV12, the Y and UV planes are Tile 4 and are located at plane indices
706	* 0 and 1, respectively. The CCS for all planes are stored outside of the
707	* GEM object in a reserved memory area dedicated for the storage of the
708	* CCS data for all RC/RC_CC/MC compressible GEM objects. The main surface
709	* pitch is required to be a multiple of four Tile 4 widths.
710	*/
711	#define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 11)
712
713	/*
714	* Intel Color Control Surface with Clear Color (CCS) for DG2 render compression.
715	*
716	* The main surface is Tile 4 and at plane index 0. The CCS data is stored
717	* outside of the GEM object in a reserved memory area dedicated for the
718	* storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
719	* main surface pitch is required to be a multiple of four Tile 4 widths. The
720	* clear color is stored at plane index 1 and the pitch should be 64 bytes
721	* aligned. The format of the 256 bits of clear color data matches the one used
722	* for the I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier, see its description
723	* for details.
724	*/
725	#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12)
726
727	/*
728	* Intel Color Control Surfaces (CCS) for display ver. 14 render compression.
729	*
730	* The main surface is tile4 and at plane index 0, the CCS is linear and
731	* at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
732	* main surface. In other words, 4 bits in CCS map to a main surface cache
733	* line pair. The main surface pitch is required to be a multiple of four
734	* tile4 widths.
735	*/
736	#define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS fourcc_mod_code(INTEL, 13)
737
738	/*
739	* Intel Color Control Surfaces (CCS) for display ver. 14 media compression
740	*
741	* The main surface is tile4 and at plane index 0, the CCS is linear and
742	* at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
743	* main surface. In other words, 4 bits in CCS map to a main surface cache
744	* line pair. The main surface pitch is required to be a multiple of four
745	* tile4 widths. For semi-planar formats like NV12, CCS planes follow the
746	* Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,
747	* planes 2 and 3 for the respective CCS.
748	*/
749	#define I915_FORMAT_MOD_4_TILED_MTL_MC_CCS fourcc_mod_code(INTEL, 14)
750
751	/*
752	* Intel Color Control Surface with Clear Color (CCS) for display ver. 14 render
753	* compression.
754	*
755	* The main surface is tile4 and is at plane index 0 whereas CCS is linear
756	* and at index 1. The clear color is stored at index 2, and the pitch should
757	* be ignored. The clear color structure is 256 bits. The first 128 bits
758	* represents Raw Clear Color Red, Green, Blue and Alpha color each represented
759	* by 32 bits. The raw clear color is consumed by the 3d engine and generates
760	* the converted clear color of size 64 bits. The first 32 bits store the Lower
761	* Converted Clear Color value and the next 32 bits store the Higher Converted
762	* Clear Color value when applicable. The Converted Clear Color values are
763	* consumed by the DE. The last 64 bits are used to store Color Discard Enable
764	* and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
765	* corresponds to an area of 4x1 tiles in the main surface. The main surface
766	* pitch is required to be a multiple of 4 tile widths.
767	*/
768	#define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC fourcc_mod_code(INTEL, 15)
769
770	/*
771	* Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression
772	* on integrated graphics
773	*
774	* The main surface is Tile 4 and at plane index 0. For semi-planar formats
775	* like NV12, the Y and UV planes are Tile 4 and are located at plane indices
776	* 0 and 1, respectively. The CCS for all planes are stored outside of the
777	* GEM object in a reserved memory area dedicated for the storage of the
778	* CCS data for all compressible GEM objects.
779	*/
780	#define I915_FORMAT_MOD_4_TILED_LNL_CCS fourcc_mod_code(INTEL, 16)
781
782	/*
783	* Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression
784	* on discrete graphics
785	*
786	* The main surface is Tile 4 and at plane index 0. For semi-planar formats
787	* like NV12, the Y and UV planes are Tile 4 and are located at plane indices
788	* 0 and 1, respectively. The CCS for all planes are stored outside of the
789	* GEM object in a reserved memory area dedicated for the storage of the
790	* CCS data for all compressible GEM objects. The GEM object must be stored in
791	* contiguous memory with a size aligned to 64KB
792	*/
793	#define I915_FORMAT_MOD_4_TILED_BMG_CCS fourcc_mod_code(INTEL, 17)
794
795	/*
796	* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
797	*
798	* Macroblocks are laid in a Z-shape, and each pixel data is following the
799	* standard NV12 style.
800	* As for NV12, an image is the result of two frame buffers: one for Y,
801	* one for the interleaved Cb/Cr components (1/2 the height of the Y buffer).
802	* Alignment requirements are (for each buffer):
803	* - multiple of 128 pixels for the width
804	* - multiple of 32 pixels for the height
805	*
806	* For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html
807	*/
808	#define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
809
810	/*
811	* Tiled, 16 (pixels) x 16 (lines) - sized macroblocks
812	*
813	* This is a simple tiled layout using tiles of 16x16 pixels in a row-major
814	* layout. For YCbCr formats Cb/Cr components are taken in such a way that
815	* they correspond to their 16x16 luma block.
816	*/
817	#define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE fourcc_mod_code(SAMSUNG, 2)
818
819	/*
820	* Qualcomm Compressed Format
821	*
822	* Refers to a compressed variant of the base format that is compressed.
823	* Implementation may be platform and base-format specific.
824	*
825	* Each macrotile consists of m x n (mostly 4 x 4) tiles.
826	* Pixel data pitch/stride is aligned with macrotile width.
827	* Pixel data height is aligned with macrotile height.
828	* Entire pixel data buffer is aligned with 4k(bytes).
829	*/
830	#define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1)
831
832	/*
833	* Qualcomm Tiled Format
834	*
835	* Similar to DRM_FORMAT_MOD_QCOM_COMPRESSED but not compressed.
836	* Implementation may be platform and base-format specific.
837	*
838	* Each macrotile consists of m x n (mostly 4 x 4) tiles.
839	* Pixel data pitch/stride is aligned with macrotile width.
840	* Pixel data height is aligned with macrotile height.
841	* Entire pixel data buffer is aligned with 4k(bytes).
842	*/
843	#define DRM_FORMAT_MOD_QCOM_TILED3 fourcc_mod_code(QCOM, 3)
844
845	/*
846	* Qualcomm Alternate Tiled Format
847	*
848	* Alternate tiled format typically only used within GMEM.
849	* Implementation may be platform and base-format specific.
850	*/
851	#define DRM_FORMAT_MOD_QCOM_TILED2 fourcc_mod_code(QCOM, 2)
852
853
854	/* Vivante framebuffer modifiers */
855
856	/*
857	* Vivante 4x4 tiling layout
858	*
859	* This is a simple tiled layout using tiles of 4x4 pixels in a row-major
860	* layout.
861	*/
862	#define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1)
863
864	/*
865	* Vivante 64x64 super-tiling layout
866	*
867	* This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
868	* contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
869	* major layout.
870	*
871	* For more information: see
872	* https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling
873	*/
874	#define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2)
875
876	/*
877	* Vivante 4x4 tiling layout for dual-pipe
878	*
879	* Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
880	* different base address. Offsets from the base addresses are therefore halved
881	* compared to the non-split tiled layout.
882	*/
883	#define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3)
884
885	/*
886	* Vivante 64x64 super-tiling layout for dual-pipe
887	*
888	* Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
889	* starts at a different base address. Offsets from the base addresses are
890	* therefore halved compared to the non-split super-tiled layout.
891	*/
892	#define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
893
894	/*
895	* Vivante TS (tile-status) buffer modifiers. They can be combined with all of
896	* the color buffer tiling modifiers defined above. When TS is present it's a
897	* separate buffer containing the clear/compression status of each tile. The
898	* modifiers are defined as VIVANTE_MOD_TS_c_s, where c is the color buffer
899	* tile size in bytes covered by one entry in the status buffer and s is the
900	* number of status bits per entry.
901	* We reserve the top 8 bits of the Vivante modifier space for tile status
902	* clear/compression modifiers, as future cores might add some more TS layout
903	* variations.
904	*/
905	#define VIVANTE_MOD_TS_64_4 (1ULL << 48)
906	#define VIVANTE_MOD_TS_64_2 (2ULL << 48)
907	#define VIVANTE_MOD_TS_128_4 (3ULL << 48)
908	#define VIVANTE_MOD_TS_256_4 (4ULL << 48)
909	#define VIVANTE_MOD_TS_MASK (0xfULL << 48)
910
911	/*
912	* Vivante compression modifiers. Those depend on a TS modifier being present
913	* as the TS bits get reinterpreted as compression tags instead of simple
914	* clear markers when compression is enabled.
915	*/
916	#define VIVANTE_MOD_COMP_DEC400 (1ULL << 52)
917	#define VIVANTE_MOD_COMP_MASK (0xfULL << 52)
918
919	/* Masking out the extension bits will yield the base modifier. */
920	#define VIVANTE_MOD_EXT_MASK (VIVANTE_MOD_TS_MASK \| \
921	VIVANTE_MOD_COMP_MASK)
922
923	/* NVIDIA frame buffer modifiers */
924
925	/*
926	* Tegra Tiled Layout, used by Tegra 2, 3 and 4.
927	*
928	* Pixels are arranged in simple tiles of 16 x 16 bytes.
929	*/
930	#define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1)
931
932	/*
933	* Generalized Block Linear layout, used by desktop GPUs starting with NV50/G80,
934	* and Tegra GPUs starting with Tegra K1.
935	*
936	* Pixels are arranged in Groups of Bytes (GOBs). GOB size and layout varies
937	* based on the architecture generation. GOBs themselves are then arranged in
938	* 3D blocks, with the block dimensions (in terms of GOBs) always being a power
939	* of two, and hence expressible as their log2 equivalent (E.g., "2" represents
940	* a block depth or height of "4").
941	*
942	* Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
943	* in full detail.
944	*
945	* Macro
946	* Bits Param Description
947	* ---- ----- -----------------------------------------------------------------
948	*
949	* 3:0 h log2(height) of each block, in GOBs. Placed here for
950	* compatibility with the existing
951	* DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
952	*
953	* 4:4 - Must be 1, to indicate block-linear layout. Necessary for
954	* compatibility with the existing
955	* DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
956	*
957	* 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block
958	* size). Must be zero.
959	*
960	* Note there is no log2(width) parameter. Some portions of the
961	* hardware support a block width of two gobs, but it is impractical
962	* to use due to lack of support elsewhere, and has no known
963	* benefits.
964	*
965	* 11:9 - Reserved (To support 2D-array textures with variable array stride
966	* in blocks, specified via log2(tile width in blocks)). Must be
967	* zero.
968	*
969	* 19:12 k Page Kind. This value directly maps to a field in the page
970	* tables of all GPUs >= NV50. It affects the exact layout of bits
971	* in memory and can be derived from the tuple
972	*
973	* (format, GPU model, compression type, samples per pixel)
974	*
975	* Where compression type is defined below. If GPU model were
976	* implied by the format modifier, format, or memory buffer, page
977	* kind would not need to be included in the modifier itself, but
978	* since the modifier should define the layout of the associated
979	* memory buffer independent from any device or other context, it
980	* must be included here.
981	*
982	* 21:20 g GOB Height and Page Kind Generation. The height of a GOB changed
983	* starting with Fermi GPUs. Additionally, the mapping between page
984	* kind and bit layout has changed at various points.
985	*
986	* 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping
987	* 1 = Gob Height 4, G80 - GT2XX Page Kind mapping
988	* 2 = Gob Height 8, Turing+ Page Kind mapping
989	* 3 = Reserved for future use.
990	*
991	* 22:22 s Sector layout. There is a further bit remapping step that occurs
992	* 26:27 at an even lower level than the page kind and block linear
993	* swizzles. This causes the bit arrangement of surfaces in memory
994	* to differ subtly, and prevents direct sharing of surfaces between
995	* GPUs with different layouts.
996	*
997	* 0 = Tegra K1 - Tegra Parker/TX2 Layout
998	* 1 = Pre-GB20x, GB20x 32+ bpp, GB10, Tegra Xavier-Orin Layout
999	* 2 = GB20x(Blackwell 2)+ 8 bpp surface layout
1000	* 3 = GB20x(Blackwell 2)+ 16 bpp surface layout
1001	* 4 = Reserved for future use.
1002	* 5 = Reserved for future use.
1003	* 6 = Reserved for future use.
1004	* 7 = Reserved for future use.
1005	*
1006	* 25:23 c Lossless Framebuffer Compression type.
1007	*
1008	* 0 = none
1009	* 1 = ROP/3D, layout 1, exact compression format implied by Page
1010	* Kind field
1011	* 2 = ROP/3D, layout 2, exact compression format implied by Page
1012	* Kind field
1013	* 3 = CDE horizontal
1014	* 4 = CDE vertical
1015	* 5 = Reserved for future use
1016	* 6 = Reserved for future use
1017	* 7 = Reserved for future use
1018	*
1019	* 55:28 - Reserved for future use. Must be zero.
1020	*/
1021	#define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \
1022	fourcc_mod_code(NVIDIA, (0x10 \| \
1023	((h) & 0xf) \| \
1024	(((k) & 0xff) << 12) \| \
1025	(((g) & 0x3) << 20) \| \
1026	(((s) & 0x1) << 22) \| \
1027	(((s) & 0x6) << 25) \| \
1028	(((c) & 0x7) << 23)))
1029
1030	/* To grandfather in prior block linear format modifiers to the above layout,
1031	* the page kind "0", which corresponds to "pitch/linear" and hence is unusable
1032	* with block-linear layouts, is remapped within drivers to the value 0xfe,
1033	* which corresponds to the "generic" kind used for simple single-sample
1034	* uncompressed color formats on Fermi - Volta GPUs.
1035	*/
1036	static inline uint64_t
1037	drm_fourcc_canonicalize_nvidia_format_mod(uint64_t modifier)
1038	{
1039	if (!(modifier & 0x10) \|\| (modifier & (0xff << 12)))
1040	return modifier;
1041	else
1042	return modifier \| (0xfe << 12);
1043	}
1044
1045	/*
1046	* 16Bx2 Block Linear layout, used by Tegra K1 and later
1047	*
1048	* Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked
1049	* vertically by a power of 2 (1 to 32 GOBs) to form a block.
1050	*
1051	* Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
1052	*
1053	* Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically.
1054	* Valid values are:
1055	*
1056	* 0 == ONE_GOB
1057	* 1 == TWO_GOBS
1058	* 2 == FOUR_GOBS
1059	* 3 == EIGHT_GOBS
1060	* 4 == SIXTEEN_GOBS
1061	* 5 == THIRTYTWO_GOBS
1062	*
1063	* Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
1064	* in full detail.
1065	*/
1066	#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \
1067	DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 0, 0, 0, (v))
1068
1069	#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \
1070	DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0)
1071	#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \
1072	DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1)
1073	#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \
1074	DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2)
1075	#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \
1076	DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3)
1077	#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \
1078	DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4)
1079	#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \
1080	DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5)
1081
1082	/*
1083	* Some Broadcom modifiers take parameters, for example the number of
1084	* vertical lines in the image. Reserve the lower 32 bits for modifier
1085	* type, and the next 24 bits for parameters. Top 8 bits are the
1086	* vendor code.
1087	*/
1088	#define __fourcc_mod_broadcom_param_shift 8
1089	#define __fourcc_mod_broadcom_param_bits 48
1090	#define fourcc_mod_broadcom_code(val, params) \
1091	fourcc_mod_code(BROADCOM, ((((uint64_t)params) << __fourcc_mod_broadcom_param_shift) \| val))
1092	#define fourcc_mod_broadcom_param(m) \
1093	((int)(((m) >> __fourcc_mod_broadcom_param_shift) & \
1094	((1ULL << __fourcc_mod_broadcom_param_bits) - 1)))
1095	#define fourcc_mod_broadcom_mod(m) \
1096	((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \
1097	__fourcc_mod_broadcom_param_shift))
1098
1099	/*
1100	* Broadcom VC4 "T" format
1101	*
1102	* This is the primary layout that the V3D GPU can texture from (it
1103	* can't do linear). The T format has:
1104	*
1105	* - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4
1106	* pixels at 32 bit depth.
1107	*
1108	* - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
1109	* 16x16 pixels).
1110	*
1111	* - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On
1112	* even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows
1113	* they're (TR, BR, BL, TL), where bottom left is start of memory.
1114	*
1115	* - an image made of 4k tiles in rows either left-to-right (even rows of 4k
1116	* tiles) or right-to-left (odd rows of 4k tiles).
1117	*/
1118	#define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)
1119
1120	/*
1121	* Broadcom SAND format
1122	*
1123	* This is the native format that the H.264 codec block uses. For VC4
1124	* HVS, it is only valid for H.264 (NV12/21) and RGBA modes.
1125	*
1126	* The image can be considered to be split into columns, and the
1127	* columns are placed consecutively into memory. The width of those
1128	* columns can be either 32, 64, 128, or 256 pixels, but in practice
1129	* only 128 pixel columns are used.
1130	*
1131	* The pitch between the start of each column is set to optimally
1132	* switch between SDRAM banks. This is passed as the number of lines
1133	* of column width in the modifier (we can't use the stride value due
1134	* to various core checks that look at it , so you should set the
1135	* stride to width*cpp).
1136	*
1137	* Note that the column height for this format modifier is the same
1138	* for all of the planes, assuming that each column contains both Y
1139	* and UV. Some SAND-using hardware stores UV in a separate tiled
1140	* image from Y to reduce the column height, which is not supported
1141	* with these modifiers.
1142	*
1143	* The DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT modifier is also
1144	* supported for DRM_FORMAT_P030 where the columns remain as 128 bytes
1145	* wide, but as this is a 10 bpp format that translates to 96 pixels.
1146	*/
1147
1148	#define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \
1149	fourcc_mod_broadcom_code(2, v)
1150	#define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \
1151	fourcc_mod_broadcom_code(3, v)
1152	#define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \
1153	fourcc_mod_broadcom_code(4, v)
1154	#define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \
1155	fourcc_mod_broadcom_code(5, v)
1156
1157	#define DRM_FORMAT_MOD_BROADCOM_SAND32 \
1158	DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0)
1159	#define DRM_FORMAT_MOD_BROADCOM_SAND64 \
1160	DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0)
1161	#define DRM_FORMAT_MOD_BROADCOM_SAND128 \
1162	DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0)
1163	#define DRM_FORMAT_MOD_BROADCOM_SAND256 \
1164	DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0)
1165
1166	/* Broadcom UIF format
1167	*
1168	* This is the common format for the current Broadcom multimedia
1169	* blocks, including V3D 3.x and newer, newer video codecs, and
1170	* displays.
1171	*
1172	* The image consists of utiles (64b blocks), UIF blocks (2x2 utiles),
1173	* and macroblocks (4x4 UIF blocks). Those 4x4 UIF block groups are
1174	* stored in columns, with padding between the columns to ensure that
1175	* moving from one column to the next doesn't hit the same SDRAM page
1176	* bank.
1177	*
1178	* To calculate the padding, it is assumed that each hardware block
1179	* and the software driving it knows the platform's SDRAM page size,
1180	* number of banks, and XOR address, and that it's identical between
1181	* all blocks using the format. This tiling modifier will use XOR as
1182	* necessary to reduce the padding. If a hardware block can't do XOR,
1183	* the assumption is that a no-XOR tiling modifier will be created.
1184	*/
1185	#define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6)
1186
1187	/*
1188	* Arm Framebuffer Compression (AFBC) modifiers
1189	*
1190	* AFBC is a proprietary lossless image compression protocol and format.
1191	* It provides fine-grained random access and minimizes the amount of data
1192	* transferred between IP blocks.
1193	*
1194	* AFBC has several features which may be supported and/or used, which are
1195	* represented using bits in the modifier. Not all combinations are valid,
1196	* and different devices or use-cases may support different combinations.
1197	*
1198	* Further information on the use of AFBC modifiers can be found in
1199	* Documentation/gpu/afbc.rst
1200	*/
1201
1202	/*
1203	* The top 4 bits (out of the 56 bits allotted for specifying vendor specific
1204	* modifiers) denote the category for modifiers. Currently we have three
1205	* categories of modifiers ie AFBC, MISC and AFRC. We can have a maximum of
1206	* sixteen different categories.
1207	*/
1208	#define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \
1209	fourcc_mod_code(ARM, ((uint64_t)(__type) << 52) \| ((__val) & 0x000fffffffffffffULL))
1210
1211	#define DRM_FORMAT_MOD_ARM_TYPE_AFBC 0x00
1212	#define DRM_FORMAT_MOD_ARM_TYPE_MISC 0x01
1213
1214	#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) \
1215	DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode)
1216
1217	/*
1218	* AFBC superblock size
1219	*
1220	* Indicates the superblock size(s) used for the AFBC buffer. The buffer
1221	* size (in pixels) must be aligned to a multiple of the superblock size.
1222	* Four lowest significant bits(LSBs) are reserved for block size.
1223	*
1224	* Where one superblock size is specified, it applies to all planes of the
1225	* buffer (e.g. 16x16, 32x8). When multiple superblock sizes are specified,
1226	* the first applies to the Luma plane and the second applies to the Chroma
1227	* plane(s). e.g. (32x8_64x4 means 32x8 Luma, with 64x4 Chroma).
1228	* Multiple superblock sizes are only valid for multi-plane YCbCr formats.
1229	*/
1230	#define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf
1231	#define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL)
1232	#define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL)
1233	#define AFBC_FORMAT_MOD_BLOCK_SIZE_64x4 (3ULL)
1234	#define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL)
1235
1236	/*
1237	* AFBC lossless colorspace transform
1238	*
1239	* Indicates that the buffer makes use of the AFBC lossless colorspace
1240	* transform.
1241	*/
1242	#define AFBC_FORMAT_MOD_YTR (1ULL << 4)
1243
1244	/*
1245	* AFBC block-split
1246	*
1247	* Indicates that the payload of each superblock is split. The second
1248	* half of the payload is positioned at a predefined offset from the start
1249	* of the superblock payload.
1250	*/
1251	#define AFBC_FORMAT_MOD_SPLIT (1ULL << 5)
1252
1253	/*
1254	* AFBC sparse layout
1255	*
1256	* This flag indicates that the payload of each superblock must be stored at a
1257	* predefined position relative to the other superblocks in the same AFBC
1258	* buffer. This order is the same order used by the header buffer. In this mode
1259	* each superblock is given the same amount of space as an uncompressed
1260	* superblock of the particular format would require, rounding up to the next
1261	* multiple of 128 bytes in size.
1262	*/
1263	#define AFBC_FORMAT_MOD_SPARSE (1ULL << 6)
1264
1265	/*
1266	* AFBC copy-block restrict
1267	*
1268	* Buffers with this flag must obey the copy-block restriction. The restriction
1269	* is such that there are no copy-blocks referring across the border of 8x8
1270	* blocks. For the subsampled data the 8x8 limitation is also subsampled.
1271	*/
1272	#define AFBC_FORMAT_MOD_CBR (1ULL << 7)
1273
1274	/*
1275	* AFBC tiled layout
1276	*
1277	* The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all
1278	* superblocks inside a tile are stored together in memory. 8x8 tiles are used
1279	* for pixel formats up to and including 32 bpp while 4x4 tiles are used for
1280	* larger bpp formats. The order between the tiles is scan line.
1281	* When the tiled layout is used, the buffer size (in pixels) must be aligned
1282	* to the tile size.
1283	*/
1284	#define AFBC_FORMAT_MOD_TILED (1ULL << 8)
1285
1286	/*
1287	* AFBC solid color blocks
1288	*
1289	* Indicates that the buffer makes use of solid-color blocks, whereby bandwidth
1290	* can be reduced if a whole superblock is a single color.
1291	*/
1292	#define AFBC_FORMAT_MOD_SC (1ULL << 9)
1293
1294	/*
1295	* AFBC double-buffer
1296	*
1297	* Indicates that the buffer is allocated in a layout safe for front-buffer
1298	* rendering.
1299	*/
1300	#define AFBC_FORMAT_MOD_DB (1ULL << 10)
1301
1302	/*
1303	* AFBC buffer content hints
1304	*
1305	* Indicates that the buffer includes per-superblock content hints.
1306	*/
1307	#define AFBC_FORMAT_MOD_BCH (1ULL << 11)
1308
1309	/* AFBC uncompressed storage mode
1310	*
1311	* Indicates that the buffer is using AFBC uncompressed storage mode.
1312	* In this mode all superblock payloads in the buffer use the uncompressed
1313	* storage mode, which is usually only used for data which cannot be compressed.
1314	* The buffer layout is the same as for AFBC buffers without USM set, this only
1315	* affects the storage mode of the individual superblocks. Note that even a
1316	* buffer without USM set may use uncompressed storage mode for some or all
1317	* superblocks, USM just guarantees it for all.
1318	*/
1319	#define AFBC_FORMAT_MOD_USM (1ULL << 12)
1320
1321	/*
1322	* Arm Fixed-Rate Compression (AFRC) modifiers
1323	*
1324	* AFRC is a proprietary fixed rate image compression protocol and format,
1325	* designed to provide guaranteed bandwidth and memory footprint
1326	* reductions in graphics and media use-cases.
1327	*
1328	* AFRC buffers consist of one or more planes, with the same components
1329	* and meaning as an uncompressed buffer using the same pixel format.
1330	*
1331	* Within each plane, the pixel/luma/chroma values are grouped into
1332	* "coding unit" blocks which are individually compressed to a
1333	* fixed size (in bytes). All coding units within a given plane of a buffer
1334	* store the same number of values, and have the same compressed size.
1335	*
1336	* The coding unit size is configurable, allowing different rates of compression.
1337	*
1338	* The start of each AFRC buffer plane must be aligned to an alignment granule which
1339	* depends on the coding unit size.
1340	*
1341	* Coding Unit Size Plane Alignment
1342	* ---------------- ---------------
1343	* 16 bytes 1024 bytes
1344	* 24 bytes 512 bytes
1345	* 32 bytes 2048 bytes
1346	*
1347	* Coding units are grouped into paging tiles. AFRC buffer dimensions must be aligned
1348	* to a multiple of the paging tile dimensions.
1349	* The dimensions of each paging tile depend on whether the buffer is optimised for
1350	* scanline (SCAN layout) or rotated (ROT layout) access.
1351	*
1352	* Layout Paging Tile Width Paging Tile Height
1353	* ------ ----------------- ------------------
1354	* SCAN 16 coding units 4 coding units
1355	* ROT 8 coding units 8 coding units
1356	*
1357	* The dimensions of each coding unit depend on the number of components
1358	* in the compressed plane and whether the buffer is optimised for
1359	* scanline (SCAN layout) or rotated (ROT layout) access.
1360	*
1361	* Number of Components in Plane Layout Coding Unit Width Coding Unit Height
1362	* ----------------------------- --------- ----------------- ------------------
1363	* 1 SCAN 16 samples 4 samples
1364	* Example: 16x4 luma samples in a 'Y' plane
1365	* 16x4 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
1366	* ----------------------------- --------- ----------------- ------------------
1367	* 1 ROT 8 samples 8 samples
1368	* Example: 8x8 luma samples in a 'Y' plane
1369	* 8x8 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
1370	* ----------------------------- --------- ----------------- ------------------
1371	* 2 DONT CARE 8 samples 4 samples
1372	* Example: 8x4 chroma pairs in the 'UV' plane of a semi-planar YUV buffer
1373	* ----------------------------- --------- ----------------- ------------------
1374	* 3 DONT CARE 4 samples 4 samples
1375	* Example: 4x4 pixels in an RGB buffer without alpha
1376	* ----------------------------- --------- ----------------- ------------------
1377	* 4 DONT CARE 4 samples 4 samples
1378	* Example: 4x4 pixels in an RGB buffer with alpha
1379	*/
1380
1381	#define DRM_FORMAT_MOD_ARM_TYPE_AFRC 0x02
1382
1383	#define DRM_FORMAT_MOD_ARM_AFRC(__afrc_mode) \
1384	DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFRC, __afrc_mode)
1385
1386	/*
1387	* AFRC coding unit size modifier.
1388	*
1389	* Indicates the number of bytes used to store each compressed coding unit for
1390	* one or more planes in an AFRC encoded buffer. The coding unit size for chrominance
1391	* is the same for both Cb and Cr, which may be stored in separate planes.
1392	*
1393	* AFRC_FORMAT_MOD_CU_SIZE_P0 indicates the number of bytes used to store
1394	* each compressed coding unit in the first plane of the buffer. For RGBA buffers
1395	* this is the only plane, while for semi-planar and fully-planar YUV buffers,
1396	* this corresponds to the luma plane.
1397	*
1398	* AFRC_FORMAT_MOD_CU_SIZE_P12 indicates the number of bytes used to store
1399	* each compressed coding unit in the second and third planes in the buffer.
1400	* For semi-planar and fully-planar YUV buffers, this corresponds to the chroma plane(s).
1401	*
1402	* For single-plane buffers, AFRC_FORMAT_MOD_CU_SIZE_P0 must be specified
1403	* and AFRC_FORMAT_MOD_CU_SIZE_P12 must be zero.
1404	* For semi-planar and fully-planar buffers, both AFRC_FORMAT_MOD_CU_SIZE_P0 and
1405	* AFRC_FORMAT_MOD_CU_SIZE_P12 must be specified.
1406	*/
1407	#define AFRC_FORMAT_MOD_CU_SIZE_MASK 0xf
1408	#define AFRC_FORMAT_MOD_CU_SIZE_16 (1ULL)
1409	#define AFRC_FORMAT_MOD_CU_SIZE_24 (2ULL)
1410	#define AFRC_FORMAT_MOD_CU_SIZE_32 (3ULL)
1411
1412	#define AFRC_FORMAT_MOD_CU_SIZE_P0(__afrc_cu_size) (__afrc_cu_size)
1413	#define AFRC_FORMAT_MOD_CU_SIZE_P12(__afrc_cu_size) ((__afrc_cu_size) << 4)
1414
1415	/*
1416	* AFRC scanline memory layout.
1417	*
1418	* Indicates if the buffer uses the scanline-optimised layout
1419	* for an AFRC encoded buffer, otherwise, it uses the rotation-optimised layout.
1420	* The memory layout is the same for all planes.
1421	*/
1422	#define AFRC_FORMAT_MOD_LAYOUT_SCAN (1ULL << 8)
1423
1424	/*
1425	* Arm 16x16 Block U-Interleaved modifier
1426	*
1427	* This is used by Arm Mali Utgard and Midgard GPUs. It divides the image
1428	* into 16x16 pixel blocks. Blocks are stored linearly in order, but pixels
1429	* in the block are reordered.
1430	*/
1431	#define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED \
1432	DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL)
1433
1434	/*
1435	* ARM 64k interleaved modifier
1436	*
1437	* This is used by ARM Mali v10+ GPUs. With this modifier, the plane is divided
1438	* into 64k byte 1:1 or 2:1 -sided tiles. The 64k tiles are laid out linearly.
1439	* Each 64k tile is divided into blocks of 16x16 texel blocks, which are
1440	* themselves laid out linearly within a 64k tile. Then within each 16x16
1441	* block, texel blocks are laid out according to U order, similar to
1442	* 16X16_BLOCK_U_INTERLEAVED.
1443	*
1444	* Note that unlike 16X16_BLOCK_U_INTERLEAVED, the layout does not change
1445	* depending on whether a format is compressed or not.
1446	*/
1447	#define DRM_FORMAT_MOD_ARM_INTERLEAVED_64K \
1448	DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 2ULL)
1449
1450	/*
1451	* Allwinner tiled modifier
1452	*
1453	* This tiling mode is implemented by the VPU found on all Allwinner platforms,
1454	* codenamed sunxi. It is associated with a YUV format that uses either 2 or 3
1455	* planes.
1456	*
1457	* With this tiling, the luminance samples are disposed in tiles representing
1458	* 32x32 pixels and the chrominance samples in tiles representing 32x64 pixels.
1459	* The pixel order in each tile is linear and the tiles are disposed linearly,
1460	* both in row-major order.
1461	*/
1462	#define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1)
1463
1464	/*
1465	* Amlogic Video Framebuffer Compression modifiers
1466	*
1467	* Amlogic uses a proprietary lossless image compression protocol and format
1468	* for their hardware video codec accelerators, either video decoders or
1469	* video input encoders.
1470	*
1471	* It considerably reduces memory bandwidth while writing and reading
1472	* frames in memory.
1473	*
1474	* The underlying storage is considered to be 3 components, 8bit or 10-bit
1475	* per component YCbCr 420, single plane :
1476	* - DRM_FORMAT_YUV420_8BIT
1477	* - DRM_FORMAT_YUV420_10BIT
1478	*
1479	* The first 8 bits of the mode defines the layout, then the following 8 bits
1480	* defines the options changing the layout.
1481	*
1482	* Not all combinations are valid, and different SoCs may support different
1483	* combinations of layout and options.
1484	*/
1485	#define __fourcc_mod_amlogic_layout_mask 0xff
1486	#define __fourcc_mod_amlogic_options_shift 8
1487	#define __fourcc_mod_amlogic_options_mask 0xff
1488
1489	#define DRM_FORMAT_MOD_AMLOGIC_FBC(__layout, __options) \
1490	fourcc_mod_code(AMLOGIC, \
1491	((__layout) & __fourcc_mod_amlogic_layout_mask) \| \
1492	(((__options) & __fourcc_mod_amlogic_options_mask) \
1493	<< __fourcc_mod_amlogic_options_shift))
1494
1495	/* Amlogic FBC Layouts */
1496
1497	/*
1498	* Amlogic FBC Basic Layout
1499	*
1500	* The basic layout is composed of:
1501	* - a body content organized in 64x32 superblocks with 4096 bytes per
1502	* superblock in default mode.
1503	* - a 32 bytes per 128x64 header block
1504	*
1505	* This layout is transferrable between Amlogic SoCs supporting this modifier.
1506	*/
1507	#define AMLOGIC_FBC_LAYOUT_BASIC (1ULL)
1508
1509	/*
1510	* Amlogic FBC Scatter Memory layout
1511	*
1512	* Indicates the header contains IOMMU references to the compressed
1513	* frames content to optimize memory access and layout.
1514	*
1515	* In this mode, only the header memory address is needed, thus the
1516	* content memory organization is tied to the current producer
1517	* execution and cannot be saved/dumped neither transferrable between
1518	* Amlogic SoCs supporting this modifier.
1519	*
1520	* Due to the nature of the layout, these buffers are not expected to
1521	* be accessible by the user-space clients, but only accessible by the
1522	* hardware producers and consumers.
1523	*
1524	* The user-space clients should expect a failure while trying to mmap
1525	* the DMA-BUF handle returned by the producer.
1526	*/
1527	#define AMLOGIC_FBC_LAYOUT_SCATTER (2ULL)
1528
1529	/* Amlogic FBC Layout Options Bit Mask */
1530
1531	/*
1532	* Amlogic FBC Memory Saving mode
1533	*
1534	* Indicates the storage is packed when pixel size is multiple of word
1535	* boundaries, i.e. 8bit should be stored in this mode to save allocation
1536	* memory.
1537	*
1538	* This mode reduces body layout to 3072 bytes per 64x32 superblock with
1539	* the basic layout and 3200 bytes per 64x32 superblock combined with
1540	* the scatter layout.
1541	*/
1542	#define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0)
1543
1544	/* MediaTek modifiers
1545	* Bits Parameter Notes
1546	* ----- ------------------------ ---------------------------------------------
1547	* 7: 0 TILE LAYOUT Values are MTK_FMT_MOD_TILE_*
1548	* 15: 8 COMPRESSION Values are MTK_FMT_MOD_COMPRESS_*
1549	* 23:16 10 BIT LAYOUT Values are MTK_FMT_MOD_10BIT_LAYOUT_*
1550	*
1551	*/
1552
1553	#define DRM_FORMAT_MOD_MTK(__flags) fourcc_mod_code(MTK, __flags)
1554
1555	/*
1556	* MediaTek Tiled Modifier
1557	* The lowest 8 bits of the modifier is used to specify the tiling
1558	* layout. Only the 16L_32S tiling is used for now, but we define an
1559	* "untiled" version and leave room for future expansion.
1560	*/
1561	#define MTK_FMT_MOD_TILE_MASK 0xf
1562	#define MTK_FMT_MOD_TILE_NONE 0x0
1563	#define MTK_FMT_MOD_TILE_16L32S 0x1
1564
1565	/*
1566	* Bits 8-15 specify compression options
1567	*/
1568	#define MTK_FMT_MOD_COMPRESS_MASK (0xf << 8)
1569	#define MTK_FMT_MOD_COMPRESS_NONE (0x0 << 8)
1570	#define MTK_FMT_MOD_COMPRESS_V1 (0x1 << 8)
1571
1572	/*
1573	* Bits 16-23 specify how the bits of 10 bit formats are
1574	* stored out in memory
1575	*/
1576	#define MTK_FMT_MOD_10BIT_LAYOUT_MASK (0xf << 16)
1577	#define MTK_FMT_MOD_10BIT_LAYOUT_PACKED (0x0 << 16)
1578	#define MTK_FMT_MOD_10BIT_LAYOUT_LSBTILED (0x1 << 16)
1579	#define MTK_FMT_MOD_10BIT_LAYOUT_LSBRASTER (0x2 << 16)
1580
1581	/* alias for the most common tiling format */
1582	#define DRM_FORMAT_MOD_MTK_16L_32S_TILE DRM_FORMAT_MOD_MTK(MTK_FMT_MOD_TILE_16L32S)
1583
1584	/*
1585	* Apple GPU-tiled layouts.
1586	*
1587	* Apple GPUs support nonlinear tilings with optional lossless compression.
1588	*
1589	* GPU-tiled images are divided into 16KiB tiles:
1590	*
1591	* Bytes per pixel Tile size
1592	* --------------- ---------
1593	* 1 128x128
1594	* 2 128x64
1595	* 4 64x64
1596	* 8 64x32
1597	* 16 32x32
1598	*
1599	* Tiles are raster-order. Pixels within a tile are interleaved (Morton order).
1600	*
1601	* Compressed images pad the body to 128-bytes and are immediately followed by a
1602	* metadata section. The metadata section rounds the image dimensions to
1603	* powers-of-two and contains 8 bytes for each 16x16 compression subtile.
1604	* Subtiles are interleaved (Morton order).
1605	*
1606	* All images are 128-byte aligned.
1607	*
1608	* These layouts fundamentally do not have meaningful strides. No matter how we
1609	* specify strides for these layouts, userspace unaware of Apple image layouts
1610	* will be unable to use correctly the specified stride for any purpose.
1611	* Userspace aware of the image layouts do not use strides. The most "correct"
1612	* convention would be setting the image stride to 0. Unfortunately, some
1613	* software assumes the stride is at least (width * bytes per pixel). We
1614	* therefore require that stride equals (width * bytes per pixel). Since the
1615	* stride is arbitrary here, we pick the simplest convention.
1616	*
1617	* Although containing two sections, compressed image layouts are treated in
1618	* software as a single plane. This is modelled after AFBC, a similar
1619	* scheme. Attempting to separate the sections to be "explicit" in DRM would
1620	* only generate more confusion, as software does not treat the image this way.
1621	*
1622	* For detailed information on the hardware image layouts, see
1623	* https://docs.mesa3d.org/drivers/asahi.html#image-layouts
1624	*/
1625	#define DRM_FORMAT_MOD_APPLE_GPU_TILED fourcc_mod_code(APPLE, 1)
1626	#define DRM_FORMAT_MOD_APPLE_GPU_TILED_COMPRESSED fourcc_mod_code(APPLE, 2)
1627
1628	/*
1629	* AMD modifiers
1630	*
1631	* Memory layout:
1632	*
1633	* without DCC:
1634	* - main surface
1635	*
1636	* with DCC & without DCC_RETILE:
1637	* - main surface in plane 0
1638	* - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set)
1639	*
1640	* with DCC & DCC_RETILE:
1641	* - main surface in plane 0
1642	* - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned)
1643	* - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned)
1644	*
1645	* For multi-plane formats the above surfaces get merged into one plane for
1646	* each format plane, based on the required alignment only.
1647	*
1648	* Bits Parameter Notes
1649	* ----- ------------------------ ---------------------------------------------
1650	*
1651	* 7:0 TILE_VERSION Values are AMD_FMT_MOD_TILE_VER_*
1652	* 12:8 TILE Values are AMD_FMT_MOD_TILE_<version>_*
1653	* 13 DCC
1654	* 14 DCC_RETILE
1655	* 15 DCC_PIPE_ALIGN
1656	* 16 DCC_INDEPENDENT_64B
1657	* 17 DCC_INDEPENDENT_128B
1658	* 19:18 DCC_MAX_COMPRESSED_BLOCK Values are AMD_FMT_MOD_DCC_BLOCK_*
1659	* 20 DCC_CONSTANT_ENCODE
1660	* 23:21 PIPE_XOR_BITS Only for some chips
1661	* 26:24 BANK_XOR_BITS Only for some chips
1662	* 29:27 PACKERS Only for some chips
1663	* 32:30 RB Only for some chips
1664	* 35:33 PIPE Only for some chips
1665	* 55:36 - Reserved for future use, must be zero
1666	*/
1667	#define AMD_FMT_MOD fourcc_mod_code(AMD, 0)
1668
1669	#define IS_AMD_FMT_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_AMD)
1670
1671	/* Reserve 0 for GFX8 and older */
1672	#define AMD_FMT_MOD_TILE_VER_GFX9 1
1673	#define AMD_FMT_MOD_TILE_VER_GFX10 2
1674	#define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3
1675	#define AMD_FMT_MOD_TILE_VER_GFX11 4
1676	#define AMD_FMT_MOD_TILE_VER_GFX12 5
1677
1678	/*
1679	* 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical
1680	* version.
1681	*/
1682	#define AMD_FMT_MOD_TILE_GFX9_64K_S 9
1683
1684	/*
1685	* 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has
1686	* GFX9 as canonical version.
1687	*
1688	* 64K_D_2D on GFX12 is identical to 64K_D on GFX11.
1689	*/
1690	#define AMD_FMT_MOD_TILE_GFX9_64K_D 10
1691	#define AMD_FMT_MOD_TILE_GFX9_4K_D_X 22
1692	#define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25
1693	#define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26
1694	#define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27
1695	#define AMD_FMT_MOD_TILE_GFX11_256K_R_X 31
1696
1697	/* Gfx12 swizzle modes:
1698	* 0 - LINEAR
1699	* 1 - 256B_2D - 2D block dimensions
1700	* 2 - 4KB_2D
1701	* 3 - 64KB_2D
1702	* 4 - 256KB_2D
1703	* 5 - 4KB_3D - 3D block dimensions
1704	* 6 - 64KB_3D
1705	* 7 - 256KB_3D
1706	*/
1707	#define AMD_FMT_MOD_TILE_GFX12_256B_2D 1
1708	#define AMD_FMT_MOD_TILE_GFX12_4K_2D 2
1709	#define AMD_FMT_MOD_TILE_GFX12_64K_2D 3
1710	#define AMD_FMT_MOD_TILE_GFX12_256K_2D 4
1711
1712	#define AMD_FMT_MOD_DCC_BLOCK_64B 0
1713	#define AMD_FMT_MOD_DCC_BLOCK_128B 1
1714	#define AMD_FMT_MOD_DCC_BLOCK_256B 2
1715
1716	#define AMD_FMT_MOD_TILE_VERSION_SHIFT 0
1717	#define AMD_FMT_MOD_TILE_VERSION_MASK 0xFF
1718	#define AMD_FMT_MOD_TILE_SHIFT 8
1719	#define AMD_FMT_MOD_TILE_MASK 0x1F
1720
1721	/* Whether DCC compression is enabled. */
1722	#define AMD_FMT_MOD_DCC_SHIFT 13
1723	#define AMD_FMT_MOD_DCC_MASK 0x1
1724
1725	/*
1726	* Whether to include two DCC surfaces, one which is rb & pipe aligned, and
1727	* one which is not-aligned.
1728	*/
1729	#define AMD_FMT_MOD_DCC_RETILE_SHIFT 14
1730	#define AMD_FMT_MOD_DCC_RETILE_MASK 0x1
1731
1732	/* Only set if DCC_RETILE = false */
1733	#define AMD_FMT_MOD_DCC_PIPE_ALIGN_SHIFT 15
1734	#define AMD_FMT_MOD_DCC_PIPE_ALIGN_MASK 0x1
1735
1736	#define AMD_FMT_MOD_DCC_INDEPENDENT_64B_SHIFT 16
1737	#define AMD_FMT_MOD_DCC_INDEPENDENT_64B_MASK 0x1
1738	#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17
1739	#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1
1740	#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18
1741	#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3
1742
1743	/*
1744	* DCC supports embedding some clear colors directly in the DCC surface.
1745	* However, on older GPUs the rendering HW ignores the embedded clear color
1746	* and prefers the driver provided color. This necessitates doing a fastclear
1747	* eliminate operation before a process transfers control.
1748	*
1749	* If this bit is set that means the fastclear eliminate is not needed for these
1750	* embeddable colors.
1751	*/
1752	#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 20
1753	#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_MASK 0x1
1754
1755	/*
1756	* The below fields are for accounting for per GPU differences. These are only
1757	* relevant for GFX9 and later and if the tile field is *_X/_T.
1758	*
1759	* PIPE_XOR_BITS = always needed
1760	* BANK_XOR_BITS = only for TILE_VER_GFX9
1761	* PACKERS = only for TILE_VER_GFX10_RBPLUS
1762	* RB = only for TILE_VER_GFX9 & DCC
1763	* PIPE = only for TILE_VER_GFX9 & DCC & (DCC_RETILE \| DCC_PIPE_ALIGN)
1764	*/
1765	#define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 21
1766	#define AMD_FMT_MOD_PIPE_XOR_BITS_MASK 0x7
1767	#define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24
1768	#define AMD_FMT_MOD_BANK_XOR_BITS_MASK 0x7
1769	#define AMD_FMT_MOD_PACKERS_SHIFT 27
1770	#define AMD_FMT_MOD_PACKERS_MASK 0x7
1771	#define AMD_FMT_MOD_RB_SHIFT 30
1772	#define AMD_FMT_MOD_RB_MASK 0x7
1773	#define AMD_FMT_MOD_PIPE_SHIFT 33
1774	#define AMD_FMT_MOD_PIPE_MASK 0x7
1775
1776	#define AMD_FMT_MOD_SET(field, value) \
1777	((uint64_t)(value) << AMD_FMT_MOD_##field##_SHIFT)
1778	#define AMD_FMT_MOD_GET(field, value) \
1779	(((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK)
1780	#define AMD_FMT_MOD_CLEAR(field) \
1781	(~((uint64_t)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT))
1782
1783	#if defined(__cplusplus)
1784	}
1785	#endif
1786
1787	#endif /* DRM_FOURCC_H */