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1 /*
2 * Virtio GPU Device
3 *
4 * Copyright Red Hat, Inc. 2013-2014
5 *
6 * Authors:
7 * Dave Airlie <airlied@redhat.com>
8 * Gerd Hoffmann <kraxel@redhat.com>
9 *
10 * This header is BSD licensed so anyone can use the definitions
11 * to implement compatible drivers/servers:
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 * 3. Neither the name of IBM nor the names of its contributors
22 * may be used to endorse or promote products derived from this software
23 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
27 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL IBM OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
31 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
32 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
34 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * SUCH DAMAGE.
36 */
37
38 #ifndef VIRTIO_GPU_HW_H
39 #define VIRTIO_GPU_HW_H
40
41 #include "standard-headers/linux/types.h"
42
43 /*
44 * VIRTIO_GPU_CMD_CTX_*
45 * VIRTIO_GPU_CMD_*_3D
46 */
47 #define VIRTIO_GPU_F_VIRGL 0
48
49 /*
50 * VIRTIO_GPU_CMD_GET_EDID
51 */
52 #define VIRTIO_GPU_F_EDID 1
53 /*
54 * VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID
55 */
56 #define VIRTIO_GPU_F_RESOURCE_UUID 2
57
58 /*
59 * VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB
60 */
61 #define VIRTIO_GPU_F_RESOURCE_BLOB 3
62 /*
63 * VIRTIO_GPU_CMD_CREATE_CONTEXT with
64 * context_init and multiple timelines
65 */
66 #define VIRTIO_GPU_F_CONTEXT_INIT 4
67 /*
68 * The device provides a valid blob_alignment
69 * field in its configuration and both
70 * VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB and
71 * VIRTIO_GPU_CMD_RESOURCE_MAP_BLOB requests
72 * must be aligned to that value.
73 */
74 #define VIRTIO_GPU_F_BLOB_ALIGNMENT 5
75
76 enum virtio_gpu_ctrl_type {
77 VIRTIO_GPU_UNDEFINED = 0,
78
79 /* 2d commands */
80 VIRTIO_GPU_CMD_GET_DISPLAY_INFO = 0x0100,
81 VIRTIO_GPU_CMD_RESOURCE_CREATE_2D,
82 VIRTIO_GPU_CMD_RESOURCE_UNREF,
83 VIRTIO_GPU_CMD_SET_SCANOUT,
84 VIRTIO_GPU_CMD_RESOURCE_FLUSH,
85 VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D,
86 VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING,
87 VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING,
88 VIRTIO_GPU_CMD_GET_CAPSET_INFO,
89 VIRTIO_GPU_CMD_GET_CAPSET,
90 VIRTIO_GPU_CMD_GET_EDID,
91 VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID,
92 VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB,
93 VIRTIO_GPU_CMD_SET_SCANOUT_BLOB,
94
95 /* 3d commands */
96 VIRTIO_GPU_CMD_CTX_CREATE = 0x0200,
97 VIRTIO_GPU_CMD_CTX_DESTROY,
98 VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE,
99 VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE,
100 VIRTIO_GPU_CMD_RESOURCE_CREATE_3D,
101 VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D,
102 VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D,
103 VIRTIO_GPU_CMD_SUBMIT_3D,
104 VIRTIO_GPU_CMD_RESOURCE_MAP_BLOB,
105 VIRTIO_GPU_CMD_RESOURCE_UNMAP_BLOB,
106
107 /* cursor commands */
108 VIRTIO_GPU_CMD_UPDATE_CURSOR = 0x0300,
109 VIRTIO_GPU_CMD_MOVE_CURSOR,
110
111 /* success responses */
112 VIRTIO_GPU_RESP_OK_NODATA = 0x1100,
113 VIRTIO_GPU_RESP_OK_DISPLAY_INFO,
114 VIRTIO_GPU_RESP_OK_CAPSET_INFO,
115 VIRTIO_GPU_RESP_OK_CAPSET,
116 VIRTIO_GPU_RESP_OK_EDID,
117 VIRTIO_GPU_RESP_OK_RESOURCE_UUID,
118 VIRTIO_GPU_RESP_OK_MAP_INFO,
119
120 /* error responses */
121 VIRTIO_GPU_RESP_ERR_UNSPEC = 0x1200,
122 VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY,
123 VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID,
124 VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID,
125 VIRTIO_GPU_RESP_ERR_INVALID_CONTEXT_ID,
126 VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER,
127 };
128
129 enum virtio_gpu_shm_id {
130 VIRTIO_GPU_SHM_ID_UNDEFINED = 0,
131 /*
132 * VIRTIO_GPU_CMD_RESOURCE_MAP_BLOB
133 * VIRTIO_GPU_CMD_RESOURCE_UNMAP_BLOB
134 */
135 VIRTIO_GPU_SHM_ID_HOST_VISIBLE = 1
136 };
137
138 #define VIRTIO_GPU_FLAG_FENCE (1 << 0)
139 /*
140 * If the following flag is set, then ring_idx contains the index
141 * of the command ring that needs to used when creating the fence
142 */
143 #define VIRTIO_GPU_FLAG_INFO_RING_IDX (1 << 1)
144
145 struct virtio_gpu_ctrl_hdr {
146 uint32_t type;
147 uint32_t flags;
148 uint64_t fence_id;
149 uint32_t ctx_id;
150 uint8_t ring_idx;
151 uint8_t padding[3];
152 };
153
154 /* data passed in the cursor vq */
155
156 struct virtio_gpu_cursor_pos {
157 uint32_t scanout_id;
158 uint32_t x;
159 uint32_t y;
160 uint32_t padding;
161 };
162
163 /* VIRTIO_GPU_CMD_UPDATE_CURSOR, VIRTIO_GPU_CMD_MOVE_CURSOR */
164 struct virtio_gpu_update_cursor {
165 struct virtio_gpu_ctrl_hdr hdr;
166 struct virtio_gpu_cursor_pos pos; /* update & move */
167 uint32_t resource_id; /* update only */
168 uint32_t hot_x; /* update only */
169 uint32_t hot_y; /* update only */
170 uint32_t padding;
171 };
172
173 /* data passed in the control vq, 2d related */
174
175 struct virtio_gpu_rect {
176 uint32_t x;
177 uint32_t y;
178 uint32_t width;
179 uint32_t height;
180 };
181
182 /* VIRTIO_GPU_CMD_RESOURCE_UNREF */
183 struct virtio_gpu_resource_unref {
184 struct virtio_gpu_ctrl_hdr hdr;
185 uint32_t resource_id;
186 uint32_t padding;
187 };
188
189 /* VIRTIO_GPU_CMD_RESOURCE_CREATE_2D: create a 2d resource with a format */
190 struct virtio_gpu_resource_create_2d {
191 struct virtio_gpu_ctrl_hdr hdr;
192 uint32_t resource_id;
193 uint32_t format;
194 uint32_t width;
195 uint32_t height;
196 };
197
198 /* VIRTIO_GPU_CMD_SET_SCANOUT */
199 struct virtio_gpu_set_scanout {
200 struct virtio_gpu_ctrl_hdr hdr;
201 struct virtio_gpu_rect r;
202 uint32_t scanout_id;
203 uint32_t resource_id;
204 };
205
206 /* VIRTIO_GPU_CMD_RESOURCE_FLUSH */
207 struct virtio_gpu_resource_flush {
208 struct virtio_gpu_ctrl_hdr hdr;
209 struct virtio_gpu_rect r;
210 uint32_t resource_id;
211 uint32_t padding;
212 };
213
214 /* VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D: simple transfer to_host */
215 struct virtio_gpu_transfer_to_host_2d {
216 struct virtio_gpu_ctrl_hdr hdr;
217 struct virtio_gpu_rect r;
218 uint64_t offset;
219 uint32_t resource_id;
220 uint32_t padding;
221 };
222
223 struct virtio_gpu_mem_entry {
224 uint64_t addr;
225 uint32_t length;
226 uint32_t padding;
227 };
228
229 /* VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING */
230 struct virtio_gpu_resource_attach_backing {
231 struct virtio_gpu_ctrl_hdr hdr;
232 uint32_t resource_id;
233 uint32_t nr_entries;
234 };
235
236 /* VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING */
237 struct virtio_gpu_resource_detach_backing {
238 struct virtio_gpu_ctrl_hdr hdr;
239 uint32_t resource_id;
240 uint32_t padding;
241 };
242
243 /* VIRTIO_GPU_RESP_OK_DISPLAY_INFO */
244 #define VIRTIO_GPU_MAX_SCANOUTS 16
245 struct virtio_gpu_resp_display_info {
246 struct virtio_gpu_ctrl_hdr hdr;
247 struct virtio_gpu_display_one {
248 struct virtio_gpu_rect r;
249 uint32_t enabled;
250 uint32_t flags;
251 } pmodes[VIRTIO_GPU_MAX_SCANOUTS];
252 };
253
254 /* data passed in the control vq, 3d related */
255
256 struct virtio_gpu_box {
257 uint32_t x, y, z;
258 uint32_t w, h, d;
259 };
260
261 /* VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D, VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D */
262 struct virtio_gpu_transfer_host_3d {
263 struct virtio_gpu_ctrl_hdr hdr;
264 struct virtio_gpu_box box;
265 uint64_t offset;
266 uint32_t resource_id;
267 uint32_t level;
268 uint32_t stride;
269 uint32_t layer_stride;
270 };
271
272 /* VIRTIO_GPU_CMD_RESOURCE_CREATE_3D */
273 #define VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP (1 << 0)
274 struct virtio_gpu_resource_create_3d {
275 struct virtio_gpu_ctrl_hdr hdr;
276 uint32_t resource_id;
277 uint32_t target;
278 uint32_t format;
279 uint32_t bind;
280 uint32_t width;
281 uint32_t height;
282 uint32_t depth;
283 uint32_t array_size;
284 uint32_t last_level;
285 uint32_t nr_samples;
286 uint32_t flags;
287 uint32_t padding;
288 };
289
290 /* VIRTIO_GPU_CMD_CTX_CREATE */
291 #define VIRTIO_GPU_CONTEXT_INIT_CAPSET_ID_MASK 0x000000ff
292 struct virtio_gpu_ctx_create {
293 struct virtio_gpu_ctrl_hdr hdr;
294 uint32_t nlen;
295 uint32_t context_init;
296 char debug_name[64];
297 };
298
299 /* VIRTIO_GPU_CMD_CTX_DESTROY */
300 struct virtio_gpu_ctx_destroy {
301 struct virtio_gpu_ctrl_hdr hdr;
302 };
303
304 /* VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE, VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE */
305 struct virtio_gpu_ctx_resource {
306 struct virtio_gpu_ctrl_hdr hdr;
307 uint32_t resource_id;
308 uint32_t padding;
309 };
310
311 /* VIRTIO_GPU_CMD_SUBMIT_3D */
312 struct virtio_gpu_cmd_submit {
313 struct virtio_gpu_ctrl_hdr hdr;
314 uint32_t size;
315 uint32_t padding;
316 };
317
318 #define VIRTIO_GPU_CAPSET_VIRGL 1
319 #define VIRTIO_GPU_CAPSET_VIRGL2 2
320 #define VIRTIO_GPU_CAPSET_GFXSTREAM_VULKAN 3
321 #define VIRTIO_GPU_CAPSET_VENUS 4
322 #define VIRTIO_GPU_CAPSET_CROSS_DOMAIN 5
323 #define VIRTIO_GPU_CAPSET_DRM 6
324
325 /* VIRTIO_GPU_CMD_GET_CAPSET_INFO */
326 struct virtio_gpu_get_capset_info {
327 struct virtio_gpu_ctrl_hdr hdr;
328 uint32_t capset_index;
329 uint32_t padding;
330 };
331
332 /* VIRTIO_GPU_RESP_OK_CAPSET_INFO */
333 struct virtio_gpu_resp_capset_info {
334 struct virtio_gpu_ctrl_hdr hdr;
335 uint32_t capset_id;
336 uint32_t capset_max_version;
337 uint32_t capset_max_size;
338 uint32_t padding;
339 };
340
341 /* VIRTIO_GPU_CMD_GET_CAPSET */
342 struct virtio_gpu_get_capset {
343 struct virtio_gpu_ctrl_hdr hdr;
344 uint32_t capset_id;
345 uint32_t capset_version;
346 };
347
348 /* VIRTIO_GPU_RESP_OK_CAPSET */
349 struct virtio_gpu_resp_capset {
350 struct virtio_gpu_ctrl_hdr hdr;
351 uint8_t capset_data[];
352 };
353
354 /* VIRTIO_GPU_CMD_GET_EDID */
355 struct virtio_gpu_cmd_get_edid {
356 struct virtio_gpu_ctrl_hdr hdr;
357 uint32_t scanout;
358 uint32_t padding;
359 };
360
361 /* VIRTIO_GPU_RESP_OK_EDID */
362 struct virtio_gpu_resp_edid {
363 struct virtio_gpu_ctrl_hdr hdr;
364 uint32_t size;
365 uint32_t padding;
366 uint8_t edid[1024];
367 };
368
369 #define VIRTIO_GPU_EVENT_DISPLAY (1 << 0)
370
371 struct virtio_gpu_config {
372 uint32_t events_read;
373 uint32_t events_clear;
374 uint32_t num_scanouts;
375 uint32_t num_capsets;
376 uint32_t blob_alignment;
377 };
378
379 /* simple formats for fbcon/X use */
380 enum virtio_gpu_formats {
381 VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM = 1,
382 VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM = 2,
383 VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM = 3,
384 VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM = 4,
385
386 VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM = 67,
387 VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM = 68,
388
389 VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM = 121,
390 VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM = 134,
391 };
392
393 /* VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID */
394 struct virtio_gpu_resource_assign_uuid {
395 struct virtio_gpu_ctrl_hdr hdr;
396 uint32_t resource_id;
397 uint32_t padding;
398 };
399
400 /* VIRTIO_GPU_RESP_OK_RESOURCE_UUID */
401 struct virtio_gpu_resp_resource_uuid {
402 struct virtio_gpu_ctrl_hdr hdr;
403 uint8_t uuid[16];
404 };
405
406 /* VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB */
407 struct virtio_gpu_resource_create_blob {
408 struct virtio_gpu_ctrl_hdr hdr;
409 uint32_t resource_id;
410 #define VIRTIO_GPU_BLOB_MEM_GUEST 0x0001
411 #define VIRTIO_GPU_BLOB_MEM_HOST3D 0x0002
412 #define VIRTIO_GPU_BLOB_MEM_HOST3D_GUEST 0x0003
413
414 #define VIRTIO_GPU_BLOB_FLAG_USE_MAPPABLE 0x0001
415 #define VIRTIO_GPU_BLOB_FLAG_USE_SHAREABLE 0x0002
416 #define VIRTIO_GPU_BLOB_FLAG_USE_CROSS_DEVICE 0x0004
417 /* zero is invalid blob mem */
418 uint32_t blob_mem;
419 uint32_t blob_flags;
420 uint32_t nr_entries;
421 uint64_t blob_id;
422 uint64_t size;
423 /*
424 * sizeof(nr_entries * virtio_gpu_mem_entry) bytes follow
425 */
426 };
427
428 /* VIRTIO_GPU_CMD_SET_SCANOUT_BLOB */
429 struct virtio_gpu_set_scanout_blob {
430 struct virtio_gpu_ctrl_hdr hdr;
431 struct virtio_gpu_rect r;
432 uint32_t scanout_id;
433 uint32_t resource_id;
434 uint32_t width;
435 uint32_t height;
436 uint32_t format;
437 uint32_t padding;
438 uint32_t strides[4];
439 uint32_t offsets[4];
440 };
441
442 /* VIRTIO_GPU_CMD_RESOURCE_MAP_BLOB */
443 struct virtio_gpu_resource_map_blob {
444 struct virtio_gpu_ctrl_hdr hdr;
445 uint32_t resource_id;
446 uint32_t padding;
447 uint64_t offset;
448 };
449
450 /* VIRTIO_GPU_RESP_OK_MAP_INFO */
451 #define VIRTIO_GPU_MAP_CACHE_MASK 0x0f
452 #define VIRTIO_GPU_MAP_CACHE_NONE 0x00
453 #define VIRTIO_GPU_MAP_CACHE_CACHED 0x01
454 #define VIRTIO_GPU_MAP_CACHE_UNCACHED 0x02
455 #define VIRTIO_GPU_MAP_CACHE_WC 0x03
456 struct virtio_gpu_resp_map_info {
457 struct virtio_gpu_ctrl_hdr hdr;
458 uint32_t map_info;
459 uint32_t padding;
460 };
461
462 /* VIRTIO_GPU_CMD_RESOURCE_UNMAP_BLOB */
463 struct virtio_gpu_resource_unmap_blob {
464 struct virtio_gpu_ctrl_hdr hdr;
465 uint32_t resource_id;
466 uint32_t padding;
467 };
468
469 #endif