| 1 | /* |
| 2 | * Generic vector operation descriptor |
| 3 | * |
| 4 | * Copyright (c) 2018 Linaro |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2.1 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #ifndef TCG_TCG_GVEC_DESC_H |
| 21 | #define TCG_TCG_GVEC_DESC_H |
| 22 | |
| 23 | #include "qemu/bitops.h" |
| 24 | |
| 25 | /* |
| 26 | * This configuration allows MAXSZ to represent 2048 bytes, and |
| 27 | * OPRSZ to match MAXSZ, or represent the smaller values 8, 16, or 32. |
| 28 | * |
| 29 | * Encode this with: |
| 30 | * 0, 1, 3 -> 8, 16, 32 |
| 31 | * 2 -> maxsz |
| 32 | * |
| 33 | * This steals the input that would otherwise map to 24 to match maxsz. |
| 34 | */ |
| 35 | #define SIMD_MAXSZ_SHIFT 0 |
| 36 | #define SIMD_MAXSZ_BITS 8 |
| 37 | |
| 38 | #define SIMD_OPRSZ_SHIFT (SIMD_MAXSZ_SHIFT + SIMD_MAXSZ_BITS) |
| 39 | #define SIMD_OPRSZ_BITS 2 |
| 40 | |
| 41 | #define SIMD_DATA_SHIFT (SIMD_OPRSZ_SHIFT + SIMD_OPRSZ_BITS) |
| 42 | #define SIMD_DATA_BITS (32 - SIMD_DATA_SHIFT) |
| 43 | |
| 44 | /* Create a descriptor from components. */ |
| 45 | uint32_t simd_desc(uint32_t oprsz, uint32_t maxsz, int32_t data); |
| 46 | |
| 47 | /* Extract the max vector size from a descriptor. */ |
| 48 | static inline intptr_t simd_maxsz(uint32_t desc) |
| 49 | { |
| 50 | return extract32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS) * 8 + 8; |
| 51 | } |
| 52 | |
| 53 | /* Extract the operation size from a descriptor. */ |
| 54 | static inline intptr_t simd_oprsz(uint32_t desc) |
| 55 | { |
| 56 | uint32_t f = extract32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS); |
| 57 | intptr_t o = f * 8 + 8; |
| 58 | intptr_t m = simd_maxsz(desc); |
| 59 | return f == 2 ? m : o; |
| 60 | } |
| 61 | |
| 62 | /* Extract the operation-specific data from a descriptor. */ |
| 63 | static inline int32_t simd_data(uint32_t desc) |
| 64 | { |
| 65 | return sextract32(desc, SIMD_DATA_SHIFT, SIMD_DATA_BITS); |
| 66 | } |
| 67 | |
| 68 | #endif |