| 1 | /* SPDX-License-Identifier: MIT */ |
| 2 | /* |
| 3 | * Target dependent opcode generation functions. |
| 4 | * |
| 5 | * Copyright (c) 2008 Fabrice Bellard |
| 6 | */ |
| 7 | |
| 8 | #ifndef TCG_TCG_OP_H |
| 9 | #define TCG_TCG_OP_H |
| 10 | |
| 11 | #include "tcg/tcg-op-common.h" |
| 12 | #include "tcg/insn-start-words.h" |
| 13 | #include "exec/target_long.h" |
| 14 | |
| 15 | #ifndef TARGET_LONG_BITS |
| 16 | #error must include QEMU headers |
| 17 | #endif |
| 18 | |
| 19 | #define TCG_ADDRESS_BITS TARGET_LONG_BITS |
| 20 | #include "tcg/tcg-op-mem.h" |
| 21 | |
| 22 | #if TARGET_LONG_BITS == 32 |
| 23 | # define TCG_TYPE_TL TCG_TYPE_I32 |
| 24 | #elif TARGET_LONG_BITS == 64 |
| 25 | # define TCG_TYPE_TL TCG_TYPE_I64 |
| 26 | #else |
| 27 | # error |
| 28 | #endif |
| 29 | |
| 30 | #if INSN_START_WORDS != 3 |
| 31 | # error Mismatch with insn-start-words.h |
| 32 | #endif |
| 33 | |
| 34 | #if TARGET_LONG_BITS == 32 |
| 35 | typedef TCGv_i32 TCGv; |
| 36 | #define tcg_temp_new() tcg_temp_new_i32() |
| 37 | #define tcg_global_mem_new tcg_global_mem_new_i32 |
| 38 | #define tcgv_tl_temp tcgv_i32_temp |
| 39 | #define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i32 |
| 40 | #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i32 |
| 41 | #elif TARGET_LONG_BITS == 64 |
| 42 | typedef TCGv_i64 TCGv; |
| 43 | #define tcg_temp_new() tcg_temp_new_i64() |
| 44 | #define tcg_global_mem_new tcg_global_mem_new_i64 |
| 45 | #define tcgv_tl_temp tcgv_i64_temp |
| 46 | #define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i64 |
| 47 | #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i64 |
| 48 | #else |
| 49 | #error Unhandled TARGET_LONG_BITS value |
| 50 | #endif |
| 51 | |
| 52 | #if TARGET_LONG_BITS == 64 |
| 53 | #define tcg_gen_movi_tl tcg_gen_movi_i64 |
| 54 | #define tcg_gen_mov_tl tcg_gen_mov_i64 |
| 55 | #define tcg_gen_ld8u_tl tcg_gen_ld8u_i64 |
| 56 | #define tcg_gen_ld8s_tl tcg_gen_ld8s_i64 |
| 57 | #define tcg_gen_ld16u_tl tcg_gen_ld16u_i64 |
| 58 | #define tcg_gen_ld16s_tl tcg_gen_ld16s_i64 |
| 59 | #define tcg_gen_ld32u_tl tcg_gen_ld32u_i64 |
| 60 | #define tcg_gen_ld32s_tl tcg_gen_ld32s_i64 |
| 61 | #define tcg_gen_ld_tl tcg_gen_ld_i64 |
| 62 | #define tcg_gen_st8_tl tcg_gen_st8_i64 |
| 63 | #define tcg_gen_st16_tl tcg_gen_st16_i64 |
| 64 | #define tcg_gen_st32_tl tcg_gen_st32_i64 |
| 65 | #define tcg_gen_st_tl tcg_gen_st_i64 |
| 66 | #define tcg_gen_add_tl tcg_gen_add_i64 |
| 67 | #define tcg_gen_addi_tl tcg_gen_addi_i64 |
| 68 | #define tcg_gen_sub_tl tcg_gen_sub_i64 |
| 69 | #define tcg_gen_neg_tl tcg_gen_neg_i64 |
| 70 | #define tcg_gen_abs_tl tcg_gen_abs_i64 |
| 71 | #define tcg_gen_subfi_tl tcg_gen_subfi_i64 |
| 72 | #define tcg_gen_subi_tl tcg_gen_subi_i64 |
| 73 | #define tcg_gen_and_tl tcg_gen_and_i64 |
| 74 | #define tcg_gen_andi_tl tcg_gen_andi_i64 |
| 75 | #define tcg_gen_or_tl tcg_gen_or_i64 |
| 76 | #define tcg_gen_ori_tl tcg_gen_ori_i64 |
| 77 | #define tcg_gen_xor_tl tcg_gen_xor_i64 |
| 78 | #define tcg_gen_xori_tl tcg_gen_xori_i64 |
| 79 | #define tcg_gen_not_tl tcg_gen_not_i64 |
| 80 | #define tcg_gen_shl_tl tcg_gen_shl_i64 |
| 81 | #define tcg_gen_shli_tl tcg_gen_shli_i64 |
| 82 | #define tcg_gen_shr_tl tcg_gen_shr_i64 |
| 83 | #define tcg_gen_shri_tl tcg_gen_shri_i64 |
| 84 | #define tcg_gen_sar_tl tcg_gen_sar_i64 |
| 85 | #define tcg_gen_sari_tl tcg_gen_sari_i64 |
| 86 | #define tcg_gen_brcond_tl tcg_gen_brcond_i64 |
| 87 | #define tcg_gen_brcondi_tl tcg_gen_brcondi_i64 |
| 88 | #define tcg_gen_setcond_tl tcg_gen_setcond_i64 |
| 89 | #define tcg_gen_setcondi_tl tcg_gen_setcondi_i64 |
| 90 | #define tcg_gen_negsetcond_tl tcg_gen_negsetcond_i64 |
| 91 | #define tcg_gen_negsetcondi_tl tcg_gen_negsetcondi_i64 |
| 92 | #define tcg_gen_mul_tl tcg_gen_mul_i64 |
| 93 | #define tcg_gen_muli_tl tcg_gen_muli_i64 |
| 94 | #define tcg_gen_div_tl tcg_gen_div_i64 |
| 95 | #define tcg_gen_rem_tl tcg_gen_rem_i64 |
| 96 | #define tcg_gen_divu_tl tcg_gen_divu_i64 |
| 97 | #define tcg_gen_remu_tl tcg_gen_remu_i64 |
| 98 | #define tcg_gen_discard_tl tcg_gen_discard_i64 |
| 99 | #define tcg_gen_trunc_tl_i32 tcg_gen_extrl_i64_i32 |
| 100 | #define tcg_gen_trunc_i64_tl tcg_gen_mov_i64 |
| 101 | #define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64 |
| 102 | #define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64 |
| 103 | #define tcg_gen_extu_tl_i64 tcg_gen_mov_i64 |
| 104 | #define tcg_gen_ext_tl_i64 tcg_gen_mov_i64 |
| 105 | #define tcg_gen_ext8u_tl tcg_gen_ext8u_i64 |
| 106 | #define tcg_gen_ext8s_tl tcg_gen_ext8s_i64 |
| 107 | #define tcg_gen_ext16u_tl tcg_gen_ext16u_i64 |
| 108 | #define tcg_gen_ext16s_tl tcg_gen_ext16s_i64 |
| 109 | #define tcg_gen_ext32u_tl tcg_gen_ext32u_i64 |
| 110 | #define tcg_gen_ext32s_tl tcg_gen_ext32s_i64 |
| 111 | #define tcg_gen_ext_tl tcg_gen_ext_i64 |
| 112 | #define tcg_gen_bswap16_tl tcg_gen_bswap16_i64 |
| 113 | #define tcg_gen_bswap32_tl tcg_gen_bswap32_i64 |
| 114 | #define tcg_gen_bswap64_tl tcg_gen_bswap64_i64 |
| 115 | #define tcg_gen_bswap_tl tcg_gen_bswap64_i64 |
| 116 | #define tcg_gen_hswap_tl tcg_gen_hswap_i64 |
| 117 | #define tcg_gen_wswap_tl tcg_gen_wswap_i64 |
| 118 | #define tcg_gen_revbit8_tl tcg_gen_revbit8_i64 |
| 119 | #define tcg_gen_revbit32_tl tcg_gen_revbit32_i64 |
| 120 | #define tcg_gen_revbit64_tl tcg_gen_revbit64_i64 |
| 121 | #define tcg_gen_revbit_tl tcg_gen_revbit64_i64 |
| 122 | #define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64 |
| 123 | #define tcg_gen_extr_i64_tl tcg_gen_extr32_i64 |
| 124 | #define tcg_gen_andc_tl tcg_gen_andc_i64 |
| 125 | #define tcg_gen_eqv_tl tcg_gen_eqv_i64 |
| 126 | #define tcg_gen_nand_tl tcg_gen_nand_i64 |
| 127 | #define tcg_gen_nor_tl tcg_gen_nor_i64 |
| 128 | #define tcg_gen_orc_tl tcg_gen_orc_i64 |
| 129 | #define tcg_gen_clz_tl tcg_gen_clz_i64 |
| 130 | #define tcg_gen_ctz_tl tcg_gen_ctz_i64 |
| 131 | #define tcg_gen_clzi_tl tcg_gen_clzi_i64 |
| 132 | #define tcg_gen_ctzi_tl tcg_gen_ctzi_i64 |
| 133 | #define tcg_gen_clrsb_tl tcg_gen_clrsb_i64 |
| 134 | #define tcg_gen_ctpop_tl tcg_gen_ctpop_i64 |
| 135 | #define tcg_gen_rotl_tl tcg_gen_rotl_i64 |
| 136 | #define tcg_gen_rotli_tl tcg_gen_rotli_i64 |
| 137 | #define tcg_gen_rotr_tl tcg_gen_rotr_i64 |
| 138 | #define tcg_gen_rotri_tl tcg_gen_rotri_i64 |
| 139 | #define tcg_gen_deposit_tl tcg_gen_deposit_i64 |
| 140 | #define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i64 |
| 141 | #define tcg_gen_extract_tl tcg_gen_extract_i64 |
| 142 | #define tcg_gen_sextract_tl tcg_gen_sextract_i64 |
| 143 | #define tcg_gen_extract2_tl tcg_gen_extract2_i64 |
| 144 | #define tcg_constant_tl tcg_constant_i64 |
| 145 | #define tcg_gen_movcond_tl tcg_gen_movcond_i64 |
| 146 | #define tcg_gen_add2_tl tcg_gen_add2_i64 |
| 147 | #define tcg_gen_sub2_tl tcg_gen_sub2_i64 |
| 148 | #define tcg_gen_addcio_tl tcg_gen_addcio_i64 |
| 149 | #define tcg_gen_mulu2_tl tcg_gen_mulu2_i64 |
| 150 | #define tcg_gen_muls2_tl tcg_gen_muls2_i64 |
| 151 | #define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i64 |
| 152 | #define tcg_gen_smin_tl tcg_gen_smin_i64 |
| 153 | #define tcg_gen_umin_tl tcg_gen_umin_i64 |
| 154 | #define tcg_gen_smax_tl tcg_gen_smax_i64 |
| 155 | #define tcg_gen_umax_tl tcg_gen_umax_i64 |
| 156 | #define tcg_gen_ussub_tl tcg_gen_ussub_i64 |
| 157 | #define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i64 |
| 158 | #define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i64 |
| 159 | #define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i64 |
| 160 | #define tcg_gen_atomic_fetch_and_tl tcg_gen_atomic_fetch_and_i64 |
| 161 | #define tcg_gen_atomic_fetch_or_tl tcg_gen_atomic_fetch_or_i64 |
| 162 | #define tcg_gen_atomic_fetch_xor_tl tcg_gen_atomic_fetch_xor_i64 |
| 163 | #define tcg_gen_atomic_fetch_smin_tl tcg_gen_atomic_fetch_smin_i64 |
| 164 | #define tcg_gen_atomic_fetch_umin_tl tcg_gen_atomic_fetch_umin_i64 |
| 165 | #define tcg_gen_atomic_fetch_smax_tl tcg_gen_atomic_fetch_smax_i64 |
| 166 | #define tcg_gen_atomic_fetch_umax_tl tcg_gen_atomic_fetch_umax_i64 |
| 167 | #define tcg_gen_atomic_add_fetch_tl tcg_gen_atomic_add_fetch_i64 |
| 168 | #define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i64 |
| 169 | #define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i64 |
| 170 | #define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i64 |
| 171 | #define tcg_gen_atomic_smin_fetch_tl tcg_gen_atomic_smin_fetch_i64 |
| 172 | #define tcg_gen_atomic_umin_fetch_tl tcg_gen_atomic_umin_fetch_i64 |
| 173 | #define tcg_gen_atomic_smax_fetch_tl tcg_gen_atomic_smax_fetch_i64 |
| 174 | #define tcg_gen_atomic_umax_fetch_tl tcg_gen_atomic_umax_fetch_i64 |
| 175 | #define tcg_gen_dup_tl_vec tcg_gen_dup_i64_vec |
| 176 | #define tcg_gen_dup_tl tcg_gen_dup_i64 |
| 177 | #define dup_const_tl dup_const |
| 178 | #else |
| 179 | #define tcg_gen_movi_tl tcg_gen_movi_i32 |
| 180 | #define tcg_gen_mov_tl tcg_gen_mov_i32 |
| 181 | #define tcg_gen_ld8u_tl tcg_gen_ld8u_i32 |
| 182 | #define tcg_gen_ld8s_tl tcg_gen_ld8s_i32 |
| 183 | #define tcg_gen_ld16u_tl tcg_gen_ld16u_i32 |
| 184 | #define tcg_gen_ld16s_tl tcg_gen_ld16s_i32 |
| 185 | #define tcg_gen_ld32u_tl tcg_gen_ld_i32 |
| 186 | #define tcg_gen_ld32s_tl tcg_gen_ld_i32 |
| 187 | #define tcg_gen_ld_tl tcg_gen_ld_i32 |
| 188 | #define tcg_gen_st8_tl tcg_gen_st8_i32 |
| 189 | #define tcg_gen_st16_tl tcg_gen_st16_i32 |
| 190 | #define tcg_gen_st32_tl tcg_gen_st_i32 |
| 191 | #define tcg_gen_st_tl tcg_gen_st_i32 |
| 192 | #define tcg_gen_add_tl tcg_gen_add_i32 |
| 193 | #define tcg_gen_addi_tl tcg_gen_addi_i32 |
| 194 | #define tcg_gen_sub_tl tcg_gen_sub_i32 |
| 195 | #define tcg_gen_neg_tl tcg_gen_neg_i32 |
| 196 | #define tcg_gen_abs_tl tcg_gen_abs_i32 |
| 197 | #define tcg_gen_subfi_tl tcg_gen_subfi_i32 |
| 198 | #define tcg_gen_subi_tl tcg_gen_subi_i32 |
| 199 | #define tcg_gen_and_tl tcg_gen_and_i32 |
| 200 | #define tcg_gen_andi_tl tcg_gen_andi_i32 |
| 201 | #define tcg_gen_or_tl tcg_gen_or_i32 |
| 202 | #define tcg_gen_ori_tl tcg_gen_ori_i32 |
| 203 | #define tcg_gen_xor_tl tcg_gen_xor_i32 |
| 204 | #define tcg_gen_xori_tl tcg_gen_xori_i32 |
| 205 | #define tcg_gen_not_tl tcg_gen_not_i32 |
| 206 | #define tcg_gen_shl_tl tcg_gen_shl_i32 |
| 207 | #define tcg_gen_shli_tl tcg_gen_shli_i32 |
| 208 | #define tcg_gen_shr_tl tcg_gen_shr_i32 |
| 209 | #define tcg_gen_shri_tl tcg_gen_shri_i32 |
| 210 | #define tcg_gen_sar_tl tcg_gen_sar_i32 |
| 211 | #define tcg_gen_sari_tl tcg_gen_sari_i32 |
| 212 | #define tcg_gen_brcond_tl tcg_gen_brcond_i32 |
| 213 | #define tcg_gen_brcondi_tl tcg_gen_brcondi_i32 |
| 214 | #define tcg_gen_setcond_tl tcg_gen_setcond_i32 |
| 215 | #define tcg_gen_setcondi_tl tcg_gen_setcondi_i32 |
| 216 | #define tcg_gen_negsetcond_tl tcg_gen_negsetcond_i32 |
| 217 | #define tcg_gen_negsetcondi_tl tcg_gen_negsetcondi_i32 |
| 218 | #define tcg_gen_mul_tl tcg_gen_mul_i32 |
| 219 | #define tcg_gen_muli_tl tcg_gen_muli_i32 |
| 220 | #define tcg_gen_div_tl tcg_gen_div_i32 |
| 221 | #define tcg_gen_rem_tl tcg_gen_rem_i32 |
| 222 | #define tcg_gen_divu_tl tcg_gen_divu_i32 |
| 223 | #define tcg_gen_remu_tl tcg_gen_remu_i32 |
| 224 | #define tcg_gen_discard_tl tcg_gen_discard_i32 |
| 225 | #define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32 |
| 226 | #define tcg_gen_trunc_i64_tl tcg_gen_extrl_i64_i32 |
| 227 | #define tcg_gen_extu_i32_tl tcg_gen_mov_i32 |
| 228 | #define tcg_gen_ext_i32_tl tcg_gen_mov_i32 |
| 229 | #define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64 |
| 230 | #define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64 |
| 231 | #define tcg_gen_ext8u_tl tcg_gen_ext8u_i32 |
| 232 | #define tcg_gen_ext8s_tl tcg_gen_ext8s_i32 |
| 233 | #define tcg_gen_ext16u_tl tcg_gen_ext16u_i32 |
| 234 | #define tcg_gen_ext16s_tl tcg_gen_ext16s_i32 |
| 235 | #define tcg_gen_ext32u_tl tcg_gen_mov_i32 |
| 236 | #define tcg_gen_ext32s_tl tcg_gen_mov_i32 |
| 237 | #define tcg_gen_ext_tl tcg_gen_ext_i32 |
| 238 | #define tcg_gen_bswap16_tl tcg_gen_bswap16_i32 |
| 239 | #define tcg_gen_bswap32_tl(D, S, F) tcg_gen_bswap32_i32(D, S) |
| 240 | #define tcg_gen_bswap_tl tcg_gen_bswap32_i32 |
| 241 | #define tcg_gen_hswap_tl tcg_gen_hswap_i32 |
| 242 | #define tcg_gen_revbit8_tl tcg_gen_revbit8_i32 |
| 243 | #define tcg_gen_revbit32_tl(D, S, F) tcg_gen_revbit32_i32(D, S) |
| 244 | #define tcg_gen_revbit_tl tcg_gen_revbit32_i32 |
| 245 | #define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64 |
| 246 | #define tcg_gen_extr_i64_tl tcg_gen_extr_i64_i32 |
| 247 | #define tcg_gen_andc_tl tcg_gen_andc_i32 |
| 248 | #define tcg_gen_eqv_tl tcg_gen_eqv_i32 |
| 249 | #define tcg_gen_nand_tl tcg_gen_nand_i32 |
| 250 | #define tcg_gen_nor_tl tcg_gen_nor_i32 |
| 251 | #define tcg_gen_orc_tl tcg_gen_orc_i32 |
| 252 | #define tcg_gen_clz_tl tcg_gen_clz_i32 |
| 253 | #define tcg_gen_ctz_tl tcg_gen_ctz_i32 |
| 254 | #define tcg_gen_clzi_tl tcg_gen_clzi_i32 |
| 255 | #define tcg_gen_ctzi_tl tcg_gen_ctzi_i32 |
| 256 | #define tcg_gen_clrsb_tl tcg_gen_clrsb_i32 |
| 257 | #define tcg_gen_ctpop_tl tcg_gen_ctpop_i32 |
| 258 | #define tcg_gen_rotl_tl tcg_gen_rotl_i32 |
| 259 | #define tcg_gen_rotli_tl tcg_gen_rotli_i32 |
| 260 | #define tcg_gen_rotr_tl tcg_gen_rotr_i32 |
| 261 | #define tcg_gen_rotri_tl tcg_gen_rotri_i32 |
| 262 | #define tcg_gen_deposit_tl tcg_gen_deposit_i32 |
| 263 | #define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i32 |
| 264 | #define tcg_gen_extract_tl tcg_gen_extract_i32 |
| 265 | #define tcg_gen_sextract_tl tcg_gen_sextract_i32 |
| 266 | #define tcg_gen_extract2_tl tcg_gen_extract2_i32 |
| 267 | #define tcg_constant_tl tcg_constant_i32 |
| 268 | #define tcg_gen_movcond_tl tcg_gen_movcond_i32 |
| 269 | #define tcg_gen_add2_tl tcg_gen_add2_i32 |
| 270 | #define tcg_gen_sub2_tl tcg_gen_sub2_i32 |
| 271 | #define tcg_gen_addcio_tl tcg_gen_addcio_i32 |
| 272 | #define tcg_gen_mulu2_tl tcg_gen_mulu2_i32 |
| 273 | #define tcg_gen_muls2_tl tcg_gen_muls2_i32 |
| 274 | #define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i32 |
| 275 | #define tcg_gen_smin_tl tcg_gen_smin_i32 |
| 276 | #define tcg_gen_umin_tl tcg_gen_umin_i32 |
| 277 | #define tcg_gen_smax_tl tcg_gen_smax_i32 |
| 278 | #define tcg_gen_umax_tl tcg_gen_umax_i32 |
| 279 | #define tcg_gen_ussub_tl tcg_gen_ussub_i32 |
| 280 | #define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i32 |
| 281 | #define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i32 |
| 282 | #define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i32 |
| 283 | #define tcg_gen_atomic_fetch_and_tl tcg_gen_atomic_fetch_and_i32 |
| 284 | #define tcg_gen_atomic_fetch_or_tl tcg_gen_atomic_fetch_or_i32 |
| 285 | #define tcg_gen_atomic_fetch_xor_tl tcg_gen_atomic_fetch_xor_i32 |
| 286 | #define tcg_gen_atomic_fetch_smin_tl tcg_gen_atomic_fetch_smin_i32 |
| 287 | #define tcg_gen_atomic_fetch_umin_tl tcg_gen_atomic_fetch_umin_i32 |
| 288 | #define tcg_gen_atomic_fetch_smax_tl tcg_gen_atomic_fetch_smax_i32 |
| 289 | #define tcg_gen_atomic_fetch_umax_tl tcg_gen_atomic_fetch_umax_i32 |
| 290 | #define tcg_gen_atomic_add_fetch_tl tcg_gen_atomic_add_fetch_i32 |
| 291 | #define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i32 |
| 292 | #define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i32 |
| 293 | #define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i32 |
| 294 | #define tcg_gen_atomic_smin_fetch_tl tcg_gen_atomic_smin_fetch_i32 |
| 295 | #define tcg_gen_atomic_umin_fetch_tl tcg_gen_atomic_umin_fetch_i32 |
| 296 | #define tcg_gen_atomic_smax_fetch_tl tcg_gen_atomic_smax_fetch_i32 |
| 297 | #define tcg_gen_atomic_umax_fetch_tl tcg_gen_atomic_umax_fetch_i32 |
| 298 | #define tcg_gen_dup_tl_vec tcg_gen_dup_i32_vec |
| 299 | #define tcg_gen_dup_tl tcg_gen_dup_i32 |
| 300 | |
| 301 | #define dup_const_tl(VECE, C) \ |
| 302 | (__builtin_constant_p(VECE) \ |
| 303 | ? ( (VECE) == MO_8 ? 0x01010101ul * (uint8_t)(C) \ |
| 304 | : (VECE) == MO_16 ? 0x00010001ul * (uint16_t)(C) \ |
| 305 | : (VECE) == MO_32 ? 0x00000001ul * (uint32_t)(C) \ |
| 306 | : (qemu_build_not_reached_always(), 0)) \ |
| 307 | : (target_long)dup_const(VECE, C)) |
| 308 | |
| 309 | #endif /* TARGET_LONG_BITS == 64 */ |
| 310 | #endif /* TCG_TCG_OP_H */ |