| 1 | /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ |
| 2 | /* |
| 3 | * Copyright (C) 2012,2013 - ARM Ltd |
| 4 | * Author: Marc Zyngier <marc.zyngier@arm.com> |
| 5 | * |
| 6 | * Derived from arch/arm/include/uapi/asm/kvm.h: |
| 7 | * Copyright (C) 2012 - Virtual Open Systems and Columbia University |
| 8 | * Author: Christoffer Dall <c.dall@virtualopensystems.com> |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License version 2 as |
| 12 | * published by the Free Software Foundation. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 21 | */ |
| 22 | |
| 23 | #ifndef __ARM_KVM_H__ |
| 24 | #define __ARM_KVM_H__ |
| 25 | |
| 26 | #define KVM_SPSR_EL1 0 |
| 27 | #define KVM_SPSR_SVC KVM_SPSR_EL1 |
| 28 | #define KVM_SPSR_ABT 1 |
| 29 | #define KVM_SPSR_UND 2 |
| 30 | #define KVM_SPSR_IRQ 3 |
| 31 | #define KVM_SPSR_FIQ 4 |
| 32 | #define KVM_NR_SPSR 5 |
| 33 | |
| 34 | #ifndef __ASSEMBLER__ |
| 35 | #include <linux/psci.h> |
| 36 | #include <linux/types.h> |
| 37 | #include <asm/ptrace.h> |
| 38 | #include <asm/sve_context.h> |
| 39 | |
| 40 | #define __KVM_HAVE_IRQ_LINE |
| 41 | #define __KVM_HAVE_VCPU_EVENTS |
| 42 | |
| 43 | #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 |
| 44 | #define KVM_DIRTY_LOG_PAGE_OFFSET 64 |
| 45 | |
| 46 | struct kvm_regs { |
| 47 | struct user_pt_regs regs; /* sp = sp_el0 */ |
| 48 | |
| 49 | __u64 sp_el1; |
| 50 | __u64 elr_el1; |
| 51 | |
| 52 | __u64 spsr[KVM_NR_SPSR]; |
| 53 | |
| 54 | struct user_fpsimd_state fp_regs; |
| 55 | }; |
| 56 | |
| 57 | /* |
| 58 | * Supported CPU Targets - Adding a new target type is not recommended, |
| 59 | * unless there are some special registers not supported by the |
| 60 | * genericv8 syreg table. |
| 61 | */ |
| 62 | #define KVM_ARM_TARGET_AEM_V8 0 |
| 63 | #define KVM_ARM_TARGET_FOUNDATION_V8 1 |
| 64 | #define KVM_ARM_TARGET_CORTEX_A57 2 |
| 65 | #define KVM_ARM_TARGET_XGENE_POTENZA 3 |
| 66 | #define KVM_ARM_TARGET_CORTEX_A53 4 |
| 67 | /* Generic ARM v8 target */ |
| 68 | #define KVM_ARM_TARGET_GENERIC_V8 5 |
| 69 | |
| 70 | #define KVM_ARM_NUM_TARGETS 6 |
| 71 | |
| 72 | /* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */ |
| 73 | #define KVM_ARM_DEVICE_TYPE_SHIFT 0 |
| 74 | #define KVM_ARM_DEVICE_TYPE_MASK __GENMASK(KVM_ARM_DEVICE_TYPE_SHIFT + 15, \ |
| 75 | KVM_ARM_DEVICE_TYPE_SHIFT) |
| 76 | #define KVM_ARM_DEVICE_ID_SHIFT 16 |
| 77 | #define KVM_ARM_DEVICE_ID_MASK __GENMASK(KVM_ARM_DEVICE_ID_SHIFT + 15, \ |
| 78 | KVM_ARM_DEVICE_ID_SHIFT) |
| 79 | |
| 80 | /* Supported device IDs */ |
| 81 | #define KVM_ARM_DEVICE_VGIC_V2 0 |
| 82 | |
| 83 | /* Supported VGIC address types */ |
| 84 | #define KVM_VGIC_V2_ADDR_TYPE_DIST 0 |
| 85 | #define KVM_VGIC_V2_ADDR_TYPE_CPU 1 |
| 86 | |
| 87 | #define KVM_VGIC_V2_DIST_SIZE 0x1000 |
| 88 | #define KVM_VGIC_V2_CPU_SIZE 0x2000 |
| 89 | |
| 90 | /* Supported VGICv3 address types */ |
| 91 | #define KVM_VGIC_V3_ADDR_TYPE_DIST 2 |
| 92 | #define KVM_VGIC_V3_ADDR_TYPE_REDIST 3 |
| 93 | #define KVM_VGIC_ITS_ADDR_TYPE 4 |
| 94 | #define KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION 5 |
| 95 | |
| 96 | #define KVM_VGIC_V3_DIST_SIZE SZ_64K |
| 97 | #define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K) |
| 98 | #define KVM_VGIC_V3_ITS_SIZE (2 * SZ_64K) |
| 99 | |
| 100 | #define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF state */ |
| 101 | #define KVM_ARM_VCPU_EL1_32BIT 1 /* CPU running a 32bit VM */ |
| 102 | #define KVM_ARM_VCPU_PSCI_0_2 2 /* CPU uses PSCI v0.2 */ |
| 103 | #define KVM_ARM_VCPU_PMU_V3 3 /* Support guest PMUv3 */ |
| 104 | #define KVM_ARM_VCPU_SVE 4 /* enable SVE for this CPU */ |
| 105 | #define KVM_ARM_VCPU_PTRAUTH_ADDRESS 5 /* VCPU uses address authentication */ |
| 106 | #define KVM_ARM_VCPU_PTRAUTH_GENERIC 6 /* VCPU uses generic authentication */ |
| 107 | #define KVM_ARM_VCPU_HAS_EL2 7 /* Support nested virtualization */ |
| 108 | #define KVM_ARM_VCPU_HAS_EL2_E2H0 8 /* Limit NV support to E2H RES0 */ |
| 109 | |
| 110 | struct kvm_vcpu_init { |
| 111 | __u32 target; |
| 112 | __u32 features[7]; |
| 113 | }; |
| 114 | |
| 115 | struct kvm_sregs { |
| 116 | }; |
| 117 | |
| 118 | struct kvm_fpu { |
| 119 | }; |
| 120 | |
| 121 | /* |
| 122 | * See v8 ARM ARM D7.3: Debug Registers |
| 123 | * |
| 124 | * The architectural limit is 16 debug registers of each type although |
| 125 | * in practice there are usually less (see ID_AA64DFR0_EL1). |
| 126 | * |
| 127 | * Although the control registers are architecturally defined as 32 |
| 128 | * bits wide we use a 64 bit structure here to keep parity with |
| 129 | * KVM_GET/SET_ONE_REG behaviour which treats all system registers as |
| 130 | * 64 bit values. It also allows for the possibility of the |
| 131 | * architecture expanding the control registers without having to |
| 132 | * change the userspace ABI. |
| 133 | */ |
| 134 | #define KVM_ARM_MAX_DBG_REGS 16 |
| 135 | struct kvm_guest_debug_arch { |
| 136 | __u64 dbg_bcr[KVM_ARM_MAX_DBG_REGS]; |
| 137 | __u64 dbg_bvr[KVM_ARM_MAX_DBG_REGS]; |
| 138 | __u64 dbg_wcr[KVM_ARM_MAX_DBG_REGS]; |
| 139 | __u64 dbg_wvr[KVM_ARM_MAX_DBG_REGS]; |
| 140 | }; |
| 141 | |
| 142 | #define KVM_DEBUG_ARCH_HSR_HIGH_VALID (1 << 0) |
| 143 | struct kvm_debug_exit_arch { |
| 144 | __u32 hsr; |
| 145 | __u32 hsr_high; /* ESR_EL2[61:32] */ |
| 146 | __u64 far; /* used for watchpoints */ |
| 147 | }; |
| 148 | |
| 149 | /* |
| 150 | * Architecture specific defines for kvm_guest_debug->control |
| 151 | */ |
| 152 | |
| 153 | #define KVM_GUESTDBG_USE_SW_BP (1 << 16) |
| 154 | #define KVM_GUESTDBG_USE_HW (1 << 17) |
| 155 | |
| 156 | struct kvm_sync_regs { |
| 157 | /* Used with KVM_CAP_ARM_USER_IRQ */ |
| 158 | __u64 device_irq_level; |
| 159 | }; |
| 160 | |
| 161 | /* Bits for run->s.regs.device_irq_level */ |
| 162 | #define KVM_ARM_DEV_EL1_VTIMER (1 << 0) |
| 163 | #define KVM_ARM_DEV_EL1_PTIMER (1 << 1) |
| 164 | #define KVM_ARM_DEV_PMU (1 << 2) |
| 165 | |
| 166 | /* |
| 167 | * PMU filter structure. Describe a range of events with a particular |
| 168 | * action. To be used with KVM_ARM_VCPU_PMU_V3_FILTER. |
| 169 | */ |
| 170 | struct kvm_pmu_event_filter { |
| 171 | __u16 base_event; |
| 172 | __u16 nevents; |
| 173 | |
| 174 | #define KVM_PMU_EVENT_ALLOW 0 |
| 175 | #define KVM_PMU_EVENT_DENY 1 |
| 176 | |
| 177 | __u8 action; |
| 178 | __u8 pad[3]; |
| 179 | }; |
| 180 | |
| 181 | /* for KVM_GET/SET_VCPU_EVENTS */ |
| 182 | struct kvm_vcpu_events { |
| 183 | struct { |
| 184 | __u8 serror_pending; |
| 185 | __u8 serror_has_esr; |
| 186 | __u8 ext_dabt_pending; |
| 187 | /* Align it to 8 bytes */ |
| 188 | __u8 pad[5]; |
| 189 | __u64 serror_esr; |
| 190 | } exception; |
| 191 | __u32 reserved[12]; |
| 192 | }; |
| 193 | |
| 194 | struct kvm_arm_copy_mte_tags { |
| 195 | __u64 guest_ipa; |
| 196 | __u64 length; |
| 197 | void *addr; |
| 198 | __u64 flags; |
| 199 | __u64 reserved[2]; |
| 200 | }; |
| 201 | |
| 202 | /* |
| 203 | * Counter/Timer offset structure. Describe the virtual/physical offset. |
| 204 | * To be used with KVM_ARM_SET_COUNTER_OFFSET. |
| 205 | */ |
| 206 | struct kvm_arm_counter_offset { |
| 207 | __u64 counter_offset; |
| 208 | __u64 reserved; |
| 209 | }; |
| 210 | |
| 211 | #define KVM_ARM_TAGS_TO_GUEST 0 |
| 212 | #define KVM_ARM_TAGS_FROM_GUEST 1 |
| 213 | |
| 214 | /* If you need to interpret the index values, here is the key: */ |
| 215 | #define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000 |
| 216 | #define KVM_REG_ARM_COPROC_SHIFT 16 |
| 217 | |
| 218 | /* Normal registers are mapped as coprocessor 16. */ |
| 219 | #define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT) |
| 220 | #define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / sizeof(__u32)) |
| 221 | |
| 222 | /* Some registers need more space to represent values. */ |
| 223 | #define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT) |
| 224 | #define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00 |
| 225 | #define KVM_REG_ARM_DEMUX_ID_SHIFT 8 |
| 226 | #define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT) |
| 227 | #define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF |
| 228 | #define KVM_REG_ARM_DEMUX_VAL_SHIFT 0 |
| 229 | |
| 230 | /* AArch64 system registers */ |
| 231 | #define KVM_REG_ARM64_SYSREG (0x0013 << KVM_REG_ARM_COPROC_SHIFT) |
| 232 | #define KVM_REG_ARM64_SYSREG_OP0_MASK 0x000000000000c000 |
| 233 | #define KVM_REG_ARM64_SYSREG_OP0_SHIFT 14 |
| 234 | #define KVM_REG_ARM64_SYSREG_OP1_MASK 0x0000000000003800 |
| 235 | #define KVM_REG_ARM64_SYSREG_OP1_SHIFT 11 |
| 236 | #define KVM_REG_ARM64_SYSREG_CRN_MASK 0x0000000000000780 |
| 237 | #define KVM_REG_ARM64_SYSREG_CRN_SHIFT 7 |
| 238 | #define KVM_REG_ARM64_SYSREG_CRM_MASK 0x0000000000000078 |
| 239 | #define KVM_REG_ARM64_SYSREG_CRM_SHIFT 3 |
| 240 | #define KVM_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007 |
| 241 | #define KVM_REG_ARM64_SYSREG_OP2_SHIFT 0 |
| 242 | |
| 243 | #define ARM64_SYS_REG_SHIFT_MASK(x,n) \ |
| 244 | (((x) << KVM_REG_ARM64_SYSREG_ ## n ## _SHIFT) & \ |
| 245 | KVM_REG_ARM64_SYSREG_ ## n ## _MASK) |
| 246 | |
| 247 | #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \ |
| 248 | (KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | \ |
| 249 | ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \ |
| 250 | ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \ |
| 251 | ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \ |
| 252 | ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \ |
| 253 | ARM64_SYS_REG_SHIFT_MASK(op2, OP2)) |
| 254 | |
| 255 | #define ARM64_SYS_REG(...) (__ARM64_SYS_REG(__VA_ARGS__) | KVM_REG_SIZE_U64) |
| 256 | |
| 257 | /* Physical Timer EL0 Registers */ |
| 258 | #define KVM_REG_ARM_PTIMER_CTL ARM64_SYS_REG(3, 3, 14, 2, 1) |
| 259 | #define KVM_REG_ARM_PTIMER_CVAL ARM64_SYS_REG(3, 3, 14, 2, 2) |
| 260 | #define KVM_REG_ARM_PTIMER_CNT ARM64_SYS_REG(3, 3, 14, 0, 1) |
| 261 | |
| 262 | /* |
| 263 | * EL0 Virtual Timer Registers |
| 264 | * |
| 265 | * WARNING: |
| 266 | * KVM_REG_ARM_TIMER_CVAL and KVM_REG_ARM_TIMER_CNT are not defined |
| 267 | * with the appropriate register encodings. Their values have been |
| 268 | * accidentally swapped. As this is set API, the definitions here |
| 269 | * must be used, rather than ones derived from the encodings. |
| 270 | */ |
| 271 | #define KVM_REG_ARM_TIMER_CTL ARM64_SYS_REG(3, 3, 14, 3, 1) |
| 272 | #define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2) |
| 273 | #define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2) |
| 274 | |
| 275 | /* KVM-as-firmware specific pseudo-registers */ |
| 276 | #define KVM_REG_ARM_FW (0x0014 << KVM_REG_ARM_COPROC_SHIFT) |
| 277 | #define KVM_REG_ARM_FW_REG(r) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \ |
| 278 | KVM_REG_ARM_FW | ((r) & 0xffff)) |
| 279 | #define KVM_REG_ARM_PSCI_VERSION KVM_REG_ARM_FW_REG(0) |
| 280 | #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1 KVM_REG_ARM_FW_REG(1) |
| 281 | #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_AVAIL 0 |
| 282 | #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_AVAIL 1 |
| 283 | #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_REQUIRED 2 |
| 284 | |
| 285 | /* |
| 286 | * Only two states can be presented by the host kernel: |
| 287 | * - NOT_REQUIRED: the guest doesn't need to do anything |
| 288 | * - NOT_AVAIL: the guest isn't mitigated (it can still use SSBS if available) |
| 289 | * |
| 290 | * All the other values are deprecated. The host still accepts all |
| 291 | * values (they are ABI), but will narrow them to the above two. |
| 292 | */ |
| 293 | #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2 KVM_REG_ARM_FW_REG(2) |
| 294 | #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL 0 |
| 295 | #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_UNKNOWN 1 |
| 296 | #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_AVAIL 2 |
| 297 | #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED 3 |
| 298 | #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_ENABLED (1U << 4) |
| 299 | |
| 300 | #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3 KVM_REG_ARM_FW_REG(3) |
| 301 | #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_NOT_AVAIL 0 |
| 302 | #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_AVAIL 1 |
| 303 | #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_NOT_REQUIRED 2 |
| 304 | |
| 305 | /* SVE registers */ |
| 306 | #define KVM_REG_ARM64_SVE (0x15 << KVM_REG_ARM_COPROC_SHIFT) |
| 307 | |
| 308 | /* Z- and P-regs occupy blocks at the following offsets within this range: */ |
| 309 | #define KVM_REG_ARM64_SVE_ZREG_BASE 0 |
| 310 | #define KVM_REG_ARM64_SVE_PREG_BASE 0x400 |
| 311 | #define KVM_REG_ARM64_SVE_FFR_BASE 0x600 |
| 312 | |
| 313 | #define KVM_ARM64_SVE_NUM_ZREGS __SVE_NUM_ZREGS |
| 314 | #define KVM_ARM64_SVE_NUM_PREGS __SVE_NUM_PREGS |
| 315 | |
| 316 | #define KVM_ARM64_SVE_MAX_SLICES 32 |
| 317 | |
| 318 | #define KVM_REG_ARM64_SVE_ZREG(n, i) \ |
| 319 | (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_ZREG_BASE | \ |
| 320 | KVM_REG_SIZE_U2048 | \ |
| 321 | (((n) & (KVM_ARM64_SVE_NUM_ZREGS - 1)) << 5) | \ |
| 322 | ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1))) |
| 323 | |
| 324 | #define KVM_REG_ARM64_SVE_PREG(n, i) \ |
| 325 | (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_PREG_BASE | \ |
| 326 | KVM_REG_SIZE_U256 | \ |
| 327 | (((n) & (KVM_ARM64_SVE_NUM_PREGS - 1)) << 5) | \ |
| 328 | ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1))) |
| 329 | |
| 330 | #define KVM_REG_ARM64_SVE_FFR(i) \ |
| 331 | (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_FFR_BASE | \ |
| 332 | KVM_REG_SIZE_U256 | \ |
| 333 | ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1))) |
| 334 | |
| 335 | /* |
| 336 | * Register values for KVM_REG_ARM64_SVE_ZREG(), KVM_REG_ARM64_SVE_PREG() and |
| 337 | * KVM_REG_ARM64_SVE_FFR() are represented in memory in an endianness- |
| 338 | * invariant layout which differs from the layout used for the FPSIMD |
| 339 | * V-registers on big-endian systems: see sigcontext.h for more explanation. |
| 340 | */ |
| 341 | |
| 342 | #define KVM_ARM64_SVE_VQ_MIN __SVE_VQ_MIN |
| 343 | #define KVM_ARM64_SVE_VQ_MAX __SVE_VQ_MAX |
| 344 | |
| 345 | /* Vector lengths pseudo-register: */ |
| 346 | #define KVM_REG_ARM64_SVE_VLS (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | \ |
| 347 | KVM_REG_SIZE_U512 | 0xffff) |
| 348 | #define KVM_ARM64_SVE_VLS_WORDS \ |
| 349 | ((KVM_ARM64_SVE_VQ_MAX - KVM_ARM64_SVE_VQ_MIN) / 64 + 1) |
| 350 | |
| 351 | /* Bitmap feature firmware registers */ |
| 352 | #define KVM_REG_ARM_FW_FEAT_BMAP (0x0016 << KVM_REG_ARM_COPROC_SHIFT) |
| 353 | #define KVM_REG_ARM_FW_FEAT_BMAP_REG(r) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \ |
| 354 | KVM_REG_ARM_FW_FEAT_BMAP | \ |
| 355 | ((r) & 0xffff)) |
| 356 | |
| 357 | #define KVM_REG_ARM_STD_BMAP KVM_REG_ARM_FW_FEAT_BMAP_REG(0) |
| 358 | |
| 359 | enum { |
| 360 | KVM_REG_ARM_STD_BIT_TRNG_V1_0 = 0, |
| 361 | }; |
| 362 | |
| 363 | #define KVM_REG_ARM_STD_HYP_BMAP KVM_REG_ARM_FW_FEAT_BMAP_REG(1) |
| 364 | |
| 365 | enum { |
| 366 | KVM_REG_ARM_STD_HYP_BIT_PV_TIME = 0, |
| 367 | }; |
| 368 | |
| 369 | /* Vendor hyper call function numbers 0-63 */ |
| 370 | #define KVM_REG_ARM_VENDOR_HYP_BMAP KVM_REG_ARM_FW_FEAT_BMAP_REG(2) |
| 371 | |
| 372 | enum { |
| 373 | KVM_REG_ARM_VENDOR_HYP_BIT_FUNC_FEAT = 0, |
| 374 | KVM_REG_ARM_VENDOR_HYP_BIT_PTP = 1, |
| 375 | }; |
| 376 | |
| 377 | /* Vendor hyper call function numbers 64-127 */ |
| 378 | #define KVM_REG_ARM_VENDOR_HYP_BMAP_2 KVM_REG_ARM_FW_FEAT_BMAP_REG(3) |
| 379 | |
| 380 | enum { |
| 381 | KVM_REG_ARM_VENDOR_HYP_BIT_DISCOVER_IMPL_VER = 0, |
| 382 | KVM_REG_ARM_VENDOR_HYP_BIT_DISCOVER_IMPL_CPUS = 1, |
| 383 | }; |
| 384 | |
| 385 | /* Device Control API on vm fd */ |
| 386 | #define KVM_ARM_VM_SMCCC_CTRL 0 |
| 387 | #define KVM_ARM_VM_SMCCC_FILTER 0 |
| 388 | |
| 389 | /* Device Control API: ARM VGIC */ |
| 390 | #define KVM_DEV_ARM_VGIC_GRP_ADDR 0 |
| 391 | #define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1 |
| 392 | #define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2 |
| 393 | #define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32 |
| 394 | #define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT) |
| 395 | #define KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32 |
| 396 | #define KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \ |
| 397 | (0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT) |
| 398 | #define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0 |
| 399 | #define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT) |
| 400 | #define KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff) |
| 401 | #define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3 |
| 402 | #define KVM_DEV_ARM_VGIC_GRP_CTRL 4 |
| 403 | #define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5 |
| 404 | #define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6 |
| 405 | #define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7 |
| 406 | #define KVM_DEV_ARM_VGIC_GRP_ITS_REGS 8 |
| 407 | #define KVM_DEV_ARM_VGIC_GRP_MAINT_IRQ 9 |
| 408 | #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT 10 |
| 409 | #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \ |
| 410 | (0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT) |
| 411 | #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff |
| 412 | #define VGIC_LEVEL_INFO_LINE_LEVEL 0 |
| 413 | |
| 414 | #define KVM_DEV_ARM_VGIC_CTRL_INIT 0 |
| 415 | #define KVM_DEV_ARM_ITS_SAVE_TABLES 1 |
| 416 | #define KVM_DEV_ARM_ITS_RESTORE_TABLES 2 |
| 417 | #define KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES 3 |
| 418 | #define KVM_DEV_ARM_ITS_CTRL_RESET 4 |
| 419 | #define KVM_DEV_ARM_VGIC_USERSPACE_PPIS 5 |
| 420 | |
| 421 | /* Device Control API on vcpu fd */ |
| 422 | #define KVM_ARM_VCPU_PMU_V3_CTRL 0 |
| 423 | #define KVM_ARM_VCPU_PMU_V3_IRQ 0 |
| 424 | #define KVM_ARM_VCPU_PMU_V3_INIT 1 |
| 425 | #define KVM_ARM_VCPU_PMU_V3_FILTER 2 |
| 426 | #define KVM_ARM_VCPU_PMU_V3_SET_PMU 3 |
| 427 | #define KVM_ARM_VCPU_PMU_V3_SET_NR_COUNTERS 4 |
| 428 | #define KVM_ARM_VCPU_TIMER_CTRL 1 |
| 429 | #define KVM_ARM_VCPU_TIMER_IRQ_VTIMER 0 |
| 430 | #define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1 |
| 431 | #define KVM_ARM_VCPU_TIMER_IRQ_HVTIMER 2 |
| 432 | #define KVM_ARM_VCPU_TIMER_IRQ_HPTIMER 3 |
| 433 | #define KVM_ARM_VCPU_PVTIME_CTRL 2 |
| 434 | #define KVM_ARM_VCPU_PVTIME_IPA 0 |
| 435 | |
| 436 | /* KVM_IRQ_LINE irq field index values */ |
| 437 | #define KVM_ARM_IRQ_VCPU2_SHIFT 28 |
| 438 | #define KVM_ARM_IRQ_VCPU2_MASK 0xf |
| 439 | #define KVM_ARM_IRQ_TYPE_SHIFT 24 |
| 440 | #define KVM_ARM_IRQ_TYPE_MASK 0xf |
| 441 | #define KVM_ARM_IRQ_VCPU_SHIFT 16 |
| 442 | #define KVM_ARM_IRQ_VCPU_MASK 0xff |
| 443 | #define KVM_ARM_IRQ_NUM_SHIFT 0 |
| 444 | #define KVM_ARM_IRQ_NUM_MASK 0xffff |
| 445 | |
| 446 | /* irq_type field */ |
| 447 | #define KVM_ARM_IRQ_TYPE_CPU 0 |
| 448 | #define KVM_ARM_IRQ_TYPE_SPI 1 |
| 449 | #define KVM_ARM_IRQ_TYPE_PPI 2 |
| 450 | |
| 451 | /* out-of-kernel GIC cpu interrupt injection irq_number field */ |
| 452 | #define KVM_ARM_IRQ_CPU_IRQ 0 |
| 453 | #define KVM_ARM_IRQ_CPU_FIQ 1 |
| 454 | |
| 455 | /* |
| 456 | * This used to hold the highest supported SPI, but it is now obsolete |
| 457 | * and only here to provide source code level compatibility with older |
| 458 | * userland. The highest SPI number can be set via KVM_DEV_ARM_VGIC_GRP_NR_IRQS. |
| 459 | */ |
| 460 | #define KVM_ARM_IRQ_GIC_MAX 127 |
| 461 | |
| 462 | /* One single KVM irqchip, ie. the VGIC */ |
| 463 | #define KVM_NR_IRQCHIPS 1 |
| 464 | |
| 465 | /* PSCI interface */ |
| 466 | #define KVM_PSCI_FN_BASE 0x95c1ba5e |
| 467 | #define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n)) |
| 468 | |
| 469 | #define KVM_PSCI_FN_CPU_SUSPEND KVM_PSCI_FN(0) |
| 470 | #define KVM_PSCI_FN_CPU_OFF KVM_PSCI_FN(1) |
| 471 | #define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2) |
| 472 | #define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3) |
| 473 | |
| 474 | #define KVM_PSCI_RET_SUCCESS PSCI_RET_SUCCESS |
| 475 | #define KVM_PSCI_RET_NI PSCI_RET_NOT_SUPPORTED |
| 476 | #define KVM_PSCI_RET_INVAL PSCI_RET_INVALID_PARAMS |
| 477 | #define KVM_PSCI_RET_DENIED PSCI_RET_DENIED |
| 478 | |
| 479 | /* arm64-specific kvm_run::system_event flags */ |
| 480 | /* |
| 481 | * Reset caused by a PSCI v1.1 SYSTEM_RESET2 call. |
| 482 | * Valid only when the system event has a type of KVM_SYSTEM_EVENT_RESET. |
| 483 | */ |
| 484 | #define KVM_SYSTEM_EVENT_RESET_FLAG_PSCI_RESET2 (1ULL << 0) |
| 485 | |
| 486 | /* |
| 487 | * Shutdown caused by a PSCI v1.3 SYSTEM_OFF2 call. |
| 488 | * Valid only when the system event has a type of KVM_SYSTEM_EVENT_SHUTDOWN. |
| 489 | */ |
| 490 | #define KVM_SYSTEM_EVENT_SHUTDOWN_FLAG_PSCI_OFF2 (1ULL << 0) |
| 491 | |
| 492 | /* run->fail_entry.hardware_entry_failure_reason codes. */ |
| 493 | #define KVM_EXIT_FAIL_ENTRY_CPU_UNSUPPORTED (1ULL << 0) |
| 494 | |
| 495 | enum kvm_smccc_filter_action { |
| 496 | KVM_SMCCC_FILTER_HANDLE = 0, |
| 497 | KVM_SMCCC_FILTER_DENY, |
| 498 | KVM_SMCCC_FILTER_FWD_TO_USER, |
| 499 | |
| 500 | }; |
| 501 | |
| 502 | struct kvm_smccc_filter { |
| 503 | __u32 base; |
| 504 | __u32 nr_functions; |
| 505 | __u8 action; |
| 506 | __u8 pad[15]; |
| 507 | }; |
| 508 | |
| 509 | /* arm64-specific KVM_EXIT_HYPERCALL flags */ |
| 510 | #define KVM_HYPERCALL_EXIT_SMC (1U << 0) |
| 511 | #define KVM_HYPERCALL_EXIT_16BIT (1U << 1) |
| 512 | |
| 513 | /* |
| 514 | * Get feature ID registers userspace writable mask. |
| 515 | * |
| 516 | * From DDI0487J.a, D19.2.66 ("ID_AA64MMFR2_EL1, AArch64 Memory Model |
| 517 | * Feature Register 2"): |
| 518 | * |
| 519 | * "The Feature ID space is defined as the System register space in |
| 520 | * AArch64 with op0==3, op1=={0, 1, 3}, CRn==0, CRm=={0-7}, |
| 521 | * op2=={0-7}." |
| 522 | * |
| 523 | * This covers all currently known R/O registers that indicate |
| 524 | * anything useful feature wise, including the ID registers. |
| 525 | * |
| 526 | * If we ever need to introduce a new range, it will be described as |
| 527 | * such in the range field. |
| 528 | */ |
| 529 | #define KVM_ARM_FEATURE_ID_RANGE_IDX(op0, op1, crn, crm, op2) \ |
| 530 | ({ \ |
| 531 | __u64 __op1 = (op1) & 3; \ |
| 532 | __op1 -= (__op1 == 3); \ |
| 533 | (__op1 << 6 | ((crm) & 7) << 3 | (op2)); \ |
| 534 | }) |
| 535 | |
| 536 | #define KVM_ARM_FEATURE_ID_RANGE 0 |
| 537 | #define KVM_ARM_FEATURE_ID_RANGE_SIZE (3 * 8 * 8) |
| 538 | |
| 539 | struct reg_mask_range { |
| 540 | __u64 addr; /* Pointer to mask array */ |
| 541 | __u32 range; /* Requested range */ |
| 542 | __u32 reserved[13]; |
| 543 | }; |
| 544 | |
| 545 | #endif |
| 546 | |
| 547 | #endif /* __ARM_KVM_H__ */ |