| 1 | /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ |
| 2 | /* |
| 3 | * Copyright (C) 2019 Western Digital Corporation or its affiliates. |
| 4 | * |
| 5 | * Authors: |
| 6 | * Anup Patel <anup.patel@wdc.com> |
| 7 | */ |
| 8 | |
| 9 | #ifndef __LINUX_KVM_RISCV_H |
| 10 | #define __LINUX_KVM_RISCV_H |
| 11 | |
| 12 | #ifndef __ASSEMBLER__ |
| 13 | |
| 14 | #include <linux/types.h> |
| 15 | #include <asm/bitsperlong.h> |
| 16 | #include <asm/ptrace.h> |
| 17 | |
| 18 | #define __KVM_HAVE_IRQ_LINE |
| 19 | |
| 20 | #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 |
| 21 | #define KVM_DIRTY_LOG_PAGE_OFFSET 64 |
| 22 | |
| 23 | #define KVM_INTERRUPT_SET -1U |
| 24 | #define KVM_INTERRUPT_UNSET -2U |
| 25 | |
| 26 | #define KVM_EXIT_FAIL_ENTRY_NO_VSFILE (1ULL << 0) |
| 27 | |
| 28 | /* for KVM_GET_REGS and KVM_SET_REGS */ |
| 29 | struct kvm_regs { |
| 30 | }; |
| 31 | |
| 32 | /* for KVM_GET_FPU and KVM_SET_FPU */ |
| 33 | struct kvm_fpu { |
| 34 | }; |
| 35 | |
| 36 | /* KVM Debug exit structure */ |
| 37 | struct kvm_debug_exit_arch { |
| 38 | }; |
| 39 | |
| 40 | /* for KVM_SET_GUEST_DEBUG */ |
| 41 | struct kvm_guest_debug_arch { |
| 42 | }; |
| 43 | |
| 44 | /* definition of registers in kvm_run */ |
| 45 | struct kvm_sync_regs { |
| 46 | }; |
| 47 | |
| 48 | /* for KVM_GET_SREGS and KVM_SET_SREGS */ |
| 49 | struct kvm_sregs { |
| 50 | }; |
| 51 | |
| 52 | /* CONFIG registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ |
| 53 | struct kvm_riscv_config { |
| 54 | unsigned long isa; |
| 55 | unsigned long zicbom_block_size; |
| 56 | unsigned long mvendorid; |
| 57 | unsigned long marchid; |
| 58 | unsigned long mimpid; |
| 59 | unsigned long zicboz_block_size; |
| 60 | unsigned long satp_mode; |
| 61 | unsigned long zicbop_block_size; |
| 62 | }; |
| 63 | |
| 64 | /* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ |
| 65 | struct kvm_riscv_core { |
| 66 | struct user_regs_struct regs; |
| 67 | unsigned long mode; |
| 68 | }; |
| 69 | |
| 70 | /* Possible privilege modes for kvm_riscv_core */ |
| 71 | #define KVM_RISCV_MODE_S 1 |
| 72 | #define KVM_RISCV_MODE_U 0 |
| 73 | |
| 74 | /* General CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ |
| 75 | struct kvm_riscv_csr { |
| 76 | unsigned long sstatus; |
| 77 | unsigned long sie; |
| 78 | unsigned long stvec; |
| 79 | unsigned long sscratch; |
| 80 | unsigned long sepc; |
| 81 | unsigned long scause; |
| 82 | unsigned long stval; |
| 83 | unsigned long sip; |
| 84 | unsigned long satp; |
| 85 | unsigned long scounteren; |
| 86 | unsigned long senvcfg; |
| 87 | }; |
| 88 | |
| 89 | /* AIA CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ |
| 90 | struct kvm_riscv_aia_csr { |
| 91 | unsigned long siselect; |
| 92 | unsigned long iprio1; |
| 93 | unsigned long iprio2; |
| 94 | unsigned long sieh; |
| 95 | unsigned long siph; |
| 96 | unsigned long iprio1h; |
| 97 | unsigned long iprio2h; |
| 98 | }; |
| 99 | |
| 100 | /* Smstateen CSR for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ |
| 101 | struct kvm_riscv_smstateen_csr { |
| 102 | unsigned long sstateen0; |
| 103 | }; |
| 104 | |
| 105 | /* TIMER registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ |
| 106 | struct kvm_riscv_timer { |
| 107 | __u64 frequency; |
| 108 | __u64 time; |
| 109 | __u64 compare; |
| 110 | __u64 state; |
| 111 | }; |
| 112 | |
| 113 | /* Possible states for kvm_riscv_timer */ |
| 114 | #define KVM_RISCV_TIMER_STATE_OFF 0 |
| 115 | #define KVM_RISCV_TIMER_STATE_ON 1 |
| 116 | |
| 117 | /* |
| 118 | * ISA extension IDs specific to KVM. This is not the same as the host ISA |
| 119 | * extension IDs as that is internal to the host and should not be exposed |
| 120 | * to the guest. This should always be contiguous to keep the mapping simple |
| 121 | * in KVM implementation. |
| 122 | */ |
| 123 | enum KVM_RISCV_ISA_EXT_ID { |
| 124 | KVM_RISCV_ISA_EXT_A = 0, |
| 125 | KVM_RISCV_ISA_EXT_C, |
| 126 | KVM_RISCV_ISA_EXT_D, |
| 127 | KVM_RISCV_ISA_EXT_F, |
| 128 | KVM_RISCV_ISA_EXT_H, |
| 129 | KVM_RISCV_ISA_EXT_I, |
| 130 | KVM_RISCV_ISA_EXT_M, |
| 131 | KVM_RISCV_ISA_EXT_SVPBMT, |
| 132 | KVM_RISCV_ISA_EXT_SSTC, |
| 133 | KVM_RISCV_ISA_EXT_SVINVAL, |
| 134 | KVM_RISCV_ISA_EXT_ZIHINTPAUSE, |
| 135 | KVM_RISCV_ISA_EXT_ZICBOM, |
| 136 | KVM_RISCV_ISA_EXT_ZICBOZ, |
| 137 | KVM_RISCV_ISA_EXT_ZBB, |
| 138 | KVM_RISCV_ISA_EXT_SSAIA, |
| 139 | KVM_RISCV_ISA_EXT_V, |
| 140 | KVM_RISCV_ISA_EXT_SVNAPOT, |
| 141 | KVM_RISCV_ISA_EXT_ZBA, |
| 142 | KVM_RISCV_ISA_EXT_ZBS, |
| 143 | KVM_RISCV_ISA_EXT_ZICNTR, |
| 144 | KVM_RISCV_ISA_EXT_ZICSR, |
| 145 | KVM_RISCV_ISA_EXT_ZIFENCEI, |
| 146 | KVM_RISCV_ISA_EXT_ZIHPM, |
| 147 | KVM_RISCV_ISA_EXT_SMSTATEEN, |
| 148 | KVM_RISCV_ISA_EXT_ZICOND, |
| 149 | KVM_RISCV_ISA_EXT_ZBC, |
| 150 | KVM_RISCV_ISA_EXT_ZBKB, |
| 151 | KVM_RISCV_ISA_EXT_ZBKC, |
| 152 | KVM_RISCV_ISA_EXT_ZBKX, |
| 153 | KVM_RISCV_ISA_EXT_ZKND, |
| 154 | KVM_RISCV_ISA_EXT_ZKNE, |
| 155 | KVM_RISCV_ISA_EXT_ZKNH, |
| 156 | KVM_RISCV_ISA_EXT_ZKR, |
| 157 | KVM_RISCV_ISA_EXT_ZKSED, |
| 158 | KVM_RISCV_ISA_EXT_ZKSH, |
| 159 | KVM_RISCV_ISA_EXT_ZKT, |
| 160 | KVM_RISCV_ISA_EXT_ZVBB, |
| 161 | KVM_RISCV_ISA_EXT_ZVBC, |
| 162 | KVM_RISCV_ISA_EXT_ZVKB, |
| 163 | KVM_RISCV_ISA_EXT_ZVKG, |
| 164 | KVM_RISCV_ISA_EXT_ZVKNED, |
| 165 | KVM_RISCV_ISA_EXT_ZVKNHA, |
| 166 | KVM_RISCV_ISA_EXT_ZVKNHB, |
| 167 | KVM_RISCV_ISA_EXT_ZVKSED, |
| 168 | KVM_RISCV_ISA_EXT_ZVKSH, |
| 169 | KVM_RISCV_ISA_EXT_ZVKT, |
| 170 | KVM_RISCV_ISA_EXT_ZFH, |
| 171 | KVM_RISCV_ISA_EXT_ZFHMIN, |
| 172 | KVM_RISCV_ISA_EXT_ZIHINTNTL, |
| 173 | KVM_RISCV_ISA_EXT_ZVFH, |
| 174 | KVM_RISCV_ISA_EXT_ZVFHMIN, |
| 175 | KVM_RISCV_ISA_EXT_ZFA, |
| 176 | KVM_RISCV_ISA_EXT_ZTSO, |
| 177 | KVM_RISCV_ISA_EXT_ZACAS, |
| 178 | KVM_RISCV_ISA_EXT_SSCOFPMF, |
| 179 | KVM_RISCV_ISA_EXT_ZIMOP, |
| 180 | KVM_RISCV_ISA_EXT_ZCA, |
| 181 | KVM_RISCV_ISA_EXT_ZCB, |
| 182 | KVM_RISCV_ISA_EXT_ZCD, |
| 183 | KVM_RISCV_ISA_EXT_ZCF, |
| 184 | KVM_RISCV_ISA_EXT_ZCMOP, |
| 185 | KVM_RISCV_ISA_EXT_ZAWRS, |
| 186 | KVM_RISCV_ISA_EXT_SMNPM, |
| 187 | KVM_RISCV_ISA_EXT_SSNPM, |
| 188 | KVM_RISCV_ISA_EXT_SVADE, |
| 189 | KVM_RISCV_ISA_EXT_SVADU, |
| 190 | KVM_RISCV_ISA_EXT_SVVPTC, |
| 191 | KVM_RISCV_ISA_EXT_ZABHA, |
| 192 | KVM_RISCV_ISA_EXT_ZICCRSE, |
| 193 | KVM_RISCV_ISA_EXT_ZAAMO, |
| 194 | KVM_RISCV_ISA_EXT_ZALRSC, |
| 195 | KVM_RISCV_ISA_EXT_ZICBOP, |
| 196 | KVM_RISCV_ISA_EXT_ZFBFMIN, |
| 197 | KVM_RISCV_ISA_EXT_ZVFBFMIN, |
| 198 | KVM_RISCV_ISA_EXT_ZVFBFWMA, |
| 199 | KVM_RISCV_ISA_EXT_ZCLSD, |
| 200 | KVM_RISCV_ISA_EXT_ZILSD, |
| 201 | KVM_RISCV_ISA_EXT_ZALASR, |
| 202 | KVM_RISCV_ISA_EXT_MAX, |
| 203 | }; |
| 204 | |
| 205 | /* |
| 206 | * SBI extension IDs specific to KVM. This is not the same as the SBI |
| 207 | * extension IDs defined by the RISC-V SBI specification. |
| 208 | */ |
| 209 | enum KVM_RISCV_SBI_EXT_ID { |
| 210 | KVM_RISCV_SBI_EXT_V01 = 0, |
| 211 | KVM_RISCV_SBI_EXT_TIME, |
| 212 | KVM_RISCV_SBI_EXT_IPI, |
| 213 | KVM_RISCV_SBI_EXT_RFENCE, |
| 214 | KVM_RISCV_SBI_EXT_SRST, |
| 215 | KVM_RISCV_SBI_EXT_HSM, |
| 216 | KVM_RISCV_SBI_EXT_PMU, |
| 217 | KVM_RISCV_SBI_EXT_EXPERIMENTAL, |
| 218 | KVM_RISCV_SBI_EXT_VENDOR, |
| 219 | KVM_RISCV_SBI_EXT_DBCN, |
| 220 | KVM_RISCV_SBI_EXT_STA, |
| 221 | KVM_RISCV_SBI_EXT_SUSP, |
| 222 | KVM_RISCV_SBI_EXT_FWFT, |
| 223 | KVM_RISCV_SBI_EXT_MPXY, |
| 224 | KVM_RISCV_SBI_EXT_MAX, |
| 225 | }; |
| 226 | |
| 227 | /* SBI STA extension registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ |
| 228 | struct kvm_riscv_sbi_sta { |
| 229 | unsigned long shmem_lo; |
| 230 | unsigned long shmem_hi; |
| 231 | }; |
| 232 | |
| 233 | struct kvm_riscv_sbi_fwft_feature { |
| 234 | unsigned long enable; |
| 235 | unsigned long flags; |
| 236 | unsigned long value; |
| 237 | }; |
| 238 | |
| 239 | /* SBI FWFT extension registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ |
| 240 | struct kvm_riscv_sbi_fwft { |
| 241 | struct kvm_riscv_sbi_fwft_feature misaligned_deleg; |
| 242 | struct kvm_riscv_sbi_fwft_feature pointer_masking; |
| 243 | }; |
| 244 | |
| 245 | /* If you need to interpret the index values, here is the key: */ |
| 246 | #define KVM_REG_RISCV_TYPE_MASK 0x00000000FF000000 |
| 247 | #define KVM_REG_RISCV_TYPE_SHIFT 24 |
| 248 | #define KVM_REG_RISCV_SUBTYPE_MASK 0x0000000000FF0000 |
| 249 | #define KVM_REG_RISCV_SUBTYPE_SHIFT 16 |
| 250 | |
| 251 | /* Config registers are mapped as type 1 */ |
| 252 | #define KVM_REG_RISCV_CONFIG (0x01 << KVM_REG_RISCV_TYPE_SHIFT) |
| 253 | #define KVM_REG_RISCV_CONFIG_REG(name) \ |
| 254 | (offsetof(struct kvm_riscv_config, name) / sizeof(unsigned long)) |
| 255 | |
| 256 | /* Core registers are mapped as type 2 */ |
| 257 | #define KVM_REG_RISCV_CORE (0x02 << KVM_REG_RISCV_TYPE_SHIFT) |
| 258 | #define KVM_REG_RISCV_CORE_REG(name) \ |
| 259 | (offsetof(struct kvm_riscv_core, name) / sizeof(unsigned long)) |
| 260 | |
| 261 | /* Control and status registers are mapped as type 3 */ |
| 262 | #define KVM_REG_RISCV_CSR (0x03 << KVM_REG_RISCV_TYPE_SHIFT) |
| 263 | #define KVM_REG_RISCV_CSR_GENERAL (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT) |
| 264 | #define KVM_REG_RISCV_CSR_AIA (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT) |
| 265 | #define KVM_REG_RISCV_CSR_SMSTATEEN (0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT) |
| 266 | #define KVM_REG_RISCV_CSR_REG(name) \ |
| 267 | (offsetof(struct kvm_riscv_csr, name) / sizeof(unsigned long)) |
| 268 | #define KVM_REG_RISCV_CSR_AIA_REG(name) \ |
| 269 | (offsetof(struct kvm_riscv_aia_csr, name) / sizeof(unsigned long)) |
| 270 | #define KVM_REG_RISCV_CSR_SMSTATEEN_REG(name) \ |
| 271 | (offsetof(struct kvm_riscv_smstateen_csr, name) / sizeof(unsigned long)) |
| 272 | |
| 273 | /* Timer registers are mapped as type 4 */ |
| 274 | #define KVM_REG_RISCV_TIMER (0x04 << KVM_REG_RISCV_TYPE_SHIFT) |
| 275 | #define KVM_REG_RISCV_TIMER_REG(name) \ |
| 276 | (offsetof(struct kvm_riscv_timer, name) / sizeof(__u64)) |
| 277 | |
| 278 | /* F extension registers are mapped as type 5 */ |
| 279 | #define KVM_REG_RISCV_FP_F (0x05 << KVM_REG_RISCV_TYPE_SHIFT) |
| 280 | #define KVM_REG_RISCV_FP_F_REG(name) \ |
| 281 | (offsetof(struct __riscv_f_ext_state, name) / sizeof(__u32)) |
| 282 | |
| 283 | /* D extension registers are mapped as type 6 */ |
| 284 | #define KVM_REG_RISCV_FP_D (0x06 << KVM_REG_RISCV_TYPE_SHIFT) |
| 285 | #define KVM_REG_RISCV_FP_D_REG(name) \ |
| 286 | (offsetof(struct __riscv_d_ext_state, name) / sizeof(__u64)) |
| 287 | |
| 288 | /* ISA Extension registers are mapped as type 7 */ |
| 289 | #define KVM_REG_RISCV_ISA_EXT (0x07 << KVM_REG_RISCV_TYPE_SHIFT) |
| 290 | #define KVM_REG_RISCV_ISA_SINGLE (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT) |
| 291 | #define KVM_REG_RISCV_ISA_MULTI_EN (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT) |
| 292 | #define KVM_REG_RISCV_ISA_MULTI_DIS (0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT) |
| 293 | #define KVM_REG_RISCV_ISA_MULTI_REG(__ext_id) \ |
| 294 | ((__ext_id) / __BITS_PER_LONG) |
| 295 | #define KVM_REG_RISCV_ISA_MULTI_MASK(__ext_id) \ |
| 296 | (1UL << ((__ext_id) % __BITS_PER_LONG)) |
| 297 | #define KVM_REG_RISCV_ISA_MULTI_REG_LAST \ |
| 298 | KVM_REG_RISCV_ISA_MULTI_REG(KVM_RISCV_ISA_EXT_MAX - 1) |
| 299 | |
| 300 | /* SBI extension registers are mapped as type 8 */ |
| 301 | #define KVM_REG_RISCV_SBI_EXT (0x08 << KVM_REG_RISCV_TYPE_SHIFT) |
| 302 | #define KVM_REG_RISCV_SBI_SINGLE (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT) |
| 303 | #define KVM_REG_RISCV_SBI_MULTI_EN (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT) |
| 304 | #define KVM_REG_RISCV_SBI_MULTI_DIS (0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT) |
| 305 | #define KVM_REG_RISCV_SBI_MULTI_REG(__ext_id) \ |
| 306 | ((__ext_id) / __BITS_PER_LONG) |
| 307 | #define KVM_REG_RISCV_SBI_MULTI_MASK(__ext_id) \ |
| 308 | (1UL << ((__ext_id) % __BITS_PER_LONG)) |
| 309 | #define KVM_REG_RISCV_SBI_MULTI_REG_LAST \ |
| 310 | KVM_REG_RISCV_SBI_MULTI_REG(KVM_RISCV_SBI_EXT_MAX - 1) |
| 311 | |
| 312 | /* V extension registers are mapped as type 9 */ |
| 313 | #define KVM_REG_RISCV_VECTOR (0x09 << KVM_REG_RISCV_TYPE_SHIFT) |
| 314 | #define KVM_REG_RISCV_VECTOR_CSR_REG(name) \ |
| 315 | (offsetof(struct __riscv_v_ext_state, name) / sizeof(unsigned long)) |
| 316 | #define KVM_REG_RISCV_VECTOR_REG(n) \ |
| 317 | ((n) + sizeof(struct __riscv_v_ext_state) / sizeof(unsigned long)) |
| 318 | |
| 319 | /* Registers for specific SBI extensions are mapped as type 10 */ |
| 320 | #define KVM_REG_RISCV_SBI_STATE (0x0a << KVM_REG_RISCV_TYPE_SHIFT) |
| 321 | #define KVM_REG_RISCV_SBI_STA (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT) |
| 322 | #define KVM_REG_RISCV_SBI_STA_REG(name) \ |
| 323 | (offsetof(struct kvm_riscv_sbi_sta, name) / sizeof(unsigned long)) |
| 324 | #define KVM_REG_RISCV_SBI_FWFT (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT) |
| 325 | #define KVM_REG_RISCV_SBI_FWFT_REG(name) \ |
| 326 | (offsetof(struct kvm_riscv_sbi_fwft, name) / sizeof(unsigned long)) |
| 327 | |
| 328 | /* Device Control API: RISC-V AIA */ |
| 329 | #define KVM_DEV_RISCV_APLIC_ALIGN 0x1000 |
| 330 | #define KVM_DEV_RISCV_APLIC_SIZE 0x4000 |
| 331 | #define KVM_DEV_RISCV_APLIC_MAX_HARTS 0x4000 |
| 332 | #define KVM_DEV_RISCV_IMSIC_ALIGN 0x1000 |
| 333 | #define KVM_DEV_RISCV_IMSIC_SIZE 0x1000 |
| 334 | |
| 335 | #define KVM_DEV_RISCV_AIA_GRP_CONFIG 0 |
| 336 | #define KVM_DEV_RISCV_AIA_CONFIG_MODE 0 |
| 337 | #define KVM_DEV_RISCV_AIA_CONFIG_IDS 1 |
| 338 | #define KVM_DEV_RISCV_AIA_CONFIG_SRCS 2 |
| 339 | #define KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS 3 |
| 340 | #define KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT 4 |
| 341 | #define KVM_DEV_RISCV_AIA_CONFIG_HART_BITS 5 |
| 342 | #define KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS 6 |
| 343 | |
| 344 | /* |
| 345 | * Modes of RISC-V AIA device: |
| 346 | * 1) EMUL (aka Emulation): Trap-n-emulate IMSIC |
| 347 | * 2) HWACCEL (aka HW Acceleration): Virtualize IMSIC using IMSIC guest files |
| 348 | * 3) AUTO (aka Automatic): Virtualize IMSIC using IMSIC guest files whenever |
| 349 | * available otherwise fallback to trap-n-emulation |
| 350 | */ |
| 351 | #define KVM_DEV_RISCV_AIA_MODE_EMUL 0 |
| 352 | #define KVM_DEV_RISCV_AIA_MODE_HWACCEL 1 |
| 353 | #define KVM_DEV_RISCV_AIA_MODE_AUTO 2 |
| 354 | |
| 355 | #define KVM_DEV_RISCV_AIA_IDS_MIN 63 |
| 356 | #define KVM_DEV_RISCV_AIA_IDS_MAX 2048 |
| 357 | #define KVM_DEV_RISCV_AIA_SRCS_MAX 1024 |
| 358 | #define KVM_DEV_RISCV_AIA_GROUP_BITS_MAX 8 |
| 359 | #define KVM_DEV_RISCV_AIA_GROUP_SHIFT_MIN 24 |
| 360 | #define KVM_DEV_RISCV_AIA_GROUP_SHIFT_MAX 56 |
| 361 | #define KVM_DEV_RISCV_AIA_HART_BITS_MAX 16 |
| 362 | #define KVM_DEV_RISCV_AIA_GUEST_BITS_MAX 8 |
| 363 | |
| 364 | #define KVM_DEV_RISCV_AIA_GRP_ADDR 1 |
| 365 | #define KVM_DEV_RISCV_AIA_ADDR_APLIC 0 |
| 366 | #define KVM_DEV_RISCV_AIA_ADDR_IMSIC(__vcpu) (1 + (__vcpu)) |
| 367 | #define KVM_DEV_RISCV_AIA_ADDR_MAX \ |
| 368 | (1 + KVM_DEV_RISCV_APLIC_MAX_HARTS) |
| 369 | |
| 370 | #define KVM_DEV_RISCV_AIA_GRP_CTRL 2 |
| 371 | #define KVM_DEV_RISCV_AIA_CTRL_INIT 0 |
| 372 | |
| 373 | /* |
| 374 | * The device attribute type contains the memory mapped offset of the |
| 375 | * APLIC register (range 0x0000-0x3FFF) and it must be 4-byte aligned. |
| 376 | */ |
| 377 | #define KVM_DEV_RISCV_AIA_GRP_APLIC 3 |
| 378 | |
| 379 | /* |
| 380 | * The lower 12-bits of the device attribute type contains the iselect |
| 381 | * value of the IMSIC register (range 0x70-0xFF) whereas the higher order |
| 382 | * bits contains the VCPU id. |
| 383 | */ |
| 384 | #define KVM_DEV_RISCV_AIA_GRP_IMSIC 4 |
| 385 | #define KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS 12 |
| 386 | #define KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK \ |
| 387 | ((1U << KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS) - 1) |
| 388 | #define KVM_DEV_RISCV_AIA_IMSIC_MKATTR(__vcpu, __isel) \ |
| 389 | (((__vcpu) << KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS) | \ |
| 390 | ((__isel) & KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK)) |
| 391 | #define KVM_DEV_RISCV_AIA_IMSIC_GET_ISEL(__attr) \ |
| 392 | ((__attr) & KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK) |
| 393 | #define KVM_DEV_RISCV_AIA_IMSIC_GET_VCPU(__attr) \ |
| 394 | ((__attr) >> KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS) |
| 395 | |
| 396 | /* One single KVM irqchip, ie. the AIA */ |
| 397 | #define KVM_NR_IRQCHIPS 1 |
| 398 | |
| 399 | #endif |
| 400 | |
| 401 | #endif /* __LINUX_KVM_RISCV_H */ |