| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
| 3 | #include "qemu/osdep.h" |
| 4 | #include "qapi/error.h" |
| 5 | #include "qemu.h" |
| 6 | #include "loader.h" |
| 7 | #include "target/arm/cpu-features.h" |
| 8 | #include "target_elf.h" |
| 9 | #include "elf.h" |
| 10 | |
| 11 | |
| 12 | const char *get_elf_cpu_model(uint32_t eflags) |
| 13 | { |
| 14 | return "any"; |
| 15 | } |
| 16 | |
| 17 | enum { |
| 18 | ARM_HWCAP_A64_FP = 1 << 0, |
| 19 | ARM_HWCAP_A64_ASIMD = 1 << 1, |
| 20 | ARM_HWCAP_A64_EVTSTRM = 1 << 2, |
| 21 | ARM_HWCAP_A64_AES = 1 << 3, |
| 22 | ARM_HWCAP_A64_PMULL = 1 << 4, |
| 23 | ARM_HWCAP_A64_SHA1 = 1 << 5, |
| 24 | ARM_HWCAP_A64_SHA2 = 1 << 6, |
| 25 | ARM_HWCAP_A64_CRC32 = 1 << 7, |
| 26 | ARM_HWCAP_A64_ATOMICS = 1 << 8, |
| 27 | ARM_HWCAP_A64_FPHP = 1 << 9, |
| 28 | ARM_HWCAP_A64_ASIMDHP = 1 << 10, |
| 29 | ARM_HWCAP_A64_CPUID = 1 << 11, |
| 30 | ARM_HWCAP_A64_ASIMDRDM = 1 << 12, |
| 31 | ARM_HWCAP_A64_JSCVT = 1 << 13, |
| 32 | ARM_HWCAP_A64_FCMA = 1 << 14, |
| 33 | ARM_HWCAP_A64_LRCPC = 1 << 15, |
| 34 | ARM_HWCAP_A64_DCPOP = 1 << 16, |
| 35 | ARM_HWCAP_A64_SHA3 = 1 << 17, |
| 36 | ARM_HWCAP_A64_SM3 = 1 << 18, |
| 37 | ARM_HWCAP_A64_SM4 = 1 << 19, |
| 38 | ARM_HWCAP_A64_ASIMDDP = 1 << 20, |
| 39 | ARM_HWCAP_A64_SHA512 = 1 << 21, |
| 40 | ARM_HWCAP_A64_SVE = 1 << 22, |
| 41 | ARM_HWCAP_A64_ASIMDFHM = 1 << 23, |
| 42 | ARM_HWCAP_A64_DIT = 1 << 24, |
| 43 | ARM_HWCAP_A64_USCAT = 1 << 25, |
| 44 | ARM_HWCAP_A64_ILRCPC = 1 << 26, |
| 45 | ARM_HWCAP_A64_FLAGM = 1 << 27, |
| 46 | ARM_HWCAP_A64_SSBS = 1 << 28, |
| 47 | ARM_HWCAP_A64_SB = 1 << 29, |
| 48 | ARM_HWCAP_A64_PACA = 1 << 30, |
| 49 | ARM_HWCAP_A64_PACG = 1ULL << 31, |
| 50 | ARM_HWCAP_A64_GCS = 1ULL << 32, |
| 51 | ARM_HWCAP_A64_CMPBR = 1ULL << 33, |
| 52 | ARM_HWCAP_A64_FPRCVT = 1ULL << 34, |
| 53 | ARM_HWCAP_A64_F8MM8 = 1ULL << 35, |
| 54 | ARM_HWCAP_A64_F8MM4 = 1ULL << 36, |
| 55 | ARM_HWCAP_A64_SVE_F16MM = 1ULL << 37, |
| 56 | ARM_HWCAP_A64_SVE_ELTPERM = 1ULL << 38, |
| 57 | ARM_HWCAP_A64_SVE_AES2 = 1ULL << 39, |
| 58 | ARM_HWCAP_A64_SVE_BFSCALE = 1ULL << 40, |
| 59 | ARM_HWCAP_A64_SVE2P2 = 1ULL << 41, |
| 60 | ARM_HWCAP_A64_SME2P2 = 1ULL << 42, |
| 61 | ARM_HWCAP_A64_SME_SBITPERM = 1ULL << 43, |
| 62 | ARM_HWCAP_A64_SME_AES = 1ULL << 44, |
| 63 | ARM_HWCAP_A64_SME_SFEXPA = 1ULL << 45, |
| 64 | ARM_HWCAP_A64_SME_STMOP = 1ULL << 46, |
| 65 | ARM_HWCAP_A64_SME_SMOP4 = 1ULL << 47, |
| 66 | |
| 67 | ARM_HWCAP2_A64_DCPODP = 1 << 0, |
| 68 | ARM_HWCAP2_A64_SVE2 = 1 << 1, |
| 69 | ARM_HWCAP2_A64_SVEAES = 1 << 2, |
| 70 | ARM_HWCAP2_A64_SVEPMULL = 1 << 3, |
| 71 | ARM_HWCAP2_A64_SVEBITPERM = 1 << 4, |
| 72 | ARM_HWCAP2_A64_SVESHA3 = 1 << 5, |
| 73 | ARM_HWCAP2_A64_SVESM4 = 1 << 6, |
| 74 | ARM_HWCAP2_A64_FLAGM2 = 1 << 7, |
| 75 | ARM_HWCAP2_A64_FRINT = 1 << 8, |
| 76 | ARM_HWCAP2_A64_SVEI8MM = 1 << 9, |
| 77 | ARM_HWCAP2_A64_SVEF32MM = 1 << 10, |
| 78 | ARM_HWCAP2_A64_SVEF64MM = 1 << 11, |
| 79 | ARM_HWCAP2_A64_SVEBF16 = 1 << 12, |
| 80 | ARM_HWCAP2_A64_I8MM = 1 << 13, |
| 81 | ARM_HWCAP2_A64_BF16 = 1 << 14, |
| 82 | ARM_HWCAP2_A64_DGH = 1 << 15, |
| 83 | ARM_HWCAP2_A64_RNG = 1 << 16, |
| 84 | ARM_HWCAP2_A64_BTI = 1 << 17, |
| 85 | ARM_HWCAP2_A64_MTE = 1 << 18, |
| 86 | ARM_HWCAP2_A64_ECV = 1 << 19, |
| 87 | ARM_HWCAP2_A64_AFP = 1 << 20, |
| 88 | ARM_HWCAP2_A64_RPRES = 1 << 21, |
| 89 | ARM_HWCAP2_A64_MTE3 = 1 << 22, |
| 90 | ARM_HWCAP2_A64_SME = 1 << 23, |
| 91 | ARM_HWCAP2_A64_SME_I16I64 = 1 << 24, |
| 92 | ARM_HWCAP2_A64_SME_F64F64 = 1 << 25, |
| 93 | ARM_HWCAP2_A64_SME_I8I32 = 1 << 26, |
| 94 | ARM_HWCAP2_A64_SME_F16F32 = 1 << 27, |
| 95 | ARM_HWCAP2_A64_SME_B16F32 = 1 << 28, |
| 96 | ARM_HWCAP2_A64_SME_F32F32 = 1 << 29, |
| 97 | ARM_HWCAP2_A64_SME_FA64 = 1 << 30, |
| 98 | ARM_HWCAP2_A64_WFXT = 1ULL << 31, |
| 99 | ARM_HWCAP2_A64_EBF16 = 1ULL << 32, |
| 100 | ARM_HWCAP2_A64_SVE_EBF16 = 1ULL << 33, |
| 101 | ARM_HWCAP2_A64_CSSC = 1ULL << 34, |
| 102 | ARM_HWCAP2_A64_RPRFM = 1ULL << 35, |
| 103 | ARM_HWCAP2_A64_SVE2P1 = 1ULL << 36, |
| 104 | ARM_HWCAP2_A64_SME2 = 1ULL << 37, |
| 105 | ARM_HWCAP2_A64_SME2P1 = 1ULL << 38, |
| 106 | ARM_HWCAP2_A64_SME_I16I32 = 1ULL << 39, |
| 107 | ARM_HWCAP2_A64_SME_BI32I32 = 1ULL << 40, |
| 108 | ARM_HWCAP2_A64_SME_B16B16 = 1ULL << 41, |
| 109 | ARM_HWCAP2_A64_SME_F16F16 = 1ULL << 42, |
| 110 | ARM_HWCAP2_A64_MOPS = 1ULL << 43, |
| 111 | ARM_HWCAP2_A64_HBC = 1ULL << 44, |
| 112 | ARM_HWCAP2_A64_SVE_B16B16 = 1ULL << 45, |
| 113 | ARM_HWCAP2_A64_LRCPC3 = 1ULL << 46, |
| 114 | ARM_HWCAP2_A64_LSE128 = 1ULL << 47, |
| 115 | ARM_HWCAP2_A64_FPMR = 1ULL << 48, |
| 116 | ARM_HWCAP2_A64_LUT = 1ULL << 49, |
| 117 | ARM_HWCAP2_A64_FAMINMAX = 1ULL << 50, |
| 118 | ARM_HWCAP2_A64_F8CVT = 1ULL << 51, |
| 119 | ARM_HWCAP2_A64_F8FMA = 1ULL << 52, |
| 120 | ARM_HWCAP2_A64_F8DP4 = 1ULL << 53, |
| 121 | ARM_HWCAP2_A64_F8DP2 = 1ULL << 54, |
| 122 | ARM_HWCAP2_A64_F8E4M3 = 1ULL << 55, |
| 123 | ARM_HWCAP2_A64_F8E5M2 = 1ULL << 56, |
| 124 | ARM_HWCAP2_A64_SME_LUTV2 = 1ULL << 57, |
| 125 | ARM_HWCAP2_A64_SME_F8F16 = 1ULL << 58, |
| 126 | ARM_HWCAP2_A64_SME_F8F32 = 1ULL << 59, |
| 127 | ARM_HWCAP2_A64_SME_SF8FMA = 1ULL << 60, |
| 128 | ARM_HWCAP2_A64_SME_SF8DP4 = 1ULL << 61, |
| 129 | ARM_HWCAP2_A64_SME_SF8DP2 = 1ULL << 62, |
| 130 | ARM_HWCAP2_A64_POE = 1ULL << 63, |
| 131 | }; |
| 132 | |
| 133 | #define GET_FEATURE_ID(feat, hwcap) \ |
| 134 | do { if (cpu_isar_feature(feat, cpu)) { hwcaps |= hwcap; } } while (0) |
| 135 | |
| 136 | abi_ulong get_elf_hwcap(CPUState *cs) |
| 137 | { |
| 138 | ARMCPU *cpu = ARM_CPU(cs); |
| 139 | abi_ulong hwcaps = 0; |
| 140 | |
| 141 | hwcaps |= ARM_HWCAP_A64_FP; |
| 142 | hwcaps |= ARM_HWCAP_A64_ASIMD; |
| 143 | hwcaps |= ARM_HWCAP_A64_CPUID; |
| 144 | |
| 145 | /* probe for the extra features */ |
| 146 | |
| 147 | GET_FEATURE_ID(aa64_aes, ARM_HWCAP_A64_AES); |
| 148 | GET_FEATURE_ID(aa64_pmull, ARM_HWCAP_A64_PMULL); |
| 149 | GET_FEATURE_ID(aa64_sha1, ARM_HWCAP_A64_SHA1); |
| 150 | GET_FEATURE_ID(aa64_sha256, ARM_HWCAP_A64_SHA2); |
| 151 | GET_FEATURE_ID(aa64_sha512, ARM_HWCAP_A64_SHA512); |
| 152 | GET_FEATURE_ID(aa64_crc32, ARM_HWCAP_A64_CRC32); |
| 153 | GET_FEATURE_ID(aa64_sha3, ARM_HWCAP_A64_SHA3); |
| 154 | GET_FEATURE_ID(aa64_sm3, ARM_HWCAP_A64_SM3); |
| 155 | GET_FEATURE_ID(aa64_sm4, ARM_HWCAP_A64_SM4); |
| 156 | GET_FEATURE_ID(aa64_fp16, ARM_HWCAP_A64_FPHP | ARM_HWCAP_A64_ASIMDHP); |
| 157 | GET_FEATURE_ID(aa64_lse, ARM_HWCAP_A64_ATOMICS); |
| 158 | GET_FEATURE_ID(aa64_lse2, ARM_HWCAP_A64_USCAT); |
| 159 | GET_FEATURE_ID(aa64_rdm, ARM_HWCAP_A64_ASIMDRDM); |
| 160 | GET_FEATURE_ID(aa64_dp, ARM_HWCAP_A64_ASIMDDP); |
| 161 | GET_FEATURE_ID(aa64_fcma, ARM_HWCAP_A64_FCMA); |
| 162 | GET_FEATURE_ID(aa64_sve, ARM_HWCAP_A64_SVE); |
| 163 | GET_FEATURE_ID(aa64_pauth, ARM_HWCAP_A64_PACA | ARM_HWCAP_A64_PACG); |
| 164 | GET_FEATURE_ID(aa64_fhm, ARM_HWCAP_A64_ASIMDFHM); |
| 165 | GET_FEATURE_ID(aa64_dit, ARM_HWCAP_A64_DIT); |
| 166 | GET_FEATURE_ID(aa64_jscvt, ARM_HWCAP_A64_JSCVT); |
| 167 | GET_FEATURE_ID(aa64_sb, ARM_HWCAP_A64_SB); |
| 168 | GET_FEATURE_ID(aa64_condm_4, ARM_HWCAP_A64_FLAGM); |
| 169 | GET_FEATURE_ID(aa64_dcpop, ARM_HWCAP_A64_DCPOP); |
| 170 | GET_FEATURE_ID(aa64_rcpc_8_3, ARM_HWCAP_A64_LRCPC); |
| 171 | GET_FEATURE_ID(aa64_rcpc_8_4, ARM_HWCAP_A64_ILRCPC); |
| 172 | GET_FEATURE_ID(aa64_gcs, ARM_HWCAP_A64_GCS); |
| 173 | GET_FEATURE_ID(aa64_cmpbr, ARM_HWCAP_A64_CMPBR); |
| 174 | GET_FEATURE_ID(aa64_f8mm8, ARM_HWCAP_A64_F8MM8); |
| 175 | GET_FEATURE_ID(aa64_f8mm4, ARM_HWCAP_A64_F8MM4); |
| 176 | GET_FEATURE_ID(aa64_ssve_aes, ARM_HWCAP_A64_SME_AES); |
| 177 | GET_FEATURE_ID(aa64_ssve_fexpa, ARM_HWCAP_A64_SME_SFEXPA); |
| 178 | GET_FEATURE_ID(aa64_fprcvt, ARM_HWCAP_A64_FPRCVT); |
| 179 | GET_FEATURE_ID(aa64_sme_mop4, ARM_HWCAP_A64_SME_SMOP4); |
| 180 | GET_FEATURE_ID(aa64_sme_tmop, ARM_HWCAP_A64_SME_STMOP); |
| 181 | GET_FEATURE_ID(aa64_sve2p2, ARM_HWCAP_A64_SVE2P2); |
| 182 | GET_FEATURE_ID(aa64_sme2p2, ARM_HWCAP_A64_SME2P2); |
| 183 | GET_FEATURE_ID(aa64_sve_bfscale, ARM_HWCAP_A64_SVE_BFSCALE); |
| 184 | GET_FEATURE_ID(aa64_ssve_bitperm, ARM_HWCAP_A64_SME_SBITPERM); |
| 185 | GET_FEATURE_ID(aa64_sve_aes2, ARM_HWCAP_A64_SVE_AES2); |
| 186 | |
| 187 | return hwcaps; |
| 188 | } |
| 189 | |
| 190 | abi_ulong get_elf_hwcap2(CPUState *cs) |
| 191 | { |
| 192 | ARMCPU *cpu = ARM_CPU(cs); |
| 193 | abi_ulong hwcaps = 0; |
| 194 | |
| 195 | GET_FEATURE_ID(aa64_dcpodp, ARM_HWCAP2_A64_DCPODP); |
| 196 | GET_FEATURE_ID(aa64_sve2, ARM_HWCAP2_A64_SVE2); |
| 197 | GET_FEATURE_ID(aa64_sve_aes, ARM_HWCAP2_A64_SVEAES); |
| 198 | GET_FEATURE_ID(aa64_sve_pmull128, ARM_HWCAP2_A64_SVEPMULL); |
| 199 | GET_FEATURE_ID(aa64_sve_bitperm, ARM_HWCAP2_A64_SVEBITPERM); |
| 200 | GET_FEATURE_ID(aa64_sve_sha3, ARM_HWCAP2_A64_SVESHA3); |
| 201 | GET_FEATURE_ID(aa64_sve_sm4, ARM_HWCAP2_A64_SVESM4); |
| 202 | GET_FEATURE_ID(aa64_condm_5, ARM_HWCAP2_A64_FLAGM2); |
| 203 | GET_FEATURE_ID(aa64_frint, ARM_HWCAP2_A64_FRINT); |
| 204 | GET_FEATURE_ID(aa64_sve_i8mm, ARM_HWCAP2_A64_SVEI8MM); |
| 205 | GET_FEATURE_ID(aa64_sve_f32mm, ARM_HWCAP2_A64_SVEF32MM); |
| 206 | GET_FEATURE_ID(aa64_sve_f64mm, ARM_HWCAP2_A64_SVEF64MM); |
| 207 | GET_FEATURE_ID(aa64_sve_bf16, ARM_HWCAP2_A64_SVEBF16); |
| 208 | GET_FEATURE_ID(aa64_i8mm, ARM_HWCAP2_A64_I8MM); |
| 209 | GET_FEATURE_ID(aa64_bf16, ARM_HWCAP2_A64_BF16); |
| 210 | GET_FEATURE_ID(aa64_rndr, ARM_HWCAP2_A64_RNG); |
| 211 | GET_FEATURE_ID(aa64_bti, ARM_HWCAP2_A64_BTI); |
| 212 | GET_FEATURE_ID(aa64_mte, ARM_HWCAP2_A64_MTE); |
| 213 | GET_FEATURE_ID(aa64_mte3, ARM_HWCAP2_A64_MTE3); |
| 214 | GET_FEATURE_ID(aa64_sme, (ARM_HWCAP2_A64_SME | |
| 215 | ARM_HWCAP2_A64_SME_F32F32 | |
| 216 | ARM_HWCAP2_A64_SME_B16F32 | |
| 217 | ARM_HWCAP2_A64_SME_F16F32 | |
| 218 | ARM_HWCAP2_A64_SME_I8I32)); |
| 219 | GET_FEATURE_ID(aa64_sme_f64f64, ARM_HWCAP2_A64_SME_F64F64); |
| 220 | GET_FEATURE_ID(aa64_sme_i16i64, ARM_HWCAP2_A64_SME_I16I64); |
| 221 | GET_FEATURE_ID(aa64_sme_fa64, ARM_HWCAP2_A64_SME_FA64); |
| 222 | GET_FEATURE_ID(aa64_hbc, ARM_HWCAP2_A64_HBC); |
| 223 | GET_FEATURE_ID(aa64_mops, ARM_HWCAP2_A64_MOPS); |
| 224 | GET_FEATURE_ID(aa64_sve2p1, ARM_HWCAP2_A64_SVE2P1); |
| 225 | GET_FEATURE_ID(aa64_sme2, (ARM_HWCAP2_A64_SME2 | |
| 226 | ARM_HWCAP2_A64_SME_I16I32 | |
| 227 | ARM_HWCAP2_A64_SME_BI32I32)); |
| 228 | GET_FEATURE_ID(aa64_sme2p1, ARM_HWCAP2_A64_SME2P1); |
| 229 | GET_FEATURE_ID(aa64_sme_b16b16, ARM_HWCAP2_A64_SME_B16B16); |
| 230 | GET_FEATURE_ID(aa64_sme_f16f16, ARM_HWCAP2_A64_SME_F16F16); |
| 231 | GET_FEATURE_ID(aa64_sve_b16b16, ARM_HWCAP2_A64_SVE_B16B16); |
| 232 | GET_FEATURE_ID(aa64_cssc, ARM_HWCAP2_A64_CSSC); |
| 233 | GET_FEATURE_ID(aa64_lse128, ARM_HWCAP2_A64_LSE128); |
| 234 | GET_FEATURE_ID(aa64_faminmax, ARM_HWCAP2_A64_FAMINMAX); |
| 235 | GET_FEATURE_ID(aa64_fpmr, ARM_HWCAP2_A64_FPMR); |
| 236 | GET_FEATURE_ID(aa64_lut, ARM_HWCAP2_A64_LUT); |
| 237 | GET_FEATURE_ID(aa64_sme2p1_lutv2, ARM_HWCAP2_A64_SME_LUTV2); |
| 238 | GET_FEATURE_ID(aa64_f8cvt, ARM_HWCAP2_A64_F8CVT | |
| 239 | ARM_HWCAP2_A64_F8E4M3 | |
| 240 | ARM_HWCAP2_A64_F8E5M2); |
| 241 | GET_FEATURE_ID(aa64_f8fma, ARM_HWCAP2_A64_F8FMA); |
| 242 | GET_FEATURE_ID(aa64_f8dp4, ARM_HWCAP2_A64_F8DP4); |
| 243 | GET_FEATURE_ID(aa64_f8dp2, ARM_HWCAP2_A64_F8DP2); |
| 244 | GET_FEATURE_ID(aa64_ssve_f8fma, ARM_HWCAP2_A64_SME_SF8FMA); |
| 245 | GET_FEATURE_ID(aa64_ssve_f8dp4, ARM_HWCAP2_A64_SME_SF8DP4); |
| 246 | GET_FEATURE_ID(aa64_ssve_f8dp2, ARM_HWCAP2_A64_SME_SF8DP2); |
| 247 | GET_FEATURE_ID(aa64_sme_f8f32, ARM_HWCAP2_A64_SME_F8F32); |
| 248 | GET_FEATURE_ID(aa64_sme_f8f16, ARM_HWCAP2_A64_SME_F8F16); |
| 249 | |
| 250 | return hwcaps; |
| 251 | } |
| 252 | |
| 253 | const char *elf_hwcap_str(uint32_t bit) |
| 254 | { |
| 255 | static const char * const hwcap_str[] = { |
| 256 | [__builtin_ctz(ARM_HWCAP_A64_FP )] = "fp", |
| 257 | [__builtin_ctz(ARM_HWCAP_A64_ASIMD )] = "asimd", |
| 258 | [__builtin_ctz(ARM_HWCAP_A64_EVTSTRM )] = "evtstrm", |
| 259 | [__builtin_ctz(ARM_HWCAP_A64_AES )] = "aes", |
| 260 | [__builtin_ctz(ARM_HWCAP_A64_PMULL )] = "pmull", |
| 261 | [__builtin_ctz(ARM_HWCAP_A64_SHA1 )] = "sha1", |
| 262 | [__builtin_ctz(ARM_HWCAP_A64_SHA2 )] = "sha2", |
| 263 | [__builtin_ctz(ARM_HWCAP_A64_CRC32 )] = "crc32", |
| 264 | [__builtin_ctz(ARM_HWCAP_A64_ATOMICS )] = "atomics", |
| 265 | [__builtin_ctz(ARM_HWCAP_A64_FPHP )] = "fphp", |
| 266 | [__builtin_ctz(ARM_HWCAP_A64_ASIMDHP )] = "asimdhp", |
| 267 | [__builtin_ctz(ARM_HWCAP_A64_CPUID )] = "cpuid", |
| 268 | [__builtin_ctz(ARM_HWCAP_A64_ASIMDRDM)] = "asimdrdm", |
| 269 | [__builtin_ctz(ARM_HWCAP_A64_JSCVT )] = "jscvt", |
| 270 | [__builtin_ctz(ARM_HWCAP_A64_FCMA )] = "fcma", |
| 271 | [__builtin_ctz(ARM_HWCAP_A64_LRCPC )] = "lrcpc", |
| 272 | [__builtin_ctz(ARM_HWCAP_A64_DCPOP )] = "dcpop", |
| 273 | [__builtin_ctz(ARM_HWCAP_A64_SHA3 )] = "sha3", |
| 274 | [__builtin_ctz(ARM_HWCAP_A64_SM3 )] = "sm3", |
| 275 | [__builtin_ctz(ARM_HWCAP_A64_SM4 )] = "sm4", |
| 276 | [__builtin_ctz(ARM_HWCAP_A64_ASIMDDP )] = "asimddp", |
| 277 | [__builtin_ctz(ARM_HWCAP_A64_SHA512 )] = "sha512", |
| 278 | [__builtin_ctz(ARM_HWCAP_A64_SVE )] = "sve", |
| 279 | [__builtin_ctz(ARM_HWCAP_A64_ASIMDFHM)] = "asimdfhm", |
| 280 | [__builtin_ctz(ARM_HWCAP_A64_DIT )] = "dit", |
| 281 | [__builtin_ctz(ARM_HWCAP_A64_USCAT )] = "uscat", |
| 282 | [__builtin_ctz(ARM_HWCAP_A64_ILRCPC )] = "ilrcpc", |
| 283 | [__builtin_ctz(ARM_HWCAP_A64_FLAGM )] = "flagm", |
| 284 | [__builtin_ctz(ARM_HWCAP_A64_SSBS )] = "ssbs", |
| 285 | [__builtin_ctz(ARM_HWCAP_A64_SB )] = "sb", |
| 286 | [__builtin_ctz(ARM_HWCAP_A64_PACA )] = "paca", |
| 287 | [__builtin_ctz(ARM_HWCAP_A64_PACG )] = "pacg", |
| 288 | [__builtin_ctzll(ARM_HWCAP_A64_GCS )] = "gcs", |
| 289 | [__builtin_ctzll(ARM_HWCAP_A64_CMPBR )] = "cmpbr", |
| 290 | [__builtin_ctzll(ARM_HWCAP_A64_FPRCVT)] = "fprcvt", |
| 291 | [__builtin_ctzll(ARM_HWCAP_A64_F8MM8 )] = "f8mm8", |
| 292 | [__builtin_ctzll(ARM_HWCAP_A64_F8MM4 )] = "f8mm4", |
| 293 | [__builtin_ctzll(ARM_HWCAP_A64_SVE_F16MM)] = "svef16mm", |
| 294 | [__builtin_ctzll(ARM_HWCAP_A64_SVE_ELTPERM)] = "sveeltperm", |
| 295 | [__builtin_ctzll(ARM_HWCAP_A64_SVE_AES2)] = "sveaes2", |
| 296 | [__builtin_ctzll(ARM_HWCAP_A64_SVE_BFSCALE)] = "svebfscale", |
| 297 | [__builtin_ctzll(ARM_HWCAP_A64_SVE2P2)] = "sve2p2", |
| 298 | [__builtin_ctzll(ARM_HWCAP_A64_SME2P2)] = "sme2p2", |
| 299 | [__builtin_ctzll(ARM_HWCAP_A64_SME_SBITPERM)] = "smesbitperm", |
| 300 | [__builtin_ctzll(ARM_HWCAP_A64_SME_AES)] = "smeaes", |
| 301 | [__builtin_ctzll(ARM_HWCAP_A64_SME_SFEXPA)] = "smesfexpa", |
| 302 | [__builtin_ctzll(ARM_HWCAP_A64_SME_STMOP)] = "smestmop", |
| 303 | [__builtin_ctzll(ARM_HWCAP_A64_SME_SMOP4)] = "smesmop4", |
| 304 | }; |
| 305 | |
| 306 | return bit < ARRAY_SIZE(hwcap_str) ? hwcap_str[bit] : NULL; |
| 307 | } |
| 308 | |
| 309 | const char *elf_hwcap2_str(uint32_t bit) |
| 310 | { |
| 311 | static const char * const hwcap_str[] = { |
| 312 | [__builtin_ctz(ARM_HWCAP2_A64_DCPODP )] = "dcpodp", |
| 313 | [__builtin_ctz(ARM_HWCAP2_A64_SVE2 )] = "sve2", |
| 314 | [__builtin_ctz(ARM_HWCAP2_A64_SVEAES )] = "sveaes", |
| 315 | [__builtin_ctz(ARM_HWCAP2_A64_SVEPMULL )] = "svepmull", |
| 316 | [__builtin_ctz(ARM_HWCAP2_A64_SVEBITPERM )] = "svebitperm", |
| 317 | [__builtin_ctz(ARM_HWCAP2_A64_SVESHA3 )] = "svesha3", |
| 318 | [__builtin_ctz(ARM_HWCAP2_A64_SVESM4 )] = "svesm4", |
| 319 | [__builtin_ctz(ARM_HWCAP2_A64_FLAGM2 )] = "flagm2", |
| 320 | [__builtin_ctz(ARM_HWCAP2_A64_FRINT )] = "frint", |
| 321 | [__builtin_ctz(ARM_HWCAP2_A64_SVEI8MM )] = "svei8mm", |
| 322 | [__builtin_ctz(ARM_HWCAP2_A64_SVEF32MM )] = "svef32mm", |
| 323 | [__builtin_ctz(ARM_HWCAP2_A64_SVEF64MM )] = "svef64mm", |
| 324 | [__builtin_ctz(ARM_HWCAP2_A64_SVEBF16 )] = "svebf16", |
| 325 | [__builtin_ctz(ARM_HWCAP2_A64_I8MM )] = "i8mm", |
| 326 | [__builtin_ctz(ARM_HWCAP2_A64_BF16 )] = "bf16", |
| 327 | [__builtin_ctz(ARM_HWCAP2_A64_DGH )] = "dgh", |
| 328 | [__builtin_ctz(ARM_HWCAP2_A64_RNG )] = "rng", |
| 329 | [__builtin_ctz(ARM_HWCAP2_A64_BTI )] = "bti", |
| 330 | [__builtin_ctz(ARM_HWCAP2_A64_MTE )] = "mte", |
| 331 | [__builtin_ctz(ARM_HWCAP2_A64_ECV )] = "ecv", |
| 332 | [__builtin_ctz(ARM_HWCAP2_A64_AFP )] = "afp", |
| 333 | [__builtin_ctz(ARM_HWCAP2_A64_RPRES )] = "rpres", |
| 334 | [__builtin_ctz(ARM_HWCAP2_A64_MTE3 )] = "mte3", |
| 335 | [__builtin_ctz(ARM_HWCAP2_A64_SME )] = "sme", |
| 336 | [__builtin_ctz(ARM_HWCAP2_A64_SME_I16I64 )] = "smei16i64", |
| 337 | [__builtin_ctz(ARM_HWCAP2_A64_SME_F64F64 )] = "smef64f64", |
| 338 | [__builtin_ctz(ARM_HWCAP2_A64_SME_I8I32 )] = "smei8i32", |
| 339 | [__builtin_ctz(ARM_HWCAP2_A64_SME_F16F32 )] = "smef16f32", |
| 340 | [__builtin_ctz(ARM_HWCAP2_A64_SME_B16F32 )] = "smeb16f32", |
| 341 | [__builtin_ctz(ARM_HWCAP2_A64_SME_F32F32 )] = "smef32f32", |
| 342 | [__builtin_ctz(ARM_HWCAP2_A64_SME_FA64 )] = "smefa64", |
| 343 | [__builtin_ctz(ARM_HWCAP2_A64_WFXT )] = "wfxt", |
| 344 | [__builtin_ctzll(ARM_HWCAP2_A64_EBF16 )] = "ebf16", |
| 345 | [__builtin_ctzll(ARM_HWCAP2_A64_SVE_EBF16 )] = "sveebf16", |
| 346 | [__builtin_ctzll(ARM_HWCAP2_A64_CSSC )] = "cssc", |
| 347 | [__builtin_ctzll(ARM_HWCAP2_A64_RPRFM )] = "rprfm", |
| 348 | [__builtin_ctzll(ARM_HWCAP2_A64_SVE2P1 )] = "sve2p1", |
| 349 | [__builtin_ctzll(ARM_HWCAP2_A64_SME2 )] = "sme2", |
| 350 | [__builtin_ctzll(ARM_HWCAP2_A64_SME2P1 )] = "sme2p1", |
| 351 | [__builtin_ctzll(ARM_HWCAP2_A64_SME_I16I32 )] = "smei16i32", |
| 352 | [__builtin_ctzll(ARM_HWCAP2_A64_SME_BI32I32)] = "smebi32i32", |
| 353 | [__builtin_ctzll(ARM_HWCAP2_A64_SME_B16B16 )] = "smeb16b16", |
| 354 | [__builtin_ctzll(ARM_HWCAP2_A64_SME_F16F16 )] = "smef16f16", |
| 355 | [__builtin_ctzll(ARM_HWCAP2_A64_MOPS )] = "mops", |
| 356 | [__builtin_ctzll(ARM_HWCAP2_A64_HBC )] = "hbc", |
| 357 | [__builtin_ctzll(ARM_HWCAP2_A64_SVE_B16B16 )] = "sveb16b16", |
| 358 | [__builtin_ctzll(ARM_HWCAP2_A64_LRCPC3 )] = "lrcpc3", |
| 359 | [__builtin_ctzll(ARM_HWCAP2_A64_LSE128 )] = "lse128", |
| 360 | [__builtin_ctzll(ARM_HWCAP2_A64_FPMR )] = "fpmr", |
| 361 | [__builtin_ctzll(ARM_HWCAP2_A64_LUT )] = "lut", |
| 362 | [__builtin_ctzll(ARM_HWCAP2_A64_FAMINMAX )] = "faminmax", |
| 363 | [__builtin_ctzll(ARM_HWCAP2_A64_F8CVT )] = "f8cvt", |
| 364 | [__builtin_ctzll(ARM_HWCAP2_A64_F8FMA )] = "f8fma", |
| 365 | [__builtin_ctzll(ARM_HWCAP2_A64_F8DP4 )] = "f8dp4", |
| 366 | [__builtin_ctzll(ARM_HWCAP2_A64_F8DP2 )] = "f8dp2", |
| 367 | [__builtin_ctzll(ARM_HWCAP2_A64_F8E4M3 )] = "f8e4m3", |
| 368 | [__builtin_ctzll(ARM_HWCAP2_A64_F8E5M2 )] = "f8e5m2", |
| 369 | [__builtin_ctzll(ARM_HWCAP2_A64_SME_LUTV2 )] = "smelutv2", |
| 370 | [__builtin_ctzll(ARM_HWCAP2_A64_SME_F8F16 )] = "smef8f16", |
| 371 | [__builtin_ctzll(ARM_HWCAP2_A64_SME_F8F32 )] = "smef8f32", |
| 372 | [__builtin_ctzll(ARM_HWCAP2_A64_SME_SF8DP4 )] = "smesf8dp4", |
| 373 | [__builtin_ctzll(ARM_HWCAP2_A64_SME_SF8DP2 )] = "smesf8dp2", |
| 374 | [__builtin_ctzll(ARM_HWCAP2_A64_POE )] = "poe", |
| 375 | }; |
| 376 | |
| 377 | return bit < ARRAY_SIZE(hwcap_str) ? hwcap_str[bit] : NULL; |
| 378 | } |
| 379 | |
| 380 | const char *get_elf_platform(CPUState *cs) |
| 381 | { |
| 382 | return TARGET_BIG_ENDIAN ? "aarch64_be" : "aarch64"; |
| 383 | } |
| 384 | |
| 385 | bool arch_parse_elf_property(uint32_t pr_type, uint32_t pr_datasz, |
| 386 | const uint32_t *data, |
| 387 | struct image_info *info, |
| 388 | Error **errp) |
| 389 | { |
| 390 | if (pr_type == GNU_PROPERTY_AARCH64_FEATURE_1_AND) { |
| 391 | if (pr_datasz != sizeof(uint32_t)) { |
| 392 | error_setg(errp, "Ill-formed GNU_PROPERTY_AARCH64_FEATURE_1_AND"); |
| 393 | return false; |
| 394 | } |
| 395 | /* We will extract GNU_PROPERTY_AARCH64_FEATURE_1_BTI later. */ |
| 396 | info->note_flags = *data; |
| 397 | } |
| 398 | return true; |
| 399 | } |
| 400 | |
| 401 | void elf_core_copy_regs(target_elf_gregset_t *r, const CPUARMState *env) |
| 402 | { |
| 403 | for (int i = 0; i < 31; i++) { |
| 404 | r->pt.regs[i] = tswap64(env->xregs[i]); |
| 405 | } |
| 406 | r->pt.sp = tswap64(env->xregs[31]); |
| 407 | r->pt.pc = tswap64(env->pc); |
| 408 | r->pt.pstate = tswap64(pstate_read((CPUARMState *)env)); |
| 409 | } |