| 1 | /* |
| 2 | * ARM MemTag convenience functions. |
| 3 | * |
| 4 | * This code is licensed under the GNU GPL v2 or later. |
| 5 | * |
| 6 | * SPDX-License-Identifier: LGPL-2.1-or-later |
| 7 | */ |
| 8 | |
| 9 | #include "qemu/osdep.h" |
| 10 | #include "qemu.h" |
| 11 | #include "mte_user_helper.h" |
| 12 | |
| 13 | void arm_set_tagged_addr_ctrl(CPUArchState *env, abi_long value) |
| 14 | { |
| 15 | /* |
| 16 | * Write PR_MTE_TCF to SCTLR_EL1[TCF0]. |
| 17 | * |
| 18 | * The kernel has a per-cpu configuration for the sysadmin, |
| 19 | * /sys/devices/system/cpu/cpu<N>/mte_tcf_preferred, |
| 20 | * which qemu does not implement. |
| 21 | * |
| 22 | * Because there is no performance difference between the modes, and |
| 23 | * because SYNC is most useful for debugging MTE errors, choose SYNC |
| 24 | * as the preferred mode. With this preference, and the way the API |
| 25 | * uses only two bits, there is no way for the program to select |
| 26 | * ASYMM mode. |
| 27 | */ |
| 28 | unsigned tcf = 0; |
| 29 | if (value & PR_MTE_TCF_SYNC) { |
| 30 | tcf = 1; |
| 31 | } else if (value & PR_MTE_TCF_ASYNC) { |
| 32 | tcf = 2; |
| 33 | } |
| 34 | env->cp15.sctlr_el[1] = deposit64(env->cp15.sctlr_el[1], 38, 2, tcf); |
| 35 | |
| 36 | /* |
| 37 | * If MTE_STORE_ONLY is enabled, set the corresponding sctlr_el1 bit |
| 38 | */ |
| 39 | if (value & PR_MTE_STORE_ONLY) { |
| 40 | env->cp15.sctlr_el[1] |= SCTLR_TCSO0; |
| 41 | } else { |
| 42 | env->cp15.sctlr_el[1] &= ~SCTLR_TCSO0; |
| 43 | } |
| 44 | } |