| 1 | /* |
| 2 | * ARM MemTag convenience functions. |
| 3 | * |
| 4 | * This code is licensed under the GNU GPL v2 or later. |
| 5 | * |
| 6 | * SPDX-License-Identifier: LGPL-2.1-or-later |
| 7 | */ |
| 8 | |
| 9 | #ifndef AARCH64_MTE_USER_HELPER_H |
| 10 | #define AARCH64_MTE USER_HELPER_H |
| 11 | |
| 12 | #include "user/abitypes.h" |
| 13 | |
| 14 | #ifndef PR_MTE_TCF_SHIFT |
| 15 | # define PR_MTE_TCF_SHIFT 1 |
| 16 | # define PR_MTE_TCF_NONE (0UL << PR_MTE_TCF_SHIFT) |
| 17 | # define PR_MTE_TCF_SYNC (1UL << PR_MTE_TCF_SHIFT) |
| 18 | # define PR_MTE_TCF_ASYNC (2UL << PR_MTE_TCF_SHIFT) |
| 19 | # define PR_MTE_TCF_MASK (3UL << PR_MTE_TCF_SHIFT) |
| 20 | # define PR_MTE_TAG_SHIFT 3 |
| 21 | # define PR_MTE_TAG_MASK (0xffffUL << PR_MTE_TAG_SHIFT) |
| 22 | #endif |
| 23 | #ifndef PR_MTE_STORE_ONLY |
| 24 | # define PR_MTE_STORE_ONLY (1UL << 19) |
| 25 | #endif |
| 26 | |
| 27 | /** |
| 28 | * arm_set_tagged_addr_ctrl - Set TCF0 and TCSO0 fields in SCTLR_EL1 register |
| 29 | * @env: The CPU environment |
| 30 | * @value: The value to be set for the Tag Check Fault and Tag Check Store Only |
| 31 | * in EL0 field. |
| 32 | * |
| 33 | * Only SYNC and ASYNC modes can be selected for TCF0. If ASYMM mode is given, |
| 34 | * the SYNC mode is selected instead. So, there is no way to set the ASYMM mode. |
| 35 | */ |
| 36 | void arm_set_tagged_addr_ctrl(CPUArchState *env, abi_long value); |
| 37 | |
| 38 | #endif /* AARCH64_MTE_USER_HELPER_H */ |